Lines Matching +full:pdc +full:- +full:ranges
1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
36 #include "pinctrl-msm.h"
43 * struct msm_pinctrl - state for a pinctrl-msm device
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
106 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
115 return pctrl->soc->ngroups; in msm_get_groups_count()
123 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
133 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
134 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
149 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
151 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
159 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
160 unsigned int irq = irq_find_mapping(gc->irq.domain, group); in msm_pinmux_set_mux()
162 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
163 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
169 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
170 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
172 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
173 if (g->funcs[i] == function) in msm_pinmux_set_mux()
177 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
178 return -EINVAL; in msm_pinmux_set_mux()
191 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
194 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
204 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
205 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
208 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
209 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
210 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
212 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
213 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
218 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
219 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
222 val |= i << g->mux_bit; in msm_pinmux_set_mux()
224 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
225 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
230 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
233 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
238 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
254 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
257 if (!g->nfuncs) in msm_pinmux_request_gpio()
260 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
285 *bit = g->pull_bit; in msm_config_reg()
287 if (g->i2c_pull_bit) in msm_config_reg()
288 *mask |= BIT(g->i2c_pull_bit) >> *bit; in msm_config_reg()
291 *bit = g->od_bit; in msm_config_reg()
295 *bit = g->drv_bit; in msm_config_reg()
301 *bit = g->oe_bit; in msm_config_reg()
305 return -ENOTSUPP; in msm_config_reg()
337 if (!gpiochip_line_is_valid(&pctrl->chip, group)) in msm_config_group_get()
338 return -EINVAL; in msm_config_group_get()
340 g = &pctrl->soc->groups[group]; in msm_config_group_get()
353 return -EINVAL; in msm_config_group_get()
358 return -EINVAL; in msm_config_group_get()
362 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
363 return -ENOTSUPP; in msm_config_group_get()
366 return -EINVAL; in msm_config_group_get()
370 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
372 else if (arg & BIT(g->i2c_pull_bit)) in msm_config_group_get()
377 return -EINVAL; in msm_config_group_get()
380 /* Pin is not open-drain */ in msm_config_group_get()
382 return -EINVAL; in msm_config_group_get()
391 return -EINVAL; in msm_config_group_get()
394 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
398 return -EINVAL; in msm_config_group_get()
401 return -ENOTSUPP; in msm_config_group_get()
425 g = &pctrl->soc->groups[group]; in msm_config_group_set()
444 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
445 return -ENOTSUPP; in msm_config_group_set()
450 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
452 else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) in msm_config_group_set()
453 arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; in msm_config_group_set()
463 arg = -1; in msm_config_group_set()
465 arg = (arg / 2) - 1; in msm_config_group_set()
469 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
472 val |= BIT(g->out_bit); in msm_config_group_set()
474 val &= ~BIT(g->out_bit); in msm_config_group_set()
476 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
484 * actually be a no-op. in msm_config_group_set()
496 * no-op. However, for historical reasons and to in msm_config_group_set()
502 * that "input-enable" and "input-disable" in a device in msm_config_group_set()
513 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
515 return -EINVAL; in msm_config_group_set()
518 /* Range-check user-supplied value */ in msm_config_group_set()
520 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
521 return -EINVAL; in msm_config_group_set()
524 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
529 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
548 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
550 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
553 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
556 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
568 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
570 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
574 val |= BIT(g->out_bit); in msm_gpio_direction_output()
576 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
580 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
583 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
594 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
598 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
608 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
611 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
621 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
623 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
627 val |= BIT(g->out_bit); in msm_gpio_set()
629 val &= ~BIT(g->out_bit); in msm_gpio_set()
632 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
671 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
675 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
676 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
677 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
678 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
680 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
681 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
684 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
686 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
689 seq_printf(s, " %-8s: egpio\n", g->grp.name); in msm_gpio_dbg_show_one()
693 seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
694 seq_printf(s, " %-4s func%d", str_high_low(val), func); in msm_gpio_dbg_show_one()
696 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
705 unsigned gpio = chip->base; in msm_gpio_dbg_show()
708 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
723 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
726 /* Remove driver-provided reserved GPIOs from valid_mask */ in msm_gpio_init_valid_mask()
730 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
731 return -EINVAL; in msm_gpio_init_valid_mask()
740 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
745 return -EINVAL; in msm_gpio_init_valid_mask()
749 return -ENOMEM; in msm_gpio_init_valid_mask()
751 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
753 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
777 /* For dual-edge interrupts in software, since some hardware has no
781 * settings of both-edge irq lines to try and catch the next edge.
784 * - the status bit goes high, indicating that an edge was caught, or
785 * - the input value of the gpio doesn't change during the attempt.
790 * The do-loop tries to sledge-hammer closed the timing hole between
791 * the initial value-read and the polarity-write - if the line value changes
806 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
809 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
812 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
816 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
817 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
829 if (d->parent_data) in msm_gpio_irq_mask()
832 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
835 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
837 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
845 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
854 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
861 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
863 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
866 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
868 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
879 if (d->parent_data) in msm_gpio_irq_unmask()
882 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
885 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
887 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
890 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
891 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
894 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
896 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
904 gpiochip_enable_irq(gc, d->hwirq); in msm_gpio_irq_enable()
906 if (d->parent_data) in msm_gpio_irq_enable()
909 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
918 if (d->parent_data) in msm_gpio_irq_disable()
921 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
924 gpiochip_disable_irq(gc, d->hwirq); in msm_gpio_irq_disable()
928 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
940 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
946 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
959 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
969 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
970 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
980 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
981 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
986 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
988 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
992 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
995 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1000 d = d->parent_data; in msm_gpio_irq_eoi()
1003 d->chip->irq_eoi(d); in msm_gpio_irq_eoi()
1013 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1014 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1028 g = &pctrl->soc->groups[i]; in msm_gpio_irq_init_valid_mask()
1030 if (g->intr_detection_width != 1 && in msm_gpio_irq_init_valid_mask()
1031 g->intr_detection_width != 2) in msm_gpio_irq_init_valid_mask()
1046 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1052 if (d->parent_data) in msm_gpio_irq_set_type()
1055 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1056 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1061 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1063 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1068 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1069 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1071 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1077 if (g->intr_target_width) in msm_gpio_irq_set_type()
1078 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); in msm_gpio_irq_set_type()
1080 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1081 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1085 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1086 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1090 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1092 d->hwirq); in msm_gpio_irq_set_type()
1095 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1096 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1106 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1107 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1108 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1109 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1112 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1113 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1116 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1117 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1120 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1121 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1126 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1129 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1130 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1131 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1134 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1135 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1138 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1141 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1142 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1147 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1159 * also still have a non-matching interrupt latched, so clear whenever in msm_gpio_irq_set_type()
1165 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1168 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1189 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1192 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1199 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_reqres()
1203 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1204 return -ENODEV; in msm_gpio_irq_reqres()
1206 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1209 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1211 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1212 dev_err(gc->parent, in msm_gpio_irq_reqres()
1214 d->hwirq); in msm_gpio_irq_reqres()
1215 ret = -EINVAL; in msm_gpio_irq_reqres()
1220 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() in msm_gpio_irq_reqres()
1224 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); in msm_gpio_irq_reqres()
1230 * the PDC HW. in msm_gpio_irq_reqres()
1234 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_reqres()
1237 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1240 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_reqres()
1241 intr_cfg |= BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_reqres()
1245 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1250 module_put(gc->owner); in msm_gpio_irq_reqres()
1258 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_relres()
1262 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_relres()
1265 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_relres()
1268 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_relres()
1269 intr_cfg &= ~BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_relres()
1273 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_relres()
1276 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1277 module_put(gc->owner); in msm_gpio_irq_relres()
1286 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1289 return -EINVAL; in msm_gpio_irq_set_affinity()
1297 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1300 return -EINVAL; in msm_gpio_irq_set_vcpu_affinity()
1319 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1320 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1322 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1323 generic_handle_domain_irq(gc->irq.domain, i); in msm_gpio_irq_handler()
1348 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1349 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1350 if (map->gpio == child) { in msm_gpio_wakeirq()
1351 *parent = map->wakeirq; in msm_gpio_wakeirq()
1361 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1364 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1392 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1397 return -EINVAL; in msm_gpio_init()
1399 chip = &pctrl->chip; in msm_gpio_init()
1400 chip->base = -1; in msm_gpio_init()
1401 chip->ngpio = ngpio; in msm_gpio_init()
1402 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1403 chip->parent = pctrl->dev; in msm_gpio_init()
1404 chip->owner = THIS_MODULE; in msm_gpio_init()
1406 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1408 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1410 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1413 if (!chip->irq.parent_domain) in msm_gpio_init()
1414 return -EPROBE_DEFER; in msm_gpio_init()
1415 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1420 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1421 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1422 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1423 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1427 girq = &chip->irq; in msm_gpio_init()
1429 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1430 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1431 girq->num_parents = 1; in msm_gpio_init()
1432 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1434 if (!girq->parents) in msm_gpio_init()
1435 return -ENOMEM; in msm_gpio_init()
1436 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1437 girq->handler = handle_bad_irq; in msm_gpio_init()
1438 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1439 girq->init_valid_mask = msm_gpio_irq_init_valid_mask; in msm_gpio_init()
1441 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); in msm_gpio_init()
1443 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1448 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1449 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1450 * If it is present, it takes care of adding the pin ranges in msm_gpio_init()
1454 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1457 if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1458 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1459 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1461 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1471 struct msm_pinctrl *pctrl = data->cb_data; in msm_ps_hold_restart()
1473 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1492 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1494 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1496 if (devm_register_sys_off_handler(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1501 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1513 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1520 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1537 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1539 return -ENOMEM; in msm_pinctrl_probe()
1541 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1542 pctrl->soc = soc_data; in msm_pinctrl_probe()
1543 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1544 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1545 pctrl->dev->of_node, in msm_pinctrl_probe()
1546 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1548 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1550 if (soc_data->tiles) { in msm_pinctrl_probe()
1551 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1553 soc_data->tiles[i]); in msm_pinctrl_probe()
1554 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1555 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1556 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1559 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1560 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1561 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1563 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1568 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1569 if (pctrl->irq < 0) in msm_pinctrl_probe()
1570 return pctrl->irq; in msm_pinctrl_probe()
1572 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1573 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1574 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1575 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1576 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1577 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1578 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1580 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1581 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1582 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1583 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1586 for (i = 0; i < soc_data->nfunctions; i++) { in msm_pinctrl_probe()
1587 func = &soc_data->functions[i]; in msm_pinctrl_probe()
1589 ret = pinmux_generic_add_pinfunction(pctrl->pctrl, func, NULL); in msm_pinctrl_probe()
1600 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()