86 			    const struct msm_pingroup *g) \
88 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
91 			      const struct msm_pingroup *g) \
93 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
103 				const struct msm_pingroup *g)  in MSM_ACCESSOR()
105 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;  in MSM_ACCESSOR()
107 	msm_writel_intr_status(val, pctrl, g);  in MSM_ACCESSOR()
190 	const struct msm_pingroup *g;  in msm_pinmux_set_mux()  local
195 	g = &pctrl->soc->groups[group];  in msm_pinmux_set_mux()
196 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);  in msm_pinmux_set_mux()
198 	for (i = 0; i < g->nfuncs; i++) {  in msm_pinmux_set_mux()
199 		if (g->funcs[i] == function)  in msm_pinmux_set_mux()
203 	if (WARN_ON(i == g->nfuncs))  in msm_pinmux_set_mux()
222 	val = msm_readl_ctl(pctrl, g);  in msm_pinmux_set_mux()
230 	if (i == gpio_func && (val & BIT(g->oe_bit)) &&  in msm_pinmux_set_mux()
232 		u32 io_val = msm_readl_io(pctrl, g);  in msm_pinmux_set_mux()
234 		if (io_val & BIT(g->in_bit)) {  in msm_pinmux_set_mux()
235 			if (!(io_val & BIT(g->out_bit)))  in msm_pinmux_set_mux()
236 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
238 			if (io_val & BIT(g->out_bit))  in msm_pinmux_set_mux()
239 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
244 		if (val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
245 			val &= ~BIT(g->egpio_enable);  in msm_pinmux_set_mux()
248 		val |= i << g->mux_bit;  in msm_pinmux_set_mux()
250 		if (egpio_func && val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
251 			val |= BIT(g->egpio_enable);  in msm_pinmux_set_mux()
254 	msm_writel_ctl(val, pctrl, g);  in msm_pinmux_set_mux()
267 			msm_ack_intr_status(pctrl, g);  in msm_pinmux_set_mux()
280 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];  in msm_pinmux_request_gpio()  local
283 	if (!g->nfuncs)  in msm_pinmux_request_gpio()
286 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);  in msm_pinmux_request_gpio()
299 			  const struct msm_pingroup *g,  in msm_config_reg()  argument
309 		*bit = g->pull_bit;  in msm_config_reg()
311 		if (g->i2c_pull_bit)  in msm_config_reg()
312 			*mask |= BIT(g->i2c_pull_bit) >> *bit;  in msm_config_reg()
315 		*bit = g->od_bit;  in msm_config_reg()
319 		*bit = g->drv_bit;  in msm_config_reg()
325 		*bit = g->oe_bit;  in msm_config_reg()
351 	const struct msm_pingroup *g;  in msm_config_group_get()  local
364 	g = &pctrl->soc->groups[group];  in msm_config_group_get()
366 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_get()
370 	val = msm_readl_ctl(pctrl, g);  in msm_config_group_get()
396 		else if (arg & BIT(g->i2c_pull_bit))  in msm_config_group_get()
417 		val = msm_readl_io(pctrl, g);  in msm_config_group_get()
418 		arg = !!(val & BIT(g->in_bit));  in msm_config_group_get()
438 	const struct msm_pingroup *g;  in msm_config_group_set()  local
449 	g = &pctrl->soc->groups[group];  in msm_config_group_set()
455 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_set()
476 			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)  in msm_config_group_set()
477 				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;  in msm_config_group_set()
494 			val = msm_readl_io(pctrl, g);  in msm_config_group_set()
496 				val |= BIT(g->out_bit);  in msm_config_group_set()
498 				val &= ~BIT(g->out_bit);  in msm_config_group_set()
499 			msm_writel_io(val, pctrl, g);  in msm_config_group_set()
549 		val = msm_readl_ctl(pctrl, g);  in msm_config_group_set()
552 		msm_writel_ctl(val, pctrl, g);  in msm_config_group_set()
567 	const struct msm_pingroup *g;  in msm_gpio_direction_input()  local
572 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_input()
576 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_input()
577 	val &= ~BIT(g->oe_bit);  in msm_gpio_direction_input()
578 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_input()
587 	const struct msm_pingroup *g;  in msm_gpio_direction_output()  local
592 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_output()
596 	val = msm_readl_io(pctrl, g);  in msm_gpio_direction_output()
598 		val |= BIT(g->out_bit);  in msm_gpio_direction_output()
600 		val &= ~BIT(g->out_bit);  in msm_gpio_direction_output()
601 	msm_writel_io(val, pctrl, g);  in msm_gpio_direction_output()
603 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_output()
604 	val |= BIT(g->oe_bit);  in msm_gpio_direction_output()
605 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_output()
615 	const struct msm_pingroup *g;  in msm_gpio_get_direction()  local
618 	g = &pctrl->soc->groups[offset];  in msm_gpio_get_direction()
620 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_get_direction()
622 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :  in msm_gpio_get_direction()
628 	const struct msm_pingroup *g;  in msm_gpio_get()  local
632 	g = &pctrl->soc->groups[offset];  in msm_gpio_get()
634 	val = msm_readl_io(pctrl, g);  in msm_gpio_get()
635 	return !!(val & BIT(g->in_bit));  in msm_gpio_get()
640 	const struct msm_pingroup *g;  in msm_gpio_set()  local
645 	g = &pctrl->soc->groups[offset];  in msm_gpio_set()
649 	val = msm_readl_io(pctrl, g);  in msm_gpio_set()
651 		val |= BIT(g->out_bit);  in msm_gpio_set()
653 		val &= ~BIT(g->out_bit);  in msm_gpio_set()
654 	msm_writel_io(val, pctrl, g);  in msm_gpio_set()
669 	const struct msm_pingroup *g;  in msm_gpio_dbg_show_one()  local
695 	g = &pctrl->soc->groups[offset];  in msm_gpio_dbg_show_one()
696 	ctl_reg = msm_readl_ctl(pctrl, g);  in msm_gpio_dbg_show_one()
697 	io_reg = msm_readl_io(pctrl, g);  in msm_gpio_dbg_show_one()
699 	is_out = !!(ctl_reg & BIT(g->oe_bit));  in msm_gpio_dbg_show_one()
700 	func = (ctl_reg >> g->mux_bit) & 7;  in msm_gpio_dbg_show_one()
701 	drive = (ctl_reg >> g->drv_bit) & 7;  in msm_gpio_dbg_show_one()
702 	pull = (ctl_reg >> g->pull_bit) & 3;  in msm_gpio_dbg_show_one()
704 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))  in msm_gpio_dbg_show_one()
705 		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));  in msm_gpio_dbg_show_one()
708 		val = !!(io_reg & BIT(g->out_bit));  in msm_gpio_dbg_show_one()
710 		val = !!(io_reg & BIT(g->in_bit));  in msm_gpio_dbg_show_one()
713 		seq_printf(s, " %-8s: egpio\n", g->grp.name);  in msm_gpio_dbg_show_one()
717 	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");  in msm_gpio_dbg_show_one()
822 					  const struct msm_pingroup *g,  in msm_gpio_update_dual_edge_pos()  argument
830 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
832 		pol = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_update_dual_edge_pos()
833 		pol ^= BIT(g->intr_polarity_bit);  in msm_gpio_update_dual_edge_pos()
834 		msm_writel_intr_cfg(pol, pctrl, g);  in msm_gpio_update_dual_edge_pos()
836 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
837 		intstat = msm_readl_intr_status(pctrl, g);  in msm_gpio_update_dual_edge_pos()
849 	const struct msm_pingroup *g;  in msm_gpio_irq_mask()  local
859 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_mask()
863 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_mask()
885 		val &= ~BIT(g->intr_raw_status_bit);  in msm_gpio_irq_mask()
887 	val &= ~BIT(g->intr_enable_bit);  in msm_gpio_irq_mask()
888 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_mask()
899 	const struct msm_pingroup *g;  in msm_gpio_irq_unmask()  local
909 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_unmask()
913 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_unmask()
914 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_unmask()
915 	val |= BIT(g->intr_enable_bit);  in msm_gpio_irq_unmask()
916 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_unmask()
964 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_update_dual_edge_parent()  local
970 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
983 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
1001 	const struct msm_pingroup *g;  in msm_gpio_irq_ack()  local
1010 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_ack()
1014 	msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_ack()
1017 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_ack()
1046 	const struct msm_pingroup *g;  in msm_gpio_irq_init_valid_mask()  local
1052 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_init_valid_mask()
1054 		if (g->intr_detection_width != 1 &&  in msm_gpio_irq_init_valid_mask()
1055 		    g->intr_detection_width != 2)  in msm_gpio_irq_init_valid_mask()
1064 	const struct msm_pingroup *g;  in msm_gpio_irq_set_type()  local
1085 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_set_type()
1092 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)  in msm_gpio_irq_set_type()
1101 	if (g->intr_target_width)  in msm_gpio_irq_set_type()
1102 		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);  in msm_gpio_irq_set_type()
1105 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;  in msm_gpio_irq_set_type()
1109 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1110 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1118 		val = msm_readl_intr_target(pctrl, g);  in msm_gpio_irq_set_type()
1119 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1120 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1121 		msm_writel_intr_target(val, pctrl, g);  in msm_gpio_irq_set_type()
1129 	val = oldval = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_set_type()
1130 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
1131 	if (g->intr_detection_width == 2) {  in msm_gpio_irq_set_type()
1132 		val &= ~(3 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1133 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1136 			val |= 1 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1137 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1140 			val |= 2 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1141 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1144 			val |= 3 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1145 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1150 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1153 	} else if (g->intr_detection_width == 1) {  in msm_gpio_irq_set_type()
1154 		val &= ~(1 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1155 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1158 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1159 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1162 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1165 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1166 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1171 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1177 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_set_type()
1187 		msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_set_type()
1190 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_set_type()
1223 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_reqres()  local
1258 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_reqres()
1263 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_reqres()
1264 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_reqres()
1265 			intr_cfg |= BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_reqres()
1266 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_reqres()
1282 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_relres()  local
1286 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_relres()
1291 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_relres()
1292 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_relres()
1293 			intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_relres()
1294 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_relres()
1330 	const struct msm_pingroup *g;  in msm_gpio_irq_handler()  local
1344 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_handler()
1345 		val = msm_readl_intr_status(pctrl, g);  in msm_gpio_irq_handler()
1346 		if (val & BIT(g->intr_status_bit)) {  in msm_gpio_irq_handler()