87 			    const struct msm_pingroup *g) \
89 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 			      const struct msm_pingroup *g) \
94 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 				const struct msm_pingroup *g)  in MSM_ACCESSOR()
106 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;  in MSM_ACCESSOR()
108 	msm_writel_intr_status(val, pctrl, g);  in MSM_ACCESSOR()
164 	const struct msm_pingroup *g;  in msm_pinmux_set_mux()  local
169 	g = &pctrl->soc->groups[group];  in msm_pinmux_set_mux()
170 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);  in msm_pinmux_set_mux()
172 	for (i = 0; i < g->nfuncs; i++) {  in msm_pinmux_set_mux()
173 		if (g->funcs[i] == function)  in msm_pinmux_set_mux()
177 	if (WARN_ON(i == g->nfuncs))  in msm_pinmux_set_mux()
196 	val = msm_readl_ctl(pctrl, g);  in msm_pinmux_set_mux()
204 	if (i == gpio_func && (val & BIT(g->oe_bit)) &&  in msm_pinmux_set_mux()
206 		u32 io_val = msm_readl_io(pctrl, g);  in msm_pinmux_set_mux()
208 		if (io_val & BIT(g->in_bit)) {  in msm_pinmux_set_mux()
209 			if (!(io_val & BIT(g->out_bit)))  in msm_pinmux_set_mux()
210 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
212 			if (io_val & BIT(g->out_bit))  in msm_pinmux_set_mux()
213 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
218 		if (val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
219 			val &= ~BIT(g->egpio_enable);  in msm_pinmux_set_mux()
222 		val |= i << g->mux_bit;  in msm_pinmux_set_mux()
224 		if (egpio_func && val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
225 			val |= BIT(g->egpio_enable);  in msm_pinmux_set_mux()
228 	msm_writel_ctl(val, pctrl, g);  in msm_pinmux_set_mux()
241 			msm_ack_intr_status(pctrl, g);  in msm_pinmux_set_mux()
254 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];  in msm_pinmux_request_gpio()  local
257 	if (!g->nfuncs)  in msm_pinmux_request_gpio()
260 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);  in msm_pinmux_request_gpio()
275 			  const struct msm_pingroup *g,  in msm_config_reg()  argument
285 		*bit = g->pull_bit;  in msm_config_reg()
287 		if (g->i2c_pull_bit)  in msm_config_reg()
288 			*mask |= BIT(g->i2c_pull_bit) >> *bit;  in msm_config_reg()
291 		*bit = g->od_bit;  in msm_config_reg()
292 		*mask = 1;  in msm_config_reg()
295 		*bit = g->drv_bit;  in msm_config_reg()
301 		*bit = g->oe_bit;  in msm_config_reg()
302 		*mask = 1;  in msm_config_reg()
312 #define MSM_PULL_DOWN		1
320 	return (val + 1) * 2;  in msm_regval_to_drive()
327 	const struct msm_pingroup *g;  in msm_config_group_get()  local
340 	g = &pctrl->soc->groups[group];  in msm_config_group_get()
342 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_get()
346 	val = msm_readl_ctl(pctrl, g);  in msm_config_group_get()
354 		arg = 1;  in msm_config_group_get()
359 		arg = 1;  in msm_config_group_get()
367 		arg = 1;  in msm_config_group_get()
372 		else if (arg & BIT(g->i2c_pull_bit))  in msm_config_group_get()
383 		arg = 1;  in msm_config_group_get()
393 		val = msm_readl_io(pctrl, g);  in msm_config_group_get()
394 		arg = !!(val & BIT(g->in_bit));  in msm_config_group_get()
414 	const struct msm_pingroup *g;  in msm_config_group_set()  local
425 	g = &pctrl->soc->groups[group];  in msm_config_group_set()
431 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_set()
452 			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)  in msm_config_group_set()
453 				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;  in msm_config_group_set()
458 			arg = 1;  in msm_config_group_set()
463 				arg = -1;  in msm_config_group_set()
465 				arg = (arg / 2) - 1;  in msm_config_group_set()
470 			val = msm_readl_io(pctrl, g);  in msm_config_group_set()
472 				val |= BIT(g->out_bit);  in msm_config_group_set()
474 				val &= ~BIT(g->out_bit);  in msm_config_group_set()
475 			msm_writel_io(val, pctrl, g);  in msm_config_group_set()
479 			arg = 1;  in msm_config_group_set()
525 		val = msm_readl_ctl(pctrl, g);  in msm_config_group_set()
528 		msm_writel_ctl(val, pctrl, g);  in msm_config_group_set()
543 	const struct msm_pingroup *g;  in msm_gpio_direction_input()  local
548 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_input()
552 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_input()
553 	val &= ~BIT(g->oe_bit);  in msm_gpio_direction_input()
554 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_input()
563 	const struct msm_pingroup *g;  in msm_gpio_direction_output()  local
568 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_output()
572 	val = msm_readl_io(pctrl, g);  in msm_gpio_direction_output()
574 		val |= BIT(g->out_bit);  in msm_gpio_direction_output()
576 		val &= ~BIT(g->out_bit);  in msm_gpio_direction_output()
577 	msm_writel_io(val, pctrl, g);  in msm_gpio_direction_output()
579 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_output()
580 	val |= BIT(g->oe_bit);  in msm_gpio_direction_output()
581 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_output()
591 	const struct msm_pingroup *g;  in msm_gpio_get_direction()  local
594 	g = &pctrl->soc->groups[offset];  in msm_gpio_get_direction()
596 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_get_direction()
598 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :  in msm_gpio_get_direction()
604 	const struct msm_pingroup *g;  in msm_gpio_get()  local
608 	g = &pctrl->soc->groups[offset];  in msm_gpio_get()
610 	val = msm_readl_io(pctrl, g);  in msm_gpio_get()
611 	return !!(val & BIT(g->in_bit));  in msm_gpio_get()
616 	const struct msm_pingroup *g;  in msm_gpio_set()  local
621 	g = &pctrl->soc->groups[offset];  in msm_gpio_set()
625 	val = msm_readl_io(pctrl, g);  in msm_gpio_set()
627 		val |= BIT(g->out_bit);  in msm_gpio_set()
629 		val &= ~BIT(g->out_bit);  in msm_gpio_set()
630 	msm_writel_io(val, pctrl, g);  in msm_gpio_set()
645 	const struct msm_pingroup *g;  in msm_gpio_dbg_show_one()  local
671 	g = &pctrl->soc->groups[offset];  in msm_gpio_dbg_show_one()
672 	ctl_reg = msm_readl_ctl(pctrl, g);  in msm_gpio_dbg_show_one()
673 	io_reg = msm_readl_io(pctrl, g);  in msm_gpio_dbg_show_one()
675 	is_out = !!(ctl_reg & BIT(g->oe_bit));  in msm_gpio_dbg_show_one()
676 	func = (ctl_reg >> g->mux_bit) & 7;  in msm_gpio_dbg_show_one()
677 	drive = (ctl_reg >> g->drv_bit) & 7;  in msm_gpio_dbg_show_one()
678 	pull = (ctl_reg >> g->pull_bit) & 3;  in msm_gpio_dbg_show_one()
680 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))  in msm_gpio_dbg_show_one()
681 		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));  in msm_gpio_dbg_show_one()
684 		val = !!(io_reg & BIT(g->out_bit));  in msm_gpio_dbg_show_one()
686 		val = !!(io_reg & BIT(g->in_bit));  in msm_gpio_dbg_show_one()
689 		seq_printf(s, " %-8s: egpio\n", g->grp.name);  in msm_gpio_dbg_show_one()
693 	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");  in msm_gpio_dbg_show_one()
798 					  const struct msm_pingroup *g,  in msm_gpio_update_dual_edge_pos()  argument
806 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
808 		pol = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_update_dual_edge_pos()
809 		pol ^= BIT(g->intr_polarity_bit);  in msm_gpio_update_dual_edge_pos()
810 		msm_writel_intr_cfg(pol, pctrl, g);  in msm_gpio_update_dual_edge_pos()
812 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
813 		intstat = msm_readl_intr_status(pctrl, g);  in msm_gpio_update_dual_edge_pos()
825 	const struct msm_pingroup *g;  in msm_gpio_irq_mask()  local
835 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_mask()
839 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_mask()
861 		val &= ~BIT(g->intr_raw_status_bit);  in msm_gpio_irq_mask()
863 	val &= ~BIT(g->intr_enable_bit);  in msm_gpio_irq_mask()
864 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_mask()
875 	const struct msm_pingroup *g;  in msm_gpio_irq_unmask()  local
885 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_unmask()
889 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_unmask()
890 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_unmask()
891 	val |= BIT(g->intr_enable_bit);  in msm_gpio_irq_unmask()
892 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_unmask()
940 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_update_dual_edge_parent()  local
946 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
959 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
977 	const struct msm_pingroup *g;  in msm_gpio_irq_ack()  local
986 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_ack()
990 	msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_ack()
993 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_ack()
1022 	const struct msm_pingroup *g;  in msm_gpio_irq_init_valid_mask()  local
1028 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_init_valid_mask()
1030 		if (g->intr_detection_width != 1 &&  in msm_gpio_irq_init_valid_mask()
1031 		    g->intr_detection_width != 2)  in msm_gpio_irq_init_valid_mask()
1040 	const struct msm_pingroup *g;  in msm_gpio_irq_set_type()  local
1061 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_set_type()
1068 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)  in msm_gpio_irq_set_type()
1077 	if (g->intr_target_width)  in msm_gpio_irq_set_type()
1078 		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);  in msm_gpio_irq_set_type()
1081 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;  in msm_gpio_irq_set_type()
1085 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1086 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1094 		val = msm_readl_intr_target(pctrl, g);  in msm_gpio_irq_set_type()
1095 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1096 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1097 		msm_writel_intr_target(val, pctrl, g);  in msm_gpio_irq_set_type()
1105 	val = oldval = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_set_type()
1106 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
1107 	if (g->intr_detection_width == 2) {  in msm_gpio_irq_set_type()
1108 		val &= ~(3 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1109 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1112 			val |= 1 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1113 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1116 			val |= 2 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1117 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1120 			val |= 3 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1121 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1126 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1129 	} else if (g->intr_detection_width == 1) {  in msm_gpio_irq_set_type()
1130 		val &= ~(1 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1131 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1134 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1135 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1138 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1141 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1142 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1147 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1153 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_set_type()
1163 		msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_set_type()
1166 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_set_type()
1199 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_reqres()  local
1234 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_reqres()
1239 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_reqres()
1240 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_reqres()
1241 			intr_cfg |= BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_reqres()
1242 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_reqres()
1258 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_relres()  local
1262 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_relres()
1267 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_relres()
1268 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_relres()
1269 			intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_relres()
1270 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_relres()
1306 	const struct msm_pingroup *g;  in msm_gpio_irq_handler()  local
1320 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_handler()
1321 		val = msm_readl_intr_status(pctrl, g);  in msm_gpio_irq_handler()
1322 		if (val & BIT(g->intr_status_bit)) {  in msm_gpio_irq_handler()
1400 	chip->base = -1;  in msm_gpio_init()
1431 	girq->num_parents = 1;  in msm_gpio_init()
1432 	girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),  in msm_gpio_init()