Lines Matching +full:func +full:- +full:uart +full:- +full:c
1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl driver for the T-Head TH1520 SoC
5 * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
26 #include <linux/pinctrl/pinconf-generic.h>
67 return thp->base + 4 * (pin / 2); in th1520_padcfg()
78 return thp->base + 0x400 + 4 * (pin / 8); in th1520_muxcfg()
116 [TH1520_MUX_UART] = "uart",
183 TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0),
184 TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0),
220 TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0),
221 TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0),
226 TH1520_PAD(10, UART1_TXD, UART, ____, ____, GPIO, ____, ____, 0),
227 TH1520_PAD(11, UART1_RXD, UART, ____, ____, GPIO, ____, ____, 0),
228 TH1520_PAD(12, UART4_TXD, UART, ____, ____, GPIO, ____, ____, 0),
229 TH1520_PAD(13, UART4_RXD, UART, ____, ____, GPIO, ____, ____, 0),
230 TH1520_PAD(14, UART4_CTSN, UART, ____, ____, GPIO, ____, ____, 0),
231 TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0),
232 TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0),
233 TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0),
236 TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, DPU0, DPU1, 0),
237 TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0),
261 TH1520_PAD(45, GPIO1_13, GPIO, UART, ____, ____, DPU0, DPU1, 0),
262 TH1520_PAD(46, GPIO1_14, GPIO, UART, ____, ____, DPU0, DPU1, 0),
263 TH1520_PAD(47, GPIO1_15, GPIO, UART, ____, ____, DPU0, DPU1, 0),
264 TH1520_PAD(48, GPIO1_16, GPIO, UART, ____, ____, DPU0, DPU1, 0),
282 TH1520_PAD(0, UART0_TXD, UART, ____, ____, GPIO, ____, ____, 0),
283 TH1520_PAD(1, UART0_RXD, UART, ____, ____, GPIO, ____, ____, 0),
291 TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0),
292 TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0),
296 TH1520_PAD(14, SPI_SCLK, SPI, UART, IR, GPIO, ____, ____, 0),
297 TH1520_PAD(15, SPI_CSN, SPI, UART, IR, GPIO, ____, ____, 0),
323 TH1520_PAD(41, GMAC0_TXEN, MAC0, UART, ____, GPIO, ____, ____, 0),
324 TH1520_PAD(42, GMAC0_TXD0, MAC0, UART, ____, GPIO, ____, ____, 0),
325 TH1520_PAD(43, GMAC0_TXD1, MAC0, UART, ____, GPIO, ____, ____, 0),
326 TH1520_PAD(44, GMAC0_TXD2, MAC0, UART, ____, GPIO, ____, ____, 0),
340 .name = "th1520-group1",
346 .name = "th1520-group2",
352 .name = "th1520-group3",
361 return thp->desc.npins; in th1520_pinctrl_get_groups_count()
369 return thp->desc.pins[gsel].name; in th1520_pinctrl_get_group_name()
379 *pins = &thp->desc.pins[gsel].number; in th1520_pinctrl_get_group_pins()
394 scoped_guard(raw_spinlock_irqsave, &thp->lock) { in th1520_pin_dbg_show()
441 dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n", in th1520_pinctrl_dt_node_to_map()
443 return -EINVAL; in th1520_pinctrl_dt_node_to_map()
452 return -ENOMEM; in th1520_pinctrl_dt_node_to_map()
455 guard(mutex)(&thp->mutex); in th1520_pinctrl_dt_node_to_map()
467 dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n", in th1520_pinctrl_dt_node_to_map()
475 dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n", in th1520_pinctrl_dt_node_to_map()
477 ret = -EINVAL; in th1520_pinctrl_dt_node_to_map()
481 funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn", in th1520_pinctrl_dt_node_to_map()
484 ret = -ENOMEM; in th1520_pinctrl_dt_node_to_map()
489 pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL); in th1520_pinctrl_dt_node_to_map()
491 ret = -ENOMEM; in th1520_pinctrl_dt_node_to_map()
502 for (i = 0; i < thp->desc.npins; i++) { in th1520_pinctrl_dt_node_to_map()
503 if (!strcmp(pinname, thp->desc.pins[i].name)) in th1520_pinctrl_dt_node_to_map()
506 if (i == thp->desc.npins) { in th1520_pinctrl_dt_node_to_map()
508 dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n", in th1520_pinctrl_dt_node_to_map()
510 ret = -EINVAL; in th1520_pinctrl_dt_node_to_map()
516 map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name; in th1520_pinctrl_dt_node_to_map()
522 pgnames[npins++] = thp->desc.pins[i].name; in th1520_pinctrl_dt_node_to_map()
525 map[nmaps].data.mux.group = thp->desc.pins[i].name; in th1520_pinctrl_dt_node_to_map()
534 dev_err(thp->pctl->dev, "error adding function %s\n", funcname); in th1520_pinctrl_dt_node_to_map()
585 scoped_guard(raw_spinlock_irqsave, &thp->lock) { in th1520_padcfg_rmw()
603 if (th1520_pad_no_padcfg(desc->drv_data)) in th1520_pinconf_get()
604 return -ENOTSUPP; in th1520_pinconf_get()
649 return -ENOTSUPP; in th1520_pinconf_get()
653 return enabled ? 0 : -EINVAL; in th1520_pinconf_get()
660 unsigned int pin = thp->desc.pins[gsel].number; in th1520_pinconf_group_get()
673 if (th1520_pad_no_padcfg(desc->drv_data)) in th1520_pinconf_set()
674 return -ENOTSUPP; in th1520_pinconf_set()
689 return -ENOTSUPP; in th1520_pinconf_set()
696 return -ENOTSUPP; in th1520_pinconf_set()
731 return -ENOTSUPP; in th1520_pinconf_set()
744 unsigned int pin = thp->desc.pins[gsel].number; in th1520_pinconf_group_set()
785 dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n", in th1520_pinmux_set()
786 th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin)); in th1520_pinmux_set()
787 return -EINVAL; in th1520_pinmux_set()
793 scoped_guard(raw_spinlock_irqsave, &thp->lock) { in th1520_pinmux_set()
805 const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel); in th1520_pinmux_set_mux() local
808 if (!func) in th1520_pinmux_set_mux()
809 return -EINVAL; in th1520_pinmux_set_mux()
811 muxtype = (uintptr_t)func->data; in th1520_pinmux_set_mux()
812 return th1520_pinmux_set(thp, thp->desc.pins[gsel].number, in th1520_pinmux_set_mux()
813 th1520_pad_muxdata(thp->desc.pins[gsel].drv_data), in th1520_pinmux_set_mux()
825 th1520_pad_muxdata(desc->drv_data), in th1520_gpio_request_enable()
851 struct device *dev = &pdev->dev; in th1520_pinctrl_probe()
853 struct device_node *np = dev->of_node; in th1520_pinctrl_probe()
861 return -ENOMEM; in th1520_pinctrl_probe()
863 thp->base = devm_platform_ioremap_resource(pdev, 0); in th1520_pinctrl_probe()
864 if (IS_ERR(thp->base)) in th1520_pinctrl_probe()
865 return PTR_ERR(thp->base); in th1520_pinctrl_probe()
871 ret = of_property_read_u32(np, "thead,pad-group", &pin_group); in th1520_pinctrl_probe()
873 return dev_err_probe(dev, ret, "failed to read the thead,pad-group property\n"); in th1520_pinctrl_probe()
882 return dev_err_probe(dev, -EINVAL, "unit address did not match any pad group\n"); in th1520_pinctrl_probe()
884 thp->desc.name = group->name; in th1520_pinctrl_probe()
885 thp->desc.pins = group->pins; in th1520_pinctrl_probe()
886 thp->desc.npins = group->npins; in th1520_pinctrl_probe()
887 thp->desc.pctlops = &th1520_pinctrl_ops; in th1520_pinctrl_probe()
888 thp->desc.pmxops = &th1520_pinmux_ops; in th1520_pinctrl_probe()
889 thp->desc.confops = &th1520_pinconf_ops; in th1520_pinctrl_probe()
890 thp->desc.owner = THIS_MODULE; in th1520_pinctrl_probe()
891 mutex_init(&thp->mutex); in th1520_pinctrl_probe()
892 raw_spin_lock_init(&thp->lock); in th1520_pinctrl_probe()
894 ret = devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl); in th1520_pinctrl_probe()
898 return pinctrl_enable(thp->pctl); in th1520_pinctrl_probe()
902 { .compatible = "thead,th1520-pinctrl"},
910 .name = "pinctrl-th1520",
916 MODULE_DESCRIPTION("Pinctrl driver for the T-Head TH1520 SoC");