Lines Matching +full:3 +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0-only
22 #include "pinctrl-utils.h"
36 #define PCFG_PORT_MASK(PORT) \ argument
37 (((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))
40 /* Port 1 */
44 PINCTRL_PIN(TB10X_PORT1 + 3, "MDI_S0"),
52 /* Port 2 */
56 PINCTRL_PIN(TB10X_PORT2 + 3, "MDI_S2"),
64 /* Port 3 */
68 PINCTRL_PIN(TB10X_PORT3 + 3, "MDI_S4"),
76 /* Port 4 */
80 PINCTRL_PIN(TB10X_PORT4 + 3, "MDI_S6"),
88 /* Port 5 */
92 PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"),
143 /* Port 6 */
147 PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"),
154 /* Port 7 */
158 PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"),
163 /* Port 8 */
167 PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"),
168 /* Port 9 */
172 PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"),
179 PINCTRL_PIN(TB10X_GPIOS + 3, "GPIOD1"),
209 /* Port 1 */
211 TB10X_PORT1 + 2, TB10X_PORT1 + 3};
217 TB10X_PORT1 + 2, TB10X_PORT1 + 3,
223 /* Port 2 */
225 TB10X_PORT2 + 2, TB10X_PORT2 + 3};
231 TB10X_PORT2 + 2, TB10X_PORT2 + 3,
237 /* Port 3 */
239 TB10X_PORT3 + 2, TB10X_PORT3 + 3};
245 TB10X_PORT3 + 2, TB10X_PORT3 + 3,
251 /* Port 4 */
253 TB10X_PORT4 + 2, TB10X_PORT4 + 3};
259 TB10X_PORT4 + 2, TB10X_PORT4 + 3,
265 /* Port 6 */
267 TB10X_PORT6 + 2, TB10X_PORT6 + 3,
273 static const unsigned mos1_pins[] = { TB10X_PORT6 + 3, TB10X_PORT6 + 4,
279 /* Port 7 */
281 TB10X_PORT7 + 2, TB10X_PORT7 + 3};
285 TB10X_PORT7 + 2, TB10X_PORT7 + 3};
289 /* Port 8 */
291 TB10X_PORT8 + 2, TB10X_PORT8 + 3};
293 TB10X_PORT8 + 2, TB10X_PORT8 + 3};
295 /* Port 9 */
297 TB10X_PORT9 + 2, TB10X_PORT9 + 3,
300 TB10X_PORT9 + 2, TB10X_PORT9 + 3,
303 /* Port 5 */
305 TB10X_PORT5 + 2, TB10X_PORT5 + 3,
332 TB10X_PORT5 + 2, TB10X_PORT5 + 3,
358 static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10,
382 static const unsigned gpiod_pins[] = { TB10X_GPIOS + 2, TB10X_GPIOS + 3};
396 const int port; member
400 #define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \ argument
403 .port = (PORT), .mode = (MODE), \
419 DEFPINFUNCGRP(mis6, 3, 0, 0),
420 DEFPINFUNCGRP(gpiog, 3, 0, 1),
421 DEFPINFUNCGRP(mis7, 3, 0, 0),
422 DEFPINFUNCGRP(mip7, 3, 1, 0),
427 DEFPINFUNCGRP(stc0, 4, 3, 0),
428 DEFPINFUNCGRP(stc1, 4, 3, 0),
442 DEFPINFUNCGRP(gpiob, -1, 0, 1),
443 DEFPINFUNCGRP(gpiod, -1, 0, 1),
444 DEFPINFUNCGRP(gpiof, -1, 0, 1),
445 DEFPINFUNCGRP(gpioh, -1, 0, 1),
446 DEFPINFUNCGRP(gpioi, -1, 0, 1),
458 * struct tb10x_port - state of an I/O port
459 * @mode: Node this port is currently in.
460 * @count: Number of enabled functions which require this port to be
469 * struct tb10x_pinctrl - TB10x pin controller internal state
476 * @ports: current state of each port.
493 unsigned int port, unsigned int mode) in tb10x_pinctrl_set_config() argument
497 if (state->ports[port].count) in tb10x_pinctrl_set_config()
500 state->ports[port].mode = mode; in tb10x_pinctrl_set_config()
502 pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port)); in tb10x_pinctrl_set_config()
503 pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port); in tb10x_pinctrl_set_config()
504 iowrite32(pcfg, state->base); in tb10x_pinctrl_set_config()
509 unsigned int port) in tb10x_pinctrl_get_config() argument
511 return (ioread32(state->base) & PCFG_PORT_MASK(port)) in tb10x_pinctrl_get_config()
512 >> (PCFG_PORT_BITWIDTH * port); in tb10x_pinctrl_get_config()
518 return state->pinfuncgrpcnt; in tb10x_get_groups_count()
524 return state->pingroups[n].name; in tb10x_get_group_name()
533 *pins = state->pingroups[n].pins; in tb10x_get_group_pins()
534 *num_pins = state->pingroups[n].pincnt; in tb10x_get_group_pins()
550 return -EINVAL; in tb10x_dt_node_to_map()
562 num_maps, string, np_config->name); in tb10x_dt_node_to_map()
579 return state->pinfuncnt; in tb10x_get_functions_count()
586 return state->pinfuncs[n].name; in tb10x_get_function_name()
595 *groups = &state->pinfuncs[n].group; in tb10x_get_function_groups()
606 int muxport = -1; in tb10x_gpio_request_enable()
607 int muxmode = -1; in tb10x_gpio_request_enable()
610 mutex_lock(&state->mutex); in tb10x_gpio_request_enable()
613 * Figure out to which port the requested GPIO belongs and how to in tb10x_gpio_request_enable()
614 * configure that port. in tb10x_gpio_request_enable()
618 for (i = 0; i < state->pinfuncgrpcnt; i++) { in tb10x_gpio_request_enable()
619 const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i]; in tb10x_gpio_request_enable()
620 unsigned int mode = pfg->mode; in tb10x_gpio_request_enable()
621 int j, port = pfg->port; in tb10x_gpio_request_enable() local
627 if (port < 0) in tb10x_gpio_request_enable()
630 for (j = 0; j < pfg->pincnt; j++) { in tb10x_gpio_request_enable()
631 if (pin == pfg->pins[j]) { in tb10x_gpio_request_enable()
632 if (pfg->isgpio) { in tb10x_gpio_request_enable()
634 * Remember the GPIO-only setting of in tb10x_gpio_request_enable()
635 * the port this pin belongs to. in tb10x_gpio_request_enable()
637 muxport = port; in tb10x_gpio_request_enable()
639 } else if (state->ports[port].count in tb10x_gpio_request_enable()
640 && (state->ports[port].mode == mode)) { in tb10x_gpio_request_enable()
645 mutex_unlock(&state->mutex); in tb10x_gpio_request_enable()
646 return -EBUSY; in tb10x_gpio_request_enable()
659 set_bit(pin, state->gpios); in tb10x_gpio_request_enable()
664 * Right Thing, either configure the port in GPIO only mode or leave in tb10x_gpio_request_enable()
670 mutex_unlock(&state->mutex); in tb10x_gpio_request_enable()
681 mutex_lock(&state->mutex); in tb10x_gpio_disable_free()
683 clear_bit(pin, state->gpios); in tb10x_gpio_disable_free()
685 mutex_unlock(&state->mutex); in tb10x_gpio_disable_free()
692 const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector]; in tb10x_pctl_set_mux()
695 if (grp->port < 0) in tb10x_pctl_set_mux()
698 mutex_lock(&state->mutex); in tb10x_pctl_set_mux()
704 if (state->ports[grp->port].count in tb10x_pctl_set_mux()
705 && (state->ports[grp->port].mode != grp->mode)) { in tb10x_pctl_set_mux()
706 mutex_unlock(&state->mutex); in tb10x_pctl_set_mux()
707 return -EBUSY; in tb10x_pctl_set_mux()
714 for (i = 0; i < grp->pincnt; i++) in tb10x_pctl_set_mux()
715 if (test_bit(grp->pins[i], state->gpios)) { in tb10x_pctl_set_mux()
716 mutex_unlock(&state->mutex); in tb10x_pctl_set_mux()
717 return -EBUSY; in tb10x_pctl_set_mux()
720 tb10x_pinctrl_set_config(state, grp->port, grp->mode); in tb10x_pctl_set_mux()
722 state->ports[grp->port].count++; in tb10x_pctl_set_mux()
724 mutex_unlock(&state->mutex); in tb10x_pctl_set_mux()
749 int ret = -EINVAL; in tb10x_pinctrl_probe()
750 struct device *dev = &pdev->dev; in tb10x_pinctrl_probe()
751 struct device_node *of_node = dev->of_node; in tb10x_pinctrl_probe()
758 return -EINVAL; in tb10x_pinctrl_probe()
765 return -ENOMEM; in tb10x_pinctrl_probe()
768 mutex_init(&state->mutex); in tb10x_pinctrl_probe()
770 state->base = devm_platform_ioremap_resource(pdev, 0); in tb10x_pinctrl_probe()
771 if (IS_ERR(state->base)) { in tb10x_pinctrl_probe()
772 ret = PTR_ERR(state->base); in tb10x_pinctrl_probe()
776 state->pingroups = tb10x_pingroups; in tb10x_pinctrl_probe()
777 state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups); in tb10x_pinctrl_probe()
780 state->ports[i].mode = tb10x_pinctrl_get_config(state, i); in tb10x_pinctrl_probe()
787 state->pinfuncs[state->pinfuncnt].name = child->name; in tb10x_pinctrl_probe()
788 state->pinfuncs[state->pinfuncnt].group = name; in tb10x_pinctrl_probe()
789 state->pinfuncnt++; in tb10x_pinctrl_probe()
793 state->pctl = devm_pinctrl_register(dev, &tb10x_pindesc, state); in tb10x_pinctrl_probe()
794 if (IS_ERR(state->pctl)) { in tb10x_pinctrl_probe()
796 ret = PTR_ERR(state->pctl); in tb10x_pinctrl_probe()
803 mutex_destroy(&state->mutex); in tb10x_pinctrl_probe()
811 mutex_destroy(&state->mutex); in tb10x_pinctrl_remove()
816 { .compatible = "abilis,tb10x-iomux" },