Lines Matching +full:per +full:- +full:pin
1 // SPDX-License-Identifier: GPL-2.0-only
78 * each register is dedicated per pin.
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
114 * +----------------+ |
115 *[22] | retime-invclk | |
116 * +----------------+ v
117 *[21] |retime-clknotdat| [Retime-type ]
118 * +----------------+ ^
119 *[20] | retime-de | |
120 * +----------------+-------------
121 *[19:18]| retime-clk |------>[Retime-Clk ]
122 * +----------------+
123 *[17:16]| reserved-1 |
124 * +----------------+
125 *[15..0]| retime-delay |------>[Retime Delay]
126 * +----------------+
252 int pin; member
275 * of each gpio pin in a GPIO bank.
278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
280 * bit allocation per pin is:
281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
282 * --------------------------------------------------------
283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
284 * --------------------------------------------------------
286 * A pin can have one of following the values in its edge configuration field.
288 * ------- ----------------------------
289 * [0-3] - Description
290 * ------- ----------------------------
291 * 0000 - No edge IRQ.
292 * 0001 - Falling edge IRQ.
293 * 0010 - Rising edge IRQ.
294 * 0011 - Rising and Falling edge IRQ.
295 * ------- ----------------------------
304 #define ST_IRQ_RISING_EDGE_CONF(pin) \ argument
305 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
307 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ argument
308 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
310 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ argument
311 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
313 #define ST_IRQ_EDGE_CONF(conf, pin) \ argument
314 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
360 .oe = -1, /* Not Available */
361 .pu = -1, /* Not Available */
367 struct pinctrl_dev *pctldev, int pin) in st_get_pio_control() argument
370 pinctrl_find_gpio_range_from_pin(pctldev, pin); in st_get_pio_control()
373 return &bank->pc; in st_get_pio_control()
388 int pin, unsigned long config) in st_pinconf_set_config() argument
390 struct regmap_field *output_enable = pc->oe; in st_pinconf_set_config()
391 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
392 struct regmap_field *open_drain = pc->od; in st_pinconf_set_config()
394 unsigned long mask = BIT(pin); in st_pinconf_set_config()
424 struct regmap_field *alt = pc->alt; in st_pctl_set_function()
426 int pin = st_gpio_pin(pin_id); in st_pctl_set_function() local
427 int offset = pin * 4; in st_pctl_set_function()
438 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) in st_pctl_get_pin_function() argument
440 struct regmap_field *alt = pc->alt; in st_pctl_get_pin_function()
442 int offset = pin * 4; in st_pctl_get_pin_function()
456 int num_delay_times, i, closest_index = -1; in st_pinconf_delay_to_bit()
460 delay_times = data->output_delays; in st_pinconf_delay_to_bit()
461 num_delay_times = data->noutput_delays; in st_pinconf_delay_to_bit()
463 delay_times = data->input_delays; in st_pinconf_delay_to_bit()
464 num_delay_times = data->ninput_delays; in st_pinconf_delay_to_bit()
468 unsigned int divergence = abs(delay - delay_times[i]); in st_pinconf_delay_to_bit()
492 delay_times = data->output_delays; in st_pinconf_bit_to_delay()
493 num_delay_times = data->noutput_delays; in st_pinconf_bit_to_delay()
495 delay_times = data->input_delays; in st_pinconf_bit_to_delay()
496 num_delay_times = data->ninput_delays; in st_pinconf_bit_to_delay()
508 int enable, int pin) in st_regmap_field_bit_set_clear_pin() argument
514 val |= BIT(pin); in st_regmap_field_bit_set_clear_pin()
516 val &= ~BIT(pin); in st_regmap_field_bit_set_clear_pin()
521 struct st_pio_control *pc, unsigned long config, int pin) in st_pinconf_set_retime_packed() argument
523 const struct st_pctl_data *data = info->data; in st_pinconf_set_retime_packed()
524 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_set_retime_packed()
527 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, in st_pinconf_set_retime_packed()
528 ST_PINCONF_UNPACK_RT_CLK(config), pin); in st_pinconf_set_retime_packed()
530 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, in st_pinconf_set_retime_packed()
531 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); in st_pinconf_set_retime_packed()
533 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, in st_pinconf_set_retime_packed()
534 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); in st_pinconf_set_retime_packed()
536 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, in st_pinconf_set_retime_packed()
537 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); in st_pinconf_set_retime_packed()
539 st_regmap_field_bit_set_clear_pin(rt_p->retime, in st_pinconf_set_retime_packed()
540 ST_PINCONF_UNPACK_RT(config), pin); in st_pinconf_set_retime_packed()
545 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); in st_pinconf_set_retime_packed()
547 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); in st_pinconf_set_retime_packed()
551 struct st_pio_control *pc, unsigned long config, int pin) in st_pinconf_set_retime_dedicated() argument
562 info->data, config); in st_pinconf_set_retime_dedicated()
563 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_set_retime_dedicated()
574 regmap_field_write(rt_d->rt[pin], retime_config); in st_pinconf_set_retime_dedicated()
578 int pin, unsigned long *config) in st_pinconf_get_direction() argument
582 if (pc->oe) { in st_pinconf_get_direction()
583 regmap_field_read(pc->oe, &oe_value); in st_pinconf_get_direction()
584 if (oe_value & BIT(pin)) in st_pinconf_get_direction()
588 if (pc->pu) { in st_pinconf_get_direction()
589 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
590 if (pu_value & BIT(pin)) in st_pinconf_get_direction()
594 if (pc->od) { in st_pinconf_get_direction()
595 regmap_field_read(pc->od, &od_value); in st_pinconf_get_direction()
596 if (od_value & BIT(pin)) in st_pinconf_get_direction()
602 struct st_pio_control *pc, int pin, unsigned long *config) in st_pinconf_get_retime_packed() argument
604 const struct st_pctl_data *data = info->data; in st_pinconf_get_retime_packed()
605 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_get_retime_packed()
609 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
612 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
615 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
618 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
621 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
624 regmap_field_read(rt_p->delay_0, &delay0); in st_pinconf_get_retime_packed()
625 regmap_field_read(rt_p->delay_1, &delay1); in st_pinconf_get_retime_packed()
626 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | in st_pinconf_get_retime_packed()
627 (((delay0 & BIT(pin)) ? 1 : 0)); in st_pinconf_get_retime_packed()
635 struct st_pio_control *pc, int pin, unsigned long *config) in st_pinconf_get_retime_dedicated() argument
640 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_get_retime_dedicated()
642 regmap_field_read(rt_d->rt[pin], &value); in st_pinconf_get_retime_dedicated()
648 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); in st_pinconf_get_retime_dedicated()
672 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); in __st_gpio_set()
674 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); in __st_gpio_set()
685 * PIO port pins. Each pin can be configured as an input, output, in st_gpio_direction()
686 * bidirectional, or alternative function pin. Three bits, one bit in st_gpio_direction()
691 * 0 0 0 [Input Weak pull-up] in st_gpio_direction()
701 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); in st_gpio_direction()
703 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); in st_gpio_direction()
711 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); in st_gpio_get()
733 struct st_pio_control pc = bank->pc; in st_gpio_get_direction()
752 * - See st_gpio_direction() above for an explanation in st_gpio_get_direction()
755 value = readl(bank->base + REG_PIO_PC(i)); in st_gpio_get_direction()
770 return info->ngroups; in st_pctl_get_groups_count()
778 return info->groups[selector].name; in st_pctl_get_group_name()
786 if (selector >= info->ngroups) in st_pctl_get_group_pins()
787 return -EINVAL; in st_pctl_get_group_pins()
789 *pins = info->groups[selector].pins; in st_pctl_get_group_pins()
790 *npins = info->groups[selector].npins; in st_pctl_get_group_pins()
800 for (i = 0; i < info->ngroups; i++) { in st_pctl_find_group_by_name()
801 if (!strcmp(info->groups[i].name, name)) in st_pctl_find_group_by_name()
802 return &info->groups[i]; in st_pctl_find_group_by_name()
813 struct device *dev = info->dev; in st_pctl_dt_node_to_map()
818 grp = st_pctl_find_group_by_name(info, np->name); in st_pctl_dt_node_to_map()
821 return -EINVAL; in st_pctl_dt_node_to_map()
824 map_num = grp->npins + 1; in st_pctl_dt_node_to_map()
827 return -ENOMEM; in st_pctl_dt_node_to_map()
832 return -EINVAL; in st_pctl_dt_node_to_map()
838 new_map[0].data.mux.function = parent->name; in st_pctl_dt_node_to_map()
839 new_map[0].data.mux.group = np->name; in st_pctl_dt_node_to_map()
842 /* create config map per pin */ in st_pctl_dt_node_to_map()
844 for (i = 0; i < grp->npins; i++) { in st_pctl_dt_node_to_map()
847 pin_get_name(pctldev, grp->pins[i]); in st_pctl_dt_node_to_map()
848 new_map[i].data.configs.configs = &grp->pin_conf[i].config; in st_pctl_dt_node_to_map()
852 (*map)->data.mux.function, grp->name, map_num); in st_pctl_dt_node_to_map()
875 return info->nfunctions; in st_pmx_get_funcs_count()
883 return info->functions[selector].name; in st_pmx_get_fname()
890 *grps = info->functions[selector].groups; in st_pmx_get_groups()
891 *ngrps = info->functions[selector].ngroups; in st_pmx_get_groups()
900 struct st_pinconf *conf = info->groups[group].pin_conf; in st_pmx_set_mux()
904 for (i = 0; i < info->groups[group].npins; i++) { in st_pmx_set_mux()
905 pc = st_get_pio_control(pctldev, conf[i].pin); in st_pmx_set_mux()
906 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); in st_pmx_set_mux()
922 st_pctl_set_function(&bank->pc, gpio, 0); in st_pmx_set_gpio_direction()
940 struct st_pio_control *pc, int pin, unsigned long *config) in st_pinconf_get_retime() argument
942 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_get_retime()
943 st_pinconf_get_retime_packed(info, pc, pin, config); in st_pinconf_get_retime()
944 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_get_retime()
945 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_get_retime()
947 pin, config); in st_pinconf_get_retime()
951 struct st_pio_control *pc, int pin, unsigned long config) in st_pinconf_set_retime() argument
953 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_set_retime()
954 st_pinconf_set_retime_packed(info, pc, config, pin); in st_pinconf_set_retime()
955 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_set_retime()
956 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_set_retime()
958 config, pin); in st_pinconf_set_retime()
964 int pin = st_gpio_pin(pin_id); in st_pinconf_set() local
970 st_pinconf_set_config(pc, pin, configs[i]); in st_pinconf_set()
971 st_pinconf_set_retime(info, pc, pin, configs[i]); in st_pinconf_set()
980 int pin = st_gpio_pin(pin_id); in st_pinconf_get() local
985 st_pinconf_get_direction(pc, pin, config); in st_pinconf_get()
986 st_pinconf_get_retime(info, pc, pin, config); in st_pinconf_get()
1001 mutex_unlock(&pctldev->mutex); in st_pinconf_dbg_show()
1004 mutex_lock(&pctldev->mutex); in st_pinconf_dbg_show()
1012 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); in st_pinconf_dbg_show()
1015 "de:%ld,rt-clk:%ld,rt-delay:%ld]", in st_pinconf_dbg_show()
1039 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_dt_child_count()
1040 info->nbanks++; in st_pctl_dt_child_count()
1042 info->nfunctions++; in st_pctl_dt_child_count()
1043 info->ngroups += of_get_child_count(child); in st_pctl_dt_child_count()
1051 struct device *dev = info->dev; in st_pctl_dt_setup_retime_packed()
1052 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_packed()
1053 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_packed()
1054 /* 2 registers per bank */ in st_pctl_dt_setup_retime_packed()
1055 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_packed()
1056 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pctl_dt_setup_retime_packed()
1067 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); in st_pctl_dt_setup_retime_packed()
1068 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); in st_pctl_dt_setup_retime_packed()
1069 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); in st_pctl_dt_setup_retime_packed()
1070 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); in st_pctl_dt_setup_retime_packed()
1071 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); in st_pctl_dt_setup_retime_packed()
1072 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); in st_pctl_dt_setup_retime_packed()
1073 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); in st_pctl_dt_setup_retime_packed()
1075 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || in st_pctl_dt_setup_retime_packed()
1076 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || in st_pctl_dt_setup_retime_packed()
1077 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || in st_pctl_dt_setup_retime_packed()
1078 IS_ERR(rt_p->double_edge)) in st_pctl_dt_setup_retime_packed()
1079 return -EINVAL; in st_pctl_dt_setup_retime_packed()
1087 struct device *dev = info->dev; in st_pctl_dt_setup_retime_dedicated()
1088 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_dedicated()
1089 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_dedicated()
1090 /* 8 registers per bank */ in st_pctl_dt_setup_retime_dedicated()
1091 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_dedicated()
1092 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pctl_dt_setup_retime_dedicated()
1094 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated()
1099 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); in st_pctl_dt_setup_retime_dedicated()
1100 if (IS_ERR(rt_d->rt[j])) in st_pctl_dt_setup_retime_dedicated()
1101 return -EINVAL; in st_pctl_dt_setup_retime_dedicated()
1111 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime()
1112 if (data->rt_style == st_retime_style_packed) in st_pctl_dt_setup_retime()
1114 else if (data->rt_style == st_retime_style_dedicated) in st_pctl_dt_setup_retime()
1117 return -EINVAL; in st_pctl_dt_setup_retime()
1136 const struct st_pctl_data *data = info->data; in st_parse_syscfgs()
1138 * For a given shared register like OE/PU/OD, there are 8 bits per bank in st_parse_syscfgs()
1143 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; in st_parse_syscfgs()
1144 struct st_pio_control *pc = &info->banks[bank].pc; in st_parse_syscfgs()
1145 struct device *dev = info->dev; in st_parse_syscfgs()
1146 struct regmap *regmap = info->regmap; in st_parse_syscfgs()
1148 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); in st_parse_syscfgs()
1149 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); in st_parse_syscfgs()
1150 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
1151 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); in st_parse_syscfgs()
1154 pc->rt_pin_mask = 0xff; in st_parse_syscfgs()
1155 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); in st_parse_syscfgs()
1166 int retval = -EINVAL; in st_pctl_dt_calculate_pin()
1171 return -EINVAL; in st_pctl_dt_calculate_pin()
1173 for (i = 0; i < info->nbanks; i++) { in st_pctl_dt_calculate_pin()
1174 chip = &info->banks[i].gpio_chip; in st_pctl_dt_calculate_pin()
1175 if (chip->fwnode == of_fwnode_handle(np)) { in st_pctl_dt_calculate_pin()
1176 if (offset < chip->ngpio) in st_pctl_dt_calculate_pin()
1177 retval = chip->base + offset; in st_pctl_dt_calculate_pin()
1187 * Each pin is represented in of the below forms.
1196 struct device *dev = info->dev; in st_pctl_dt_parse_groups()
1205 return -ENODATA; in st_pctl_dt_parse_groups()
1209 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1212 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { in st_pctl_dt_parse_groups()
1216 return -EINVAL; in st_pctl_dt_parse_groups()
1220 grp->npins = npins; in st_pctl_dt_parse_groups()
1221 grp->name = np->name; in st_pctl_dt_parse_groups()
1222 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); in st_pctl_dt_parse_groups()
1223 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); in st_pctl_dt_parse_groups()
1225 if (!grp->pins || !grp->pin_conf) in st_pctl_dt_parse_groups()
1226 return -ENOMEM; in st_pctl_dt_parse_groups()
1230 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1232 nr_props = pp->length/sizeof(u32); in st_pctl_dt_parse_groups()
1233 list = pp->value; in st_pctl_dt_parse_groups()
1234 conf = &grp->pin_conf[i]; in st_pctl_dt_parse_groups()
1239 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); in st_pctl_dt_parse_groups()
1240 conf->name = pp->name; in st_pctl_dt_parse_groups()
1241 grp->pins[i] = conf->pin; in st_pctl_dt_parse_groups()
1243 conf->altfunc = be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1244 conf->config = 0; in st_pctl_dt_parse_groups()
1246 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1250 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1252 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1255 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1266 struct device *dev = info->dev; in st_pctl_parse_functions()
1271 func = &info->functions[index]; in st_pctl_parse_functions()
1272 func->name = np->name; in st_pctl_parse_functions()
1273 func->ngroups = of_get_child_count(np); in st_pctl_parse_functions()
1274 if (func->ngroups == 0) in st_pctl_parse_functions()
1275 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); in st_pctl_parse_functions()
1276 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in st_pctl_parse_functions()
1277 if (!func->groups) in st_pctl_parse_functions()
1278 return -ENOMEM; in st_pctl_parse_functions()
1282 func->groups[i] = child->name; in st_pctl_parse_functions()
1283 grp = &info->groups[*grp_index]; in st_pctl_parse_functions()
1289 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); in st_pctl_parse_functions()
1299 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); in st_gpio_irq_mask()
1309 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); in st_gpio_irq_unmask()
1316 pinctrl_gpio_direction_input(gc, d->hwirq); in st_gpio_irq_request_resources()
1318 return gpiochip_reqres_irq(gc, d->hwirq); in st_gpio_irq_request_resources()
1325 gpiochip_relres_irq(gc, d->hwirq); in st_gpio_irq_release_resources()
1333 int comp, pin = d->hwirq; in st_gpio_irq_set_type() local
1343 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); in st_gpio_irq_set_type()
1350 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); in st_gpio_irq_set_type()
1353 comp = st_gpio_get(&bank->gpio_chip, pin); in st_gpio_irq_set_type()
1354 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); in st_gpio_irq_set_type()
1357 return -EINVAL; in st_gpio_irq_set_type()
1360 spin_lock_irqsave(&bank->lock, flags); in st_gpio_irq_set_type()
1361 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( in st_gpio_irq_set_type()
1362 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); in st_gpio_irq_set_type()
1363 bank->irq_edge_conf |= pin_edge_conf; in st_gpio_irq_set_type()
1364 spin_unlock_irqrestore(&bank->lock, flags); in st_gpio_irq_set_type()
1366 val = readl(bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1367 val &= ~BIT(pin); in st_gpio_irq_set_type()
1368 val |= (comp << pin); in st_gpio_irq_set_type()
1369 writel(val, bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1380 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1383 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1384 * IGNORE calling the actual interrupt handler for the pin at this stage.
1386 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1387 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1388 * DISPATCH the interrupt to the interrupt handler of the pin.
1390 * step-1 ________ __________
1391 * | | step - 3
1393 * step -2 |_____|
1404 spin_lock_irqsave(&bank->lock, flags); in __gpio_irq_handler()
1405 bank_edge_mask = bank->irq_edge_conf; in __gpio_irq_handler()
1406 spin_unlock_irqrestore(&bank->lock, flags); in __gpio_irq_handler()
1409 port_in = readl(bank->base + REG_PIO_PIN); in __gpio_irq_handler()
1410 port_comp = readl(bank->base + REG_PIO_PCOMP); in __gpio_irq_handler()
1411 port_mask = readl(bank->base + REG_PIO_PMASK); in __gpio_irq_handler()
1424 val = st_gpio_get(&bank->gpio_chip, n); in __gpio_irq_handler()
1427 val ? bank->base + REG_PIO_SET_PCOMP : in __gpio_irq_handler()
1428 bank->base + REG_PIO_CLR_PCOMP); in __gpio_irq_handler()
1435 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); in __gpio_irq_handler()
1442 /* interrupt dedicated per bank */ in st_gpio_irq_handler()
1461 status = readl(info->irqmux_base); in st_gpio_irqmux_handler()
1463 for_each_set_bit(n, &status, info->nbanks) in st_gpio_irqmux_handler()
1464 __gpio_irq_handler(&info->banks[n]); in st_gpio_irqmux_handler()
1494 struct st_gpio_bank *bank = &info->banks[bank_nr]; in st_gpiolib_register_bank()
1495 struct pinctrl_gpio_range *range = &bank->range; in st_gpiolib_register_bank()
1496 struct device *dev = info->dev; in st_gpiolib_register_bank()
1502 return -ENODEV; in st_gpiolib_register_bank()
1504 bank->base = devm_ioremap_resource(dev, &res); in st_gpiolib_register_bank()
1505 if (IS_ERR(bank->base)) in st_gpiolib_register_bank()
1506 return PTR_ERR(bank->base); in st_gpiolib_register_bank()
1508 bank->gpio_chip = st_gpio_template; in st_gpiolib_register_bank()
1509 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1510 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1511 bank->gpio_chip.fwnode = of_fwnode_handle(np); in st_gpiolib_register_bank()
1512 bank->gpio_chip.parent = dev; in st_gpiolib_register_bank()
1513 spin_lock_init(&bank->lock); in st_gpiolib_register_bank()
1515 of_property_read_string(np, "st,bank-name", &range->name); in st_gpiolib_register_bank()
1516 bank->gpio_chip.label = range->name; in st_gpiolib_register_bank()
1518 range->id = bank_num; in st_gpiolib_register_bank()
1519 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1520 range->npins = bank->gpio_chip.ngpio; in st_gpiolib_register_bank()
1521 range->gc = &bank->gpio_chip; in st_gpiolib_register_bank()
1525 * interrupt-wirings. in st_gpiolib_register_bank()
1531 * | |----> [gpio-bank (n) ] in st_gpiolib_register_bank()
1532 * | |----> [gpio-bank (n + 1)] in st_gpiolib_register_bank()
1533 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] in st_gpiolib_register_bank()
1534 * | |----> [gpio-bank (... )] in st_gpiolib_register_bank()
1535 * |_________|----> [gpio-bank (n + 7)] in st_gpiolib_register_bank()
1537 * Second type has a dedicated interrupt per each gpio bank. in st_gpiolib_register_bank()
1539 * [irqN]----> [gpio-bank (n)] in st_gpiolib_register_bank()
1552 if (!info->irqmux_base) { in st_gpiolib_register_bank()
1557 girq = &bank->gpio_chip.irq; in st_gpiolib_register_bank()
1559 girq->parent_handler = st_gpio_irq_handler; in st_gpiolib_register_bank()
1560 girq->num_parents = 1; in st_gpiolib_register_bank()
1561 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in st_gpiolib_register_bank()
1563 if (!girq->parents) in st_gpiolib_register_bank()
1564 return -ENOMEM; in st_gpiolib_register_bank()
1565 girq->parents[0] = gpio_irq; in st_gpiolib_register_bank()
1566 girq->default_type = IRQ_TYPE_NONE; in st_gpiolib_register_bank()
1567 girq->handler = handle_simple_irq; in st_gpiolib_register_bank()
1571 err = gpiochip_add_data(&bank->gpio_chip, bank); in st_gpiolib_register_bank()
1574 dev_info(dev, "%s bank added.\n", range->name); in st_gpiolib_register_bank()
1580 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1581 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1582 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1583 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1590 struct device *dev = &pdev->dev; in st_pctl_probe_dt()
1594 struct device_node *np = dev->of_node; in st_pctl_probe_dt()
1599 if (!info->nbanks) in st_pctl_probe_dt()
1600 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); in st_pctl_probe_dt()
1602 dev_info(dev, "nbanks = %d\n", info->nbanks); in st_pctl_probe_dt()
1603 dev_info(dev, "nfunctions = %d\n", info->nfunctions); in st_pctl_probe_dt()
1604 dev_info(dev, "ngroups = %d\n", info->ngroups); in st_pctl_probe_dt()
1606 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in st_pctl_probe_dt()
1608 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in st_pctl_probe_dt()
1610 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); in st_pctl_probe_dt()
1612 if (!info->functions || !info->groups || !info->banks) in st_pctl_probe_dt()
1613 return -ENOMEM; in st_pctl_probe_dt()
1615 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in st_pctl_probe_dt()
1616 if (IS_ERR(info->regmap)) in st_pctl_probe_dt()
1617 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); in st_pctl_probe_dt()
1618 info->data = of_match_node(st_pctl_of_match, np)->data; in st_pctl_probe_dt()
1623 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); in st_pctl_probe_dt()
1624 if (IS_ERR(info->irqmux_base)) in st_pctl_probe_dt()
1625 return PTR_ERR(info->irqmux_base); in st_pctl_probe_dt()
1631 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; in st_pctl_probe_dt()
1632 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); in st_pctl_probe_dt()
1634 return -ENOMEM; in st_pctl_probe_dt()
1636 pctl_desc->pins = pdesc; in st_pctl_probe_dt()
1640 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_probe_dt()
1648 k = info->banks[bank].range.pin_base; in st_pctl_probe_dt()
1649 bank_name = info->banks[bank].range.name; in st_pctl_probe_dt()
1656 pdesc->number = k; in st_pctl_probe_dt()
1657 pdesc->name = pin_names[j]; in st_pctl_probe_dt()
1677 struct device *dev = &pdev->dev; in st_pctl_probe()
1682 if (!dev->of_node) { in st_pctl_probe()
1684 return -EINVAL; in st_pctl_probe()
1689 return -ENOMEM; in st_pctl_probe()
1693 return -ENOMEM; in st_pctl_probe()
1695 info->dev = dev; in st_pctl_probe()
1701 pctl_desc->owner = THIS_MODULE; in st_pctl_probe()
1702 pctl_desc->pctlops = &st_pctlops; in st_pctl_probe()
1703 pctl_desc->pmxops = &st_pmxops; in st_pctl_probe()
1704 pctl_desc->confops = &st_confops; in st_pctl_probe()
1705 pctl_desc->name = dev_name(dev); in st_pctl_probe()
1707 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); in st_pctl_probe()
1708 if (IS_ERR(info->pctl)) in st_pctl_probe()
1709 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); in st_pctl_probe()
1711 for (i = 0; i < info->nbanks; i++) in st_pctl_probe()
1712 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); in st_pctl_probe()
1719 .name = "st-pinctrl",