Lines Matching +full:four +full:- +full:bank
1 // SPDX-License-Identifier: GPL-2.0-only
64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
99 * All the bit fields can be encapsulated into four variables
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
114 * +----------------+ |
115 *[22] | retime-invclk | |
116 * +----------------+ v
117 *[21] |retime-clknotdat| [Retime-type ]
118 * +----------------+ ^
119 *[20] | retime-de | |
120 * +----------------+-------------
121 *[19:18]| retime-clk |------>[Retime-Clk ]
122 * +----------------+
123 *[17:16]| reserved-1 |
124 * +----------------+
125 *[15..0]| retime-delay |------>[Retime Delay]
126 * +----------------+
275 * of each gpio pin in a GPIO bank.
277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
282 * --------------------------------------------------------
283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
284 * --------------------------------------------------------
288 * ------- ----------------------------
289 * [0-3] - Description
290 * ------- ----------------------------
291 * 0000 - No edge IRQ.
292 * 0001 - Falling edge IRQ.
293 * 0010 - Rising edge IRQ.
294 * 0011 - Rising and Falling edge IRQ.
295 * ------- ----------------------------
360 .oe = -1, /* Not Available */
361 .pu = -1, /* Not Available */
371 struct st_gpio_bank *bank = gpio_range_to_bank(range); in st_get_pio_control() local
373 return &bank->pc; in st_get_pio_control()
385 struct regmap_field *output_enable = pc->oe; in st_pinconf_set_config()
386 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
387 struct regmap_field *open_drain = pc->od; in st_pinconf_set_config()
419 struct regmap_field *alt = pc->alt; in st_pctl_set_function()
435 struct regmap_field *alt = pc->alt; in st_pctl_get_pin_function()
451 int num_delay_times, i, closest_index = -1; in st_pinconf_delay_to_bit()
455 delay_times = data->output_delays; in st_pinconf_delay_to_bit()
456 num_delay_times = data->noutput_delays; in st_pinconf_delay_to_bit()
458 delay_times = data->input_delays; in st_pinconf_delay_to_bit()
459 num_delay_times = data->ninput_delays; in st_pinconf_delay_to_bit()
463 unsigned int divergence = abs(delay - delay_times[i]); in st_pinconf_delay_to_bit()
487 delay_times = data->output_delays; in st_pinconf_bit_to_delay()
488 num_delay_times = data->noutput_delays; in st_pinconf_bit_to_delay()
490 delay_times = data->input_delays; in st_pinconf_bit_to_delay()
491 num_delay_times = data->ninput_delays; in st_pinconf_bit_to_delay()
518 const struct st_pctl_data *data = info->data; in st_pinconf_set_retime_packed()
519 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_set_retime_packed()
522 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, in st_pinconf_set_retime_packed()
525 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, in st_pinconf_set_retime_packed()
528 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, in st_pinconf_set_retime_packed()
531 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, in st_pinconf_set_retime_packed()
534 st_regmap_field_bit_set_clear_pin(rt_p->retime, in st_pinconf_set_retime_packed()
540 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); in st_pinconf_set_retime_packed()
542 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); in st_pinconf_set_retime_packed()
557 info->data, config); in st_pinconf_set_retime_dedicated()
558 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_set_retime_dedicated()
569 regmap_field_write(rt_d->rt[pin], retime_config); in st_pinconf_set_retime_dedicated()
577 if (pc->oe) { in st_pinconf_get_direction()
578 regmap_field_read(pc->oe, &oe_value); in st_pinconf_get_direction()
583 if (pc->pu) { in st_pinconf_get_direction()
584 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
589 if (pc->od) { in st_pinconf_get_direction()
590 regmap_field_read(pc->od, &od_value); in st_pinconf_get_direction()
599 const struct st_pctl_data *data = info->data; in st_pinconf_get_retime_packed()
600 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_get_retime_packed()
604 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
607 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
610 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
613 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
616 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
619 regmap_field_read(rt_p->delay_0, &delay0); in st_pinconf_get_retime_packed()
620 regmap_field_read(rt_p->delay_1, &delay1); in st_pinconf_get_retime_packed()
635 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_get_retime_dedicated()
637 regmap_field_read(rt_d->rt[pin], &value); in st_pinconf_get_retime_dedicated()
643 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); in st_pinconf_get_retime_dedicated()
663 static inline void __st_gpio_set(struct st_gpio_bank *bank, in __st_gpio_set() argument
667 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); in __st_gpio_set()
669 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); in __st_gpio_set()
672 static void st_gpio_direction(struct st_gpio_bank *bank, in st_gpio_direction() argument
686 * 0 0 0 [Input Weak pull-up] in st_gpio_direction()
696 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); in st_gpio_direction()
698 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); in st_gpio_direction()
704 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_get() local
706 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); in st_gpio_get()
711 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_set() local
712 __st_gpio_set(bank, offset, value); in st_gpio_set()
720 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_direction_output() local
722 __st_gpio_set(bank, offset, value); in st_gpio_direction_output()
729 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_get_direction() local
730 struct st_pio_control pc = bank->pc; in st_gpio_get_direction()
749 * - See st_gpio_direction() above for an explanation in st_gpio_get_direction()
752 value = readl(bank->base + REG_PIO_PC(i)); in st_gpio_get_direction()
767 return info->ngroups; in st_pctl_get_groups_count()
775 return info->groups[selector].name; in st_pctl_get_group_name()
783 if (selector >= info->ngroups) in st_pctl_get_group_pins()
784 return -EINVAL; in st_pctl_get_group_pins()
786 *pins = info->groups[selector].pins; in st_pctl_get_group_pins()
787 *npins = info->groups[selector].npins; in st_pctl_get_group_pins()
797 for (i = 0; i < info->ngroups; i++) { in st_pctl_find_group_by_name()
798 if (!strcmp(info->groups[i].name, name)) in st_pctl_find_group_by_name()
799 return &info->groups[i]; in st_pctl_find_group_by_name()
810 struct device *dev = info->dev; in st_pctl_dt_node_to_map()
815 grp = st_pctl_find_group_by_name(info, np->name); in st_pctl_dt_node_to_map()
818 return -EINVAL; in st_pctl_dt_node_to_map()
821 map_num = grp->npins + 1; in st_pctl_dt_node_to_map()
824 return -ENOMEM; in st_pctl_dt_node_to_map()
829 return -EINVAL; in st_pctl_dt_node_to_map()
835 new_map[0].data.mux.function = parent->name; in st_pctl_dt_node_to_map()
836 new_map[0].data.mux.group = np->name; in st_pctl_dt_node_to_map()
841 for (i = 0; i < grp->npins; i++) { in st_pctl_dt_node_to_map()
844 pin_get_name(pctldev, grp->pins[i]); in st_pctl_dt_node_to_map()
845 new_map[i].data.configs.configs = &grp->pin_conf[i].config; in st_pctl_dt_node_to_map()
849 (*map)->data.mux.function, grp->name, map_num); in st_pctl_dt_node_to_map()
872 return info->nfunctions; in st_pmx_get_funcs_count()
880 return info->functions[selector].name; in st_pmx_get_fname()
887 *grps = info->functions[selector].groups; in st_pmx_get_groups()
888 *ngrps = info->functions[selector].ngroups; in st_pmx_get_groups()
897 struct st_pinconf *conf = info->groups[group].pin_conf; in st_pmx_set_mux()
901 for (i = 0; i < info->groups[group].npins; i++) { in st_pmx_set_mux()
913 struct st_gpio_bank *bank = gpio_range_to_bank(range); in st_pmx_set_gpio_direction() local
915 * When a PIO bank is used in its primary function mode (altfunc = 0) in st_pmx_set_gpio_direction()
919 st_pctl_set_function(&bank->pc, gpio, 0); in st_pmx_set_gpio_direction()
920 st_gpio_direction(bank, gpio, input ? in st_pmx_set_gpio_direction()
939 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_get_retime()
941 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_get_retime()
942 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_get_retime()
950 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_set_retime()
952 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_set_retime()
953 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_set_retime()
998 mutex_unlock(&pctldev->mutex); in st_pinconf_dbg_show()
1001 mutex_lock(&pctldev->mutex); in st_pinconf_dbg_show()
1009 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); in st_pinconf_dbg_show()
1012 "de:%ld,rt-clk:%ld,rt-delay:%ld]", in st_pinconf_dbg_show()
1036 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_dt_child_count()
1037 info->nbanks++; in st_pctl_dt_child_count()
1039 info->nfunctions++; in st_pctl_dt_child_count()
1040 info->ngroups += of_get_child_count(child); in st_pctl_dt_child_count()
1046 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime_packed() argument
1048 struct device *dev = info->dev; in st_pctl_dt_setup_retime_packed()
1049 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_packed()
1050 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_packed()
1051 /* 2 registers per bank */ in st_pctl_dt_setup_retime_packed()
1052 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_packed()
1053 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pctl_dt_setup_retime_packed()
1064 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); in st_pctl_dt_setup_retime_packed()
1065 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); in st_pctl_dt_setup_retime_packed()
1066 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); in st_pctl_dt_setup_retime_packed()
1067 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); in st_pctl_dt_setup_retime_packed()
1068 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); in st_pctl_dt_setup_retime_packed()
1069 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); in st_pctl_dt_setup_retime_packed()
1070 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); in st_pctl_dt_setup_retime_packed()
1072 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || in st_pctl_dt_setup_retime_packed()
1073 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || in st_pctl_dt_setup_retime_packed()
1074 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || in st_pctl_dt_setup_retime_packed()
1075 IS_ERR(rt_p->double_edge)) in st_pctl_dt_setup_retime_packed()
1076 return -EINVAL; in st_pctl_dt_setup_retime_packed()
1082 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime_dedicated() argument
1084 struct device *dev = info->dev; in st_pctl_dt_setup_retime_dedicated()
1085 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_dedicated()
1086 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_dedicated()
1087 /* 8 registers per bank */ in st_pctl_dt_setup_retime_dedicated()
1088 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_dedicated()
1089 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pctl_dt_setup_retime_dedicated()
1091 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated()
1096 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); in st_pctl_dt_setup_retime_dedicated()
1097 if (IS_ERR(rt_d->rt[j])) in st_pctl_dt_setup_retime_dedicated()
1098 return -EINVAL; in st_pctl_dt_setup_retime_dedicated()
1106 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime() argument
1108 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime()
1109 if (data->rt_style == st_retime_style_packed) in st_pctl_dt_setup_retime()
1110 return st_pctl_dt_setup_retime_packed(info, bank, pc); in st_pctl_dt_setup_retime()
1111 else if (data->rt_style == st_retime_style_dedicated) in st_pctl_dt_setup_retime()
1112 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); in st_pctl_dt_setup_retime()
1114 return -EINVAL; in st_pctl_dt_setup_retime()
1119 struct regmap *regmap, int bank, in st_pc_get_value() argument
1122 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); in st_pc_get_value()
1130 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, in st_parse_syscfgs() argument
1133 const struct st_pctl_data *data = info->data; in st_parse_syscfgs()
1135 * For a given shared register like OE/PU/OD, there are 8 bits per bank in st_parse_syscfgs()
1139 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; in st_parse_syscfgs()
1140 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; in st_parse_syscfgs()
1141 struct st_pio_control *pc = &info->banks[bank].pc; in st_parse_syscfgs()
1142 struct device *dev = info->dev; in st_parse_syscfgs()
1143 struct regmap *regmap = info->regmap; in st_parse_syscfgs()
1145 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); in st_parse_syscfgs()
1146 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); in st_parse_syscfgs()
1147 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
1148 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); in st_parse_syscfgs()
1151 pc->rt_pin_mask = 0xff; in st_parse_syscfgs()
1152 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); in st_parse_syscfgs()
1153 st_pctl_dt_setup_retime(info, bank, pc); in st_parse_syscfgs()
1159 phandle bank, unsigned int offset) in st_pctl_dt_calculate_pin() argument
1163 int retval = -EINVAL; in st_pctl_dt_calculate_pin()
1166 np = of_find_node_by_phandle(bank); in st_pctl_dt_calculate_pin()
1168 return -EINVAL; in st_pctl_dt_calculate_pin()
1170 for (i = 0; i < info->nbanks; i++) { in st_pctl_dt_calculate_pin()
1171 chip = &info->banks[i].gpio_chip; in st_pctl_dt_calculate_pin()
1172 if (chip->fwnode == of_fwnode_handle(np)) { in st_pctl_dt_calculate_pin()
1173 if (offset < chip->ngpio) in st_pctl_dt_calculate_pin()
1174 retval = chip->base + offset; in st_pctl_dt_calculate_pin()
1185 * <bank offset mux direction rt_type rt_delay rt_clk>
1190 /* bank pad direction val altfunction */ in st_pctl_dt_parse_groups()
1193 struct device *dev = info->dev; in st_pctl_dt_parse_groups()
1196 phandle bank; in st_pctl_dt_parse_groups() local
1202 return -ENODATA; in st_pctl_dt_parse_groups()
1206 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1209 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { in st_pctl_dt_parse_groups()
1213 return -EINVAL; in st_pctl_dt_parse_groups()
1217 grp->npins = npins; in st_pctl_dt_parse_groups()
1218 grp->name = np->name; in st_pctl_dt_parse_groups()
1219 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); in st_pctl_dt_parse_groups()
1220 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); in st_pctl_dt_parse_groups()
1222 if (!grp->pins || !grp->pin_conf) in st_pctl_dt_parse_groups()
1223 return -ENOMEM; in st_pctl_dt_parse_groups()
1225 /* <bank offset mux direction rt_type rt_delay rt_clk> */ in st_pctl_dt_parse_groups()
1227 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1229 nr_props = pp->length/sizeof(u32); in st_pctl_dt_parse_groups()
1230 list = pp->value; in st_pctl_dt_parse_groups()
1231 conf = &grp->pin_conf[i]; in st_pctl_dt_parse_groups()
1233 /* bank & offset */ in st_pctl_dt_parse_groups()
1234 bank = be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1236 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); in st_pctl_dt_parse_groups()
1237 conf->name = pp->name; in st_pctl_dt_parse_groups()
1238 grp->pins[i] = conf->pin; in st_pctl_dt_parse_groups()
1240 conf->altfunc = be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1241 conf->config = 0; in st_pctl_dt_parse_groups()
1243 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1247 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1249 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1252 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1263 struct device *dev = info->dev; in st_pctl_parse_functions()
1268 func = &info->functions[index]; in st_pctl_parse_functions()
1269 func->name = np->name; in st_pctl_parse_functions()
1270 func->ngroups = of_get_child_count(np); in st_pctl_parse_functions()
1271 if (func->ngroups == 0) in st_pctl_parse_functions()
1272 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); in st_pctl_parse_functions()
1273 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in st_pctl_parse_functions()
1274 if (!func->groups) in st_pctl_parse_functions()
1275 return -ENOMEM; in st_pctl_parse_functions()
1279 func->groups[i] = child->name; in st_pctl_parse_functions()
1280 grp = &info->groups[*grp_index]; in st_pctl_parse_functions()
1286 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); in st_pctl_parse_functions()
1294 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_mask() local
1296 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); in st_gpio_irq_mask()
1303 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_unmask() local
1306 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); in st_gpio_irq_unmask()
1313 pinctrl_gpio_direction_input(gc, d->hwirq); in st_gpio_irq_request_resources()
1315 return gpiochip_reqres_irq(gc, d->hwirq); in st_gpio_irq_request_resources()
1322 gpiochip_relres_irq(gc, d->hwirq); in st_gpio_irq_release_resources()
1328 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_set_type() local
1330 int comp, pin = d->hwirq; in st_gpio_irq_set_type()
1350 comp = st_gpio_get(&bank->gpio_chip, pin); in st_gpio_irq_set_type()
1354 return -EINVAL; in st_gpio_irq_set_type()
1357 spin_lock_irqsave(&bank->lock, flags); in st_gpio_irq_set_type()
1358 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( in st_gpio_irq_set_type()
1360 bank->irq_edge_conf |= pin_edge_conf; in st_gpio_irq_set_type()
1361 spin_unlock_irqrestore(&bank->lock, flags); in st_gpio_irq_set_type()
1363 val = readl(bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1366 writel(val, bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1379 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1383 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1387 * step-1 ________ __________
1388 * | | step - 3
1390 * step -2 |_____|
1395 static void __gpio_irq_handler(struct st_gpio_bank *bank) in __gpio_irq_handler() argument
1401 spin_lock_irqsave(&bank->lock, flags); in __gpio_irq_handler()
1402 bank_edge_mask = bank->irq_edge_conf; in __gpio_irq_handler()
1403 spin_unlock_irqrestore(&bank->lock, flags); in __gpio_irq_handler()
1406 port_in = readl(bank->base + REG_PIO_PIN); in __gpio_irq_handler()
1407 port_comp = readl(bank->base + REG_PIO_PCOMP); in __gpio_irq_handler()
1408 port_mask = readl(bank->base + REG_PIO_PMASK); in __gpio_irq_handler()
1421 val = st_gpio_get(&bank->gpio_chip, n); in __gpio_irq_handler()
1424 val ? bank->base + REG_PIO_SET_PCOMP : in __gpio_irq_handler()
1425 bank->base + REG_PIO_CLR_PCOMP); in __gpio_irq_handler()
1432 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); in __gpio_irq_handler()
1439 /* interrupt dedicated per bank */ in st_gpio_irq_handler()
1442 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_handler() local
1445 __gpio_irq_handler(bank); in st_gpio_irq_handler()
1458 status = readl(info->irqmux_base); in st_gpio_irqmux_handler()
1460 for_each_set_bit(n, &status, info->nbanks) in st_gpio_irqmux_handler()
1461 __gpio_irq_handler(&info->banks[n]); in st_gpio_irqmux_handler()
1491 struct st_gpio_bank *bank = &info->banks[bank_nr]; in st_gpiolib_register_bank() local
1492 struct pinctrl_gpio_range *range = &bank->range; in st_gpiolib_register_bank()
1493 struct device *dev = info->dev; in st_gpiolib_register_bank()
1499 return -ENODEV; in st_gpiolib_register_bank()
1501 bank->base = devm_ioremap_resource(dev, &res); in st_gpiolib_register_bank()
1502 if (IS_ERR(bank->base)) in st_gpiolib_register_bank()
1503 return PTR_ERR(bank->base); in st_gpiolib_register_bank()
1505 bank->gpio_chip = st_gpio_template; in st_gpiolib_register_bank()
1506 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1507 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1508 bank->gpio_chip.fwnode = of_fwnode_handle(np); in st_gpiolib_register_bank()
1509 bank->gpio_chip.parent = dev; in st_gpiolib_register_bank()
1510 spin_lock_init(&bank->lock); in st_gpiolib_register_bank()
1512 of_property_read_string(np, "st,bank-name", &range->name); in st_gpiolib_register_bank()
1513 bank->gpio_chip.label = range->name; in st_gpiolib_register_bank()
1515 range->id = bank_num; in st_gpiolib_register_bank()
1516 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1517 range->npins = bank->gpio_chip.ngpio; in st_gpiolib_register_bank()
1518 range->gc = &bank->gpio_chip; in st_gpiolib_register_bank()
1521 * GPIO bank can have one of the two possible types of in st_gpiolib_register_bank()
1522 * interrupt-wirings. in st_gpiolib_register_bank()
1528 * | |----> [gpio-bank (n) ] in st_gpiolib_register_bank()
1529 * | |----> [gpio-bank (n + 1)] in st_gpiolib_register_bank()
1530 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] in st_gpiolib_register_bank()
1531 * | |----> [gpio-bank (... )] in st_gpiolib_register_bank()
1532 * |_________|----> [gpio-bank (n + 7)] in st_gpiolib_register_bank()
1534 * Second type has a dedicated interrupt per each gpio bank. in st_gpiolib_register_bank()
1536 * [irqN]----> [gpio-bank (n)] in st_gpiolib_register_bank()
1545 dev_err(dev, "invalid IRQ for %pOF bank\n", np); in st_gpiolib_register_bank()
1549 if (!info->irqmux_base) { in st_gpiolib_register_bank()
1550 dev_err(dev, "no irqmux for %pOF bank\n", np); in st_gpiolib_register_bank()
1554 girq = &bank->gpio_chip.irq; in st_gpiolib_register_bank()
1556 girq->parent_handler = st_gpio_irq_handler; in st_gpiolib_register_bank()
1557 girq->num_parents = 1; in st_gpiolib_register_bank()
1558 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in st_gpiolib_register_bank()
1560 if (!girq->parents) in st_gpiolib_register_bank()
1561 return -ENOMEM; in st_gpiolib_register_bank()
1562 girq->parents[0] = gpio_irq; in st_gpiolib_register_bank()
1563 girq->default_type = IRQ_TYPE_NONE; in st_gpiolib_register_bank()
1564 girq->handler = handle_simple_irq; in st_gpiolib_register_bank()
1568 err = gpiochip_add_data(&bank->gpio_chip, bank); in st_gpiolib_register_bank()
1571 dev_info(dev, "%s bank added.\n", range->name); in st_gpiolib_register_bank()
1577 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1578 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1579 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1580 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1587 struct device *dev = &pdev->dev; in st_pctl_probe_dt()
1589 int i = 0, j = 0, k = 0, bank; in st_pctl_probe_dt() local
1591 struct device_node *np = dev->of_node; in st_pctl_probe_dt()
1596 if (!info->nbanks) in st_pctl_probe_dt()
1597 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); in st_pctl_probe_dt()
1599 dev_info(dev, "nbanks = %d\n", info->nbanks); in st_pctl_probe_dt()
1600 dev_info(dev, "nfunctions = %d\n", info->nfunctions); in st_pctl_probe_dt()
1601 dev_info(dev, "ngroups = %d\n", info->ngroups); in st_pctl_probe_dt()
1603 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in st_pctl_probe_dt()
1605 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in st_pctl_probe_dt()
1607 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); in st_pctl_probe_dt()
1609 if (!info->functions || !info->groups || !info->banks) in st_pctl_probe_dt()
1610 return -ENOMEM; in st_pctl_probe_dt()
1612 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in st_pctl_probe_dt()
1613 if (IS_ERR(info->regmap)) in st_pctl_probe_dt()
1614 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); in st_pctl_probe_dt()
1615 info->data = of_match_node(st_pctl_of_match, np)->data; in st_pctl_probe_dt()
1620 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); in st_pctl_probe_dt()
1621 if (IS_ERR(info->irqmux_base)) in st_pctl_probe_dt()
1622 return PTR_ERR(info->irqmux_base); in st_pctl_probe_dt()
1628 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; in st_pctl_probe_dt()
1629 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); in st_pctl_probe_dt()
1631 return -ENOMEM; in st_pctl_probe_dt()
1633 pctl_desc->pins = pdesc; in st_pctl_probe_dt()
1635 bank = 0; in st_pctl_probe_dt()
1637 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_probe_dt()
1641 ret = st_gpiolib_register_bank(info, bank, child); in st_pctl_probe_dt()
1645 k = info->banks[bank].range.pin_base; in st_pctl_probe_dt()
1646 bank_name = info->banks[bank].range.name; in st_pctl_probe_dt()
1653 pdesc->number = k; in st_pctl_probe_dt()
1654 pdesc->name = pin_names[j]; in st_pctl_probe_dt()
1657 st_parse_syscfgs(info, bank, child); in st_pctl_probe_dt()
1658 bank++; in st_pctl_probe_dt()
1674 struct device *dev = &pdev->dev; in st_pctl_probe()
1679 if (!dev->of_node) { in st_pctl_probe()
1681 return -EINVAL; in st_pctl_probe()
1686 return -ENOMEM; in st_pctl_probe()
1690 return -ENOMEM; in st_pctl_probe()
1692 info->dev = dev; in st_pctl_probe()
1698 pctl_desc->owner = THIS_MODULE; in st_pctl_probe()
1699 pctl_desc->pctlops = &st_pctlops; in st_pctl_probe()
1700 pctl_desc->pmxops = &st_pmxops; in st_pctl_probe()
1701 pctl_desc->confops = &st_confops; in st_pctl_probe()
1702 pctl_desc->name = dev_name(dev); in st_pctl_probe()
1704 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); in st_pctl_probe()
1705 if (IS_ERR(info->pctl)) in st_pctl_probe()
1706 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); in st_pctl_probe()
1708 for (i = 0; i < info->nbanks; i++) in st_pctl_probe()
1709 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); in st_pctl_probe()
1716 .name = "st-pinctrl",