Lines Matching +full:function +full:- +full:mask
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
44 * @mask: mask
49 unsigned mask; member
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
54 * and value, enable, disable, mask
59 * @mask: mask bits in the register value
66 unsigned mask; member
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
81 * @name: pinctrl function name
98 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
100 * @npins: number pins with the same mux value of gpio function
101 * @gpiofunc: mux value of gpio function
112 * struct pcs_data - wrapper for data needed by pinctrl framework
126 * struct pcs_soc_data - SoC specific settings
129 * @irq_enable_mask: optional SoC specific interrupt enable mask
130 * @irq_status_mask: optional SoC specific interrupt status mask
131 * @rearm: optional SoC specific wake-up rearm function
142 * struct pcs_device - pinctrl device instance
150 * @flags: mask of PCS_FEAT_xxx values
156 * @fmask: function register mask
157 * @fshift: function register shift
168 * @read: register read function to use
169 * @write: register write function to use
205 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
206 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
207 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
271 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
273 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
276 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
286 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
301 val = pcs->read(pcs->base + offset); in pcs_pin_dbg_show()
303 if (pcs->bits_per_mux) in pcs_pin_dbg_show()
304 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); in pcs_pin_dbg_show()
306 pa = pcs->res->start + offset; in pcs_pin_dbg_show()
317 devm_kfree(pcs->dev, map); in pcs_dt_free_map()
339 struct function_desc *function; in pcs_get_function() local
343 setting = pdesc->mux_setting; in pcs_get_function()
345 return -ENOTSUPP; in pcs_get_function()
346 fselector = setting->func; in pcs_get_function()
347 function = pinmux_generic_get_function(pctldev, fselector); in pcs_get_function()
348 if (!function) in pcs_get_function()
349 return -EINVAL; in pcs_get_function()
350 *func = function->data; in pcs_get_function()
352 dev_err(pcs->dev, "%s could not find function%i\n", in pcs_get_function()
354 return -ENOTSUPP; in pcs_get_function()
363 struct function_desc *function; in pcs_set_mux() local
368 /* If function mask is null, needn't enable it. */ in pcs_set_mux()
369 if (!pcs->fmask) in pcs_set_mux()
371 function = pinmux_generic_get_function(pctldev, fselector); in pcs_set_mux()
372 if (!function) in pcs_set_mux()
373 return -EINVAL; in pcs_set_mux()
374 func = function->data; in pcs_set_mux()
376 return -EINVAL; in pcs_set_mux()
378 dev_dbg(pcs->dev, "enabling %s function%i\n", in pcs_set_mux()
379 func->name, fselector); in pcs_set_mux()
381 for (i = 0; i < func->nvals; i++) { in pcs_set_mux()
384 unsigned val, mask; in pcs_set_mux() local
386 vals = &func->vals[i]; in pcs_set_mux()
387 raw_spin_lock_irqsave(&pcs->lock, flags); in pcs_set_mux()
388 val = pcs->read(vals->reg); in pcs_set_mux()
390 if (pcs->bits_per_mux) in pcs_set_mux()
391 mask = vals->mask; in pcs_set_mux()
393 mask = pcs->fmask; in pcs_set_mux()
395 val &= ~mask; in pcs_set_mux()
396 val |= (vals->val & mask); in pcs_set_mux()
397 pcs->write(val, vals->reg); in pcs_set_mux()
398 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pcs_set_mux()
412 /* If function mask is null, return directly. */ in pcs_request_gpio()
413 if (!pcs->fmask) in pcs_request_gpio()
414 return -ENOTSUPP; in pcs_request_gpio()
416 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { in pcs_request_gpio()
420 if (pin >= frange->offset + frange->npins in pcs_request_gpio()
421 || pin < frange->offset) in pcs_request_gpio()
426 if (pcs->bits_per_mux) { in pcs_request_gpio()
429 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
430 data &= ~(pcs->fmask << pin_shift); in pcs_request_gpio()
431 data |= frange->gpiofunc << pin_shift; in pcs_request_gpio()
432 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
434 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
435 data &= ~pcs->fmask; in pcs_request_gpio()
436 data |= frange->gpiofunc; in pcs_request_gpio()
437 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
494 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_get()
501 return -ENOTSUPP; in pcs_pinconf_get()
503 } else if (param != func->conf[i].param) { in pcs_pinconf_get()
507 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_get()
508 data = pcs->read(pcs->base + offset) & func->conf[i].mask; in pcs_pinconf_get()
509 switch (func->conf[i].param) { in pcs_pinconf_get()
514 if ((data != func->conf[i].enable) || in pcs_pinconf_get()
515 (data == func->conf[i].disable)) in pcs_pinconf_get()
516 return -ENOTSUPP; in pcs_pinconf_get()
521 for (j = 0; j < func->nconfs; j++) { in pcs_pinconf_get()
522 switch (func->conf[j].param) { in pcs_pinconf_get()
524 if (data != func->conf[j].enable) in pcs_pinconf_get()
525 return -ENOTSUPP; in pcs_pinconf_get()
543 return -ENOTSUPP; in pcs_pinconf_get()
564 /* BIAS_DISABLE has no entry in the func->conf table */ in pcs_pinconf_set()
571 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_set()
572 if (param != func->conf[i].param) in pcs_pinconf_set()
575 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_set()
576 data = pcs->read(pcs->base + offset); in pcs_pinconf_set()
585 shift = ffs(func->conf[i].mask) - 1; in pcs_pinconf_set()
586 data &= ~func->conf[i].mask; in pcs_pinconf_set()
587 data |= (arg << shift) & func->conf[i].mask; in pcs_pinconf_set()
596 data &= ~func->conf[i].mask; in pcs_pinconf_set()
598 data |= func->conf[i].enable; in pcs_pinconf_set()
600 data |= func->conf[i].disable; in pcs_pinconf_set()
603 return -ENOTSUPP; in pcs_pinconf_set()
605 pcs->write(data, pcs->base + offset); in pcs_pinconf_set()
609 if (i >= func->nconfs) in pcs_pinconf_set()
610 return -ENOTSUPP; in pcs_pinconf_set()
628 return -ENOTSUPP; in pcs_pinconf_group_get()
631 return -ENOTSUPP; in pcs_pinconf_group_get()
650 return -ENOTSUPP; in pcs_pinconf_group_set()
684 * pcs_add_pin() - add a pin to the static per controller pin array
690 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_add_pin()
694 i = pcs->pins.cur; in pcs_add_pin()
695 if (i >= pcs->desc.npins) { in pcs_add_pin()
696 dev_err(pcs->dev, "too many pins, max %i\n", in pcs_add_pin()
697 pcs->desc.npins); in pcs_add_pin()
698 return -ENOMEM; in pcs_add_pin()
701 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
704 val = pcs->read(pcs->base + offset); in pcs_add_pin()
705 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
706 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", in pcs_add_pin()
707 (unsigned long)pcs->res->start + offset, val); in pcs_add_pin()
708 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
709 pcs->write(val, pcs->base + offset); in pcs_add_pin()
713 pin = &pcs->pins.pa[i]; in pcs_add_pin()
714 pin->number = i; in pcs_add_pin()
715 pcs->pins.cur++; in pcs_add_pin()
721 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
733 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_allocate_pin_table()
735 if (pcs->bits_per_mux && pcs->fmask) { in pcs_allocate_pin_table()
736 pcs->bits_per_pin = fls(pcs->fmask); in pcs_allocate_pin_table()
737 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_allocate_pin_table()
739 nr_pins = pcs->size / mux_bytes; in pcs_allocate_pin_table()
742 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); in pcs_allocate_pin_table()
743 pcs->pins.pa = devm_kcalloc(pcs->dev, in pcs_allocate_pin_table()
744 nr_pins, sizeof(*pcs->pins.pa), in pcs_allocate_pin_table()
746 if (!pcs->pins.pa) in pcs_allocate_pin_table()
747 return -ENOMEM; in pcs_allocate_pin_table()
749 pcs->desc.pins = pcs->pins.pa; in pcs_allocate_pin_table()
750 pcs->desc.npins = nr_pins; in pcs_allocate_pin_table()
752 for (i = 0; i < pcs->desc.npins; i++) { in pcs_allocate_pin_table()
759 dev_err(pcs->dev, "error adding pins: %i\n", res); in pcs_allocate_pin_table()
768 * pcs_add_function() - adds a new function to the function list
770 * @fcn: new function allocated
771 * @name: name of the function
772 * @vals: array of mux register value pairs used by the function
774 * @pgnames: array of pingroup names for the function
787 struct pcs_function *function; in pcs_add_function() local
790 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); in pcs_add_function()
791 if (!function) in pcs_add_function()
792 return -ENOMEM; in pcs_add_function()
794 function->vals = vals; in pcs_add_function()
795 function->nvals = nvals; in pcs_add_function()
796 function->name = name; in pcs_add_function()
798 selector = pinmux_generic_add_function(pcs->pctl, name, in pcs_add_function()
800 function); in pcs_add_function()
802 devm_kfree(pcs->dev, function); in pcs_add_function()
805 *fcn = function; in pcs_add_function()
812 * pcs_get_pin_by_offset() - get a pin index based on the register offset
822 if (offset >= pcs->size) { in pcs_get_pin_by_offset()
823 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", in pcs_get_pin_by_offset()
824 offset, pcs->size); in pcs_get_pin_by_offset()
825 return -EINVAL; in pcs_get_pin_by_offset()
828 if (pcs->bits_per_mux) in pcs_get_pin_by_offset()
829 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_get_pin_by_offset()
831 index = offset / (pcs->width / BITS_PER_BYTE); in pcs_get_pin_by_offset()
843 int ret = -EINVAL; in pcs_config_match()
854 unsigned mask) in add_config() argument
856 (*conf)->param = param; in add_config()
857 (*conf)->val = value; in add_config()
858 (*conf)->enable = enable; in add_config()
859 (*conf)->disable = disable; in add_config()
860 (*conf)->mask = mask; in add_config()
882 /* set value & mask */ in pcs_add_conf2()
884 shift = ffs(value[1]) - 1; in pcs_add_conf2()
898 /* value to set, enable, disable, mask */ in pcs_add_conf4()
903 dev_err(pcs->dev, "mask field of the property can't be 0\n"); in pcs_add_conf4()
911 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); in pcs_add_conf4()
926 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, in pcs_parse_pinconf()
927 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, in pcs_parse_pinconf()
928 { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, }, in pcs_parse_pinconf()
929 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, in pcs_parse_pinconf()
930 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, in pcs_parse_pinconf()
933 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, in pcs_parse_pinconf()
934 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, in pcs_parse_pinconf()
935 { "pinctrl-single,input-schmitt-enable", in pcs_parse_pinconf()
941 return -ENOTSUPP; in pcs_parse_pinconf()
953 return -ENOTSUPP; in pcs_parse_pinconf()
955 func->conf = devm_kcalloc(pcs->dev, in pcs_parse_pinconf()
958 if (!func->conf) in pcs_parse_pinconf()
959 return -ENOMEM; in pcs_parse_pinconf()
960 func->nconfs = nconfs; in pcs_parse_pinconf()
961 conf = &(func->conf[0]); in pcs_parse_pinconf()
963 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), in pcs_parse_pinconf()
966 return -ENOMEM; in pcs_parse_pinconf()
975 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; in pcs_parse_pinconf()
976 m->data.configs.group_or_pin = np->name; in pcs_parse_pinconf()
977 m->data.configs.configs = settings; in pcs_parse_pinconf()
978 m->data.configs.num_configs = nconfs; in pcs_parse_pinconf()
983 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
992 * Also note that this driver tries to avoid understanding pin and function
996 * decipher the pin and function names using debugfs.
1007 const char *name = "pinctrl-single,pins"; in pcs_parse_one_pinctrl_entry()
1009 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_one_pinctrl_entry()
1010 struct pcs_function *function = NULL; in pcs_parse_one_pinctrl_entry() local
1014 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_one_pinctrl_entry()
1015 return -EINVAL; in pcs_parse_one_pinctrl_entry()
1018 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1020 return -ENOMEM; in pcs_parse_one_pinctrl_entry()
1022 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1036 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_one_pinctrl_entry()
1042 vals[found].reg = pcs->base + offset; in pcs_parse_one_pinctrl_entry()
1053 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", in pcs_parse_one_pinctrl_entry()
1058 dev_err(pcs->dev, in pcs_parse_one_pinctrl_entry()
1066 pgnames[0] = np->name; in pcs_parse_one_pinctrl_entry()
1067 mutex_lock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1068 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_one_pinctrl_entry()
1075 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_one_pinctrl_entry()
1081 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_one_pinctrl_entry()
1082 (*map)->data.mux.group = np->name; in pcs_parse_one_pinctrl_entry()
1083 (*map)->data.mux.function = np->name; in pcs_parse_one_pinctrl_entry()
1085 if (PCS_HAS_PINCONF && function) { in pcs_parse_one_pinctrl_entry()
1086 res = pcs_parse_pinconf(pcs, np, function, map); in pcs_parse_one_pinctrl_entry()
1089 else if (res == -ENOTSUPP) in pcs_parse_one_pinctrl_entry()
1096 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1101 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_one_pinctrl_entry()
1104 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_one_pinctrl_entry()
1106 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1107 devm_kfree(pcs->dev, pins); in pcs_parse_one_pinctrl_entry()
1110 devm_kfree(pcs->dev, vals); in pcs_parse_one_pinctrl_entry()
1121 const char *name = "pinctrl-single,bits"; in pcs_parse_bits_in_pinctrl_entry()
1123 int rows, *pins, found = 0, res = -ENOMEM, i, fsel; in pcs_parse_bits_in_pinctrl_entry()
1125 struct pcs_function *function = NULL; in pcs_parse_bits_in_pinctrl_entry() local
1129 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_bits_in_pinctrl_entry()
1130 return -EINVAL; in pcs_parse_bits_in_pinctrl_entry()
1134 dev_err(pcs->dev, "pinconf not supported\n"); in pcs_parse_bits_in_pinctrl_entry()
1135 return -ENOTSUPP; in pcs_parse_bits_in_pinctrl_entry()
1138 npins_in_row = pcs->width / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1140 vals = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1144 return -ENOMEM; in pcs_parse_bits_in_pinctrl_entry()
1146 pins = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1155 unsigned mask, bit_pos, val_pos, mask_pos, submask; in pcs_parse_bits_in_pinctrl_entry() local
1164 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_bits_in_pinctrl_entry()
1172 mask = pinctrl_spec.args[2]; in pcs_parse_bits_in_pinctrl_entry()
1174 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1175 pinctrl_spec.np, offset, val, mask); in pcs_parse_bits_in_pinctrl_entry()
1178 while (mask) { in pcs_parse_bits_in_pinctrl_entry()
1179 bit_pos = __ffs(mask); in pcs_parse_bits_in_pinctrl_entry()
1180 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1181 mask_pos = ((pcs->fmask) << bit_pos); in pcs_parse_bits_in_pinctrl_entry()
1183 submask = mask & mask_pos; in pcs_parse_bits_in_pinctrl_entry()
1185 if ((mask & mask_pos) == 0) { in pcs_parse_bits_in_pinctrl_entry()
1186 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1187 "Invalid mask for %pOFn at 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1192 mask &= ~mask_pos; in pcs_parse_bits_in_pinctrl_entry()
1195 dev_warn(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1201 vals[found].mask = submask; in pcs_parse_bits_in_pinctrl_entry()
1202 vals[found].reg = pcs->base + offset; in pcs_parse_bits_in_pinctrl_entry()
1207 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1216 pgnames[0] = np->name; in pcs_parse_bits_in_pinctrl_entry()
1217 mutex_lock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1218 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_bits_in_pinctrl_entry()
1225 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_bits_in_pinctrl_entry()
1229 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_bits_in_pinctrl_entry()
1230 (*map)->data.mux.group = np->name; in pcs_parse_bits_in_pinctrl_entry()
1231 (*map)->data.mux.function = np->name; in pcs_parse_bits_in_pinctrl_entry()
1234 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1239 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_bits_in_pinctrl_entry()
1241 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1242 devm_kfree(pcs->dev, pins); in pcs_parse_bits_in_pinctrl_entry()
1245 devm_kfree(pcs->dev, vals); in pcs_parse_bits_in_pinctrl_entry()
1250 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1267 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); in pcs_dt_node_to_map()
1269 return -ENOMEM; in pcs_dt_node_to_map()
1273 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); in pcs_dt_node_to_map()
1275 ret = -ENOMEM; in pcs_dt_node_to_map()
1279 if (pcs->bits_per_mux) { in pcs_dt_node_to_map()
1283 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1291 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1300 devm_kfree(pcs->dev, pgnames); in pcs_dt_node_to_map()
1302 devm_kfree(pcs->dev, *map); in pcs_dt_node_to_map()
1308 * pcs_irq_free() - free interrupt
1313 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_free()
1315 if (pcs_soc->irq < 0) in pcs_irq_free()
1318 if (pcs->domain) in pcs_irq_free()
1319 irq_domain_remove(pcs->domain); in pcs_irq_free()
1322 free_irq(pcs_soc->irq, pcs_soc); in pcs_irq_free()
1324 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_free()
1328 * pcs_free_resources() - free memory used by this driver
1336 if (pcs->missing_nr_pinctrl_cells) in pcs_free_resources()
1337 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); in pcs_free_resources()
1343 const char *propname = "pinctrl-single,gpio-range"; in pcs_add_gpio_func()
1344 const char *cellname = "#pinctrl-single,gpio-range-cells"; in pcs_add_gpio_func()
1357 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); in pcs_add_gpio_func()
1359 ret = -ENOMEM; in pcs_add_gpio_func()
1362 range->offset = gpiospec.args[0]; in pcs_add_gpio_func()
1363 range->npins = gpiospec.args[1]; in pcs_add_gpio_func()
1364 range->gpiofunc = gpiospec.args[2]; in pcs_add_gpio_func()
1365 mutex_lock(&pcs->mutex); in pcs_add_gpio_func()
1366 list_add_tail(&range->node, &pcs->gpiofuncs); in pcs_add_gpio_func()
1367 mutex_unlock(&pcs->mutex); in pcs_add_gpio_func()
1387 * pcs_irq_set() - enables or disables an interrupt
1393 * register that is typically used for wake-up events.
1400 unsigned mask; in pcs_irq_set() local
1403 list_for_each(pos, &pcs->irqs) { in pcs_irq_set()
1408 if (irq != pcswi->irq) in pcs_irq_set()
1411 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1412 raw_spin_lock(&pcs->lock); in pcs_irq_set()
1413 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1415 mask |= soc_mask; in pcs_irq_set()
1417 mask &= ~soc_mask; in pcs_irq_set()
1418 pcs->write(mask, pcswi->reg); in pcs_irq_set()
1421 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1422 raw_spin_unlock(&pcs->lock); in pcs_irq_set()
1425 if (pcs_soc->rearm) in pcs_irq_set()
1426 pcs_soc->rearm(); in pcs_irq_set()
1430 * pcs_irq_mask() - mask pinctrl interrupt
1437 pcs_irq_set(pcs_soc, d->irq, false); in pcs_irq_mask()
1441 * pcs_irq_unmask() - unmask pinctrl interrupt
1448 pcs_irq_set(pcs_soc, d->irq, true); in pcs_irq_unmask()
1452 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1454 * @state: wake-up state
1457 * For runtime PM, the wake-up events should be enabled by default.
1470 * pcs_irq_handle() - common interrupt handler
1474 * mux register. This interrupt is typically used for wake-up events.
1484 list_for_each(pos, &pcs->irqs) { in pcs_irq_handle()
1486 unsigned mask; in pcs_irq_handle() local
1489 raw_spin_lock(&pcs->lock); in pcs_irq_handle()
1490 mask = pcs->read(pcswi->reg); in pcs_irq_handle()
1491 raw_spin_unlock(&pcs->lock); in pcs_irq_handle()
1492 if (mask & pcs_soc->irq_status_mask) { in pcs_irq_handle()
1493 generic_handle_domain_irq(pcs->domain, in pcs_irq_handle()
1494 pcswi->hwirq); in pcs_irq_handle()
1503 * pcs_irq_handler() - handler for the shared interrupt case
1508 * pinctrl-single share a single interrupt like on omaps.
1518 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1522 * pinctrl-single instance.
1539 struct pcs_soc_data *pcs_soc = d->host_data; in pcs_irqdomain_map()
1544 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); in pcs_irqdomain_map()
1546 return -ENOMEM; in pcs_irqdomain_map()
1548 pcswi->reg = pcs->base + hwirq; in pcs_irqdomain_map()
1549 pcswi->hwirq = hwirq; in pcs_irqdomain_map()
1550 pcswi->irq = irq; in pcs_irqdomain_map()
1552 mutex_lock(&pcs->mutex); in pcs_irqdomain_map()
1553 list_add_tail(&pcswi->node, &pcs->irqs); in pcs_irqdomain_map()
1554 mutex_unlock(&pcs->mutex); in pcs_irqdomain_map()
1557 irq_set_chip_and_handler(irq, &pcs->chip, in pcs_irqdomain_map()
1571 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1578 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_init_chained_handler()
1582 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1583 !pcs_soc->irq_status_mask) { in pcs_irq_init_chained_handler()
1584 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1585 return -EINVAL; in pcs_irq_init_chained_handler()
1588 INIT_LIST_HEAD(&pcs->irqs); in pcs_irq_init_chained_handler()
1589 pcs->chip.name = name; in pcs_irq_init_chained_handler()
1590 pcs->chip.irq_ack = pcs_irq_mask; in pcs_irq_init_chained_handler()
1591 pcs->chip.irq_mask = pcs_irq_mask; in pcs_irq_init_chained_handler()
1592 pcs->chip.irq_unmask = pcs_irq_unmask; in pcs_irq_init_chained_handler()
1593 pcs->chip.irq_set_wake = pcs_irq_set_wake; in pcs_irq_init_chained_handler()
1598 res = request_irq(pcs_soc->irq, pcs_irq_handler, in pcs_irq_init_chained_handler()
1603 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1607 irq_set_chained_handler_and_data(pcs_soc->irq, in pcs_irq_init_chained_handler()
1616 * interrupt per function if needed. in pcs_irq_init_chained_handler()
1618 num_irqs = pcs->size; in pcs_irq_init_chained_handler()
1620 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, in pcs_irq_init_chained_handler()
1623 if (!pcs->domain) { in pcs_irq_init_chained_handler()
1624 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_init_chained_handler()
1625 return -EINVAL; in pcs_irq_init_chained_handler()
1638 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_save_context()
1640 if (!pcs->saved_vals) { in pcs_save_context()
1641 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); in pcs_save_context()
1642 if (!pcs->saved_vals) in pcs_save_context()
1643 return -ENOMEM; in pcs_save_context()
1646 switch (pcs->width) { in pcs_save_context()
1648 regsl = pcs->saved_vals; in pcs_save_context()
1649 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1650 *regsl++ = pcs->read(pcs->base + i); in pcs_save_context()
1653 regsw = pcs->saved_vals; in pcs_save_context()
1654 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1655 *regsw++ = pcs->read(pcs->base + i); in pcs_save_context()
1658 regshw = pcs->saved_vals; in pcs_save_context()
1659 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1660 *regshw++ = pcs->read(pcs->base + i); in pcs_save_context()
1674 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_restore_context()
1676 switch (pcs->width) { in pcs_restore_context()
1678 regsl = pcs->saved_vals; in pcs_restore_context()
1679 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1680 pcs->write(*regsl++, pcs->base + i); in pcs_restore_context()
1683 regsw = pcs->saved_vals; in pcs_restore_context()
1684 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1685 pcs->write(*regsw++, pcs->base + i); in pcs_restore_context()
1688 regshw = pcs->saved_vals; in pcs_restore_context()
1689 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1690 pcs->write(*regshw++, pcs->base + i); in pcs_restore_context()
1699 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { in pinctrl_single_suspend_noirq()
1707 return pinctrl_force_sleep(pcs->pctl); in pinctrl_single_suspend_noirq()
1714 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) in pinctrl_single_resume_noirq()
1717 return pinctrl_force_default(pcs->pctl); in pinctrl_single_resume_noirq()
1725 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1730 * Handle legacy binding with no #pinctrl-cells. This should be
1731 * always two pinctrl-single,bit-per-mux and one for others.
1739 const char *name = "#pinctrl-cells"; in pcs_quirk_missing_pinctrl_cells()
1747 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", in pcs_quirk_missing_pinctrl_cells()
1750 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1752 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1754 p->length = sizeof(__be32); in pcs_quirk_missing_pinctrl_cells()
1755 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1756 if (!p->value) in pcs_quirk_missing_pinctrl_cells()
1757 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1758 *(__be32 *)p->value = cpu_to_be32(cells); in pcs_quirk_missing_pinctrl_cells()
1760 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1761 if (!p->name) in pcs_quirk_missing_pinctrl_cells()
1762 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1764 pcs->missing_nr_pinctrl_cells = p; in pcs_quirk_missing_pinctrl_cells()
1767 error = of_add_property(np, pcs->missing_nr_pinctrl_cells); in pcs_quirk_missing_pinctrl_cells()
1775 struct device_node *np = pdev->dev.of_node; in pcs_probe()
1782 soc = of_device_get_match_data(&pdev->dev); in pcs_probe()
1784 return -EINVAL; in pcs_probe()
1786 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); in pcs_probe()
1788 return -ENOMEM; in pcs_probe()
1790 pcs->dev = &pdev->dev; in pcs_probe()
1791 pcs->np = np; in pcs_probe()
1792 raw_spin_lock_init(&pcs->lock); in pcs_probe()
1793 mutex_init(&pcs->mutex); in pcs_probe()
1794 INIT_LIST_HEAD(&pcs->gpiofuncs); in pcs_probe()
1795 pcs->flags = soc->flags; in pcs_probe()
1796 memcpy(&pcs->socdata, soc, sizeof(*soc)); in pcs_probe()
1798 ret = of_property_read_u32(np, "pinctrl-single,register-width", in pcs_probe()
1799 &pcs->width); in pcs_probe()
1801 dev_err(pcs->dev, "register width not specified\n"); in pcs_probe()
1806 ret = of_property_read_u32(np, "pinctrl-single,function-mask", in pcs_probe()
1807 &pcs->fmask); in pcs_probe()
1809 pcs->fshift = __ffs(pcs->fmask); in pcs_probe()
1810 pcs->fmax = pcs->fmask >> pcs->fshift; in pcs_probe()
1812 /* If mask property doesn't exist, function mux is invalid. */ in pcs_probe()
1813 pcs->fmask = 0; in pcs_probe()
1814 pcs->fshift = 0; in pcs_probe()
1815 pcs->fmax = 0; in pcs_probe()
1818 ret = of_property_read_u32(np, "pinctrl-single,function-off", in pcs_probe()
1819 &pcs->foff); in pcs_probe()
1821 pcs->foff = PCS_OFF_DISABLED; in pcs_probe()
1823 pcs->bits_per_mux = of_property_read_bool(np, in pcs_probe()
1824 "pinctrl-single,bit-per-mux"); in pcs_probe()
1826 pcs->bits_per_mux ? 2 : 1); in pcs_probe()
1828 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); in pcs_probe()
1835 dev_err(pcs->dev, "could not get resource\n"); in pcs_probe()
1836 return -ENODEV; in pcs_probe()
1839 pcs->res = devm_request_mem_region(pcs->dev, res->start, in pcs_probe()
1841 if (!pcs->res) { in pcs_probe()
1842 dev_err(pcs->dev, "could not get mem_region\n"); in pcs_probe()
1843 return -EBUSY; in pcs_probe()
1846 pcs->size = resource_size(pcs->res); in pcs_probe()
1847 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); in pcs_probe()
1848 if (!pcs->base) { in pcs_probe()
1849 dev_err(pcs->dev, "could not ioremap\n"); in pcs_probe()
1850 return -ENODEV; in pcs_probe()
1855 switch (pcs->width) { in pcs_probe()
1857 pcs->read = pcs_readb; in pcs_probe()
1858 pcs->write = pcs_writeb; in pcs_probe()
1861 pcs->read = pcs_readw; in pcs_probe()
1862 pcs->write = pcs_writew; in pcs_probe()
1865 pcs->read = pcs_readl; in pcs_probe()
1866 pcs->write = pcs_writel; in pcs_probe()
1872 pcs->desc.name = DRIVER_NAME; in pcs_probe()
1873 pcs->desc.pctlops = &pcs_pinctrl_ops; in pcs_probe()
1874 pcs->desc.pmxops = &pcs_pinmux_ops; in pcs_probe()
1876 pcs->desc.confops = &pcs_pinconf_ops; in pcs_probe()
1877 pcs->desc.owner = THIS_MODULE; in pcs_probe()
1883 ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl); in pcs_probe()
1885 dev_err(pcs->dev, "could not register single pinctrl driver\n"); in pcs_probe()
1893 pcs->socdata.irq = irq_of_parse_and_map(np, 0); in pcs_probe()
1894 if (pcs->socdata.irq) in pcs_probe()
1895 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1898 pdata = dev_get_platdata(&pdev->dev); in pcs_probe()
1900 if (pdata->rearm) in pcs_probe()
1901 pcs->socdata.rearm = pdata->rearm; in pcs_probe()
1902 if (pdata->irq) { in pcs_probe()
1903 pcs->socdata.irq = pdata->irq; in pcs_probe()
1904 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1911 dev_warn(pcs->dev, "initialized with no interrupts\n"); in pcs_probe()
1914 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); in pcs_probe()
1916 ret = pinctrl_enable(pcs->pctl); in pcs_probe()
1969 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1970 { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
1971 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1972 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1973 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1974 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1975 { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 },
1976 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1977 { .compatible = "pinconf-single", .data = &pinconf_single },
1995 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");