Lines Matching +full:px30 +full:- +full:pmu
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
114 { .offset = -1 }, \
115 { .offset = -1 }, \
116 { .offset = -1 }, \
117 { .offset = -1 }, \
120 { .drv_type = type0, .offset = -1 }, \
121 { .drv_type = type1, .offset = -1 }, \
122 { .drv_type = type2, .offset = -1 }, \
123 { .drv_type = type3, .offset = -1 }, \
135 { .type = iom0, .offset = -1 }, \
136 { .type = iom1, .offset = -1 }, \
137 { .type = iom2, .offset = -1 }, \
138 { .type = iom3, .offset = -1 }, \
154 { .offset = -1 }, \
155 { .offset = -1 }, \
156 { .offset = -1 }, \
157 { .offset = -1 }, \
160 { .drv_type = drv0, .offset = -1 }, \
161 { .drv_type = drv1, .offset = -1 }, \
162 { .drv_type = drv2, .offset = -1 }, \
163 { .drv_type = drv3, .offset = -1 }, \
195 { .type = iom0, .offset = -1 }, \
196 { .type = iom1, .offset = -1 }, \
197 { .type = iom2, .offset = -1 }, \
198 { .type = iom3, .offset = -1 }, \
219 { .type = iom0, .offset = -1 }, \
220 { .type = iom1, .offset = -1 }, \
221 { .type = iom2, .offset = -1 }, \
222 { .type = iom3, .offset = -1 }, \
270 for (i = 0; i < info->ngroups; i++) {
271 if (!strcmp(info->groups[i].name, name))
272 return &info->groups[i];
285 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
287 while (pin >= (b->pin_base + b->nr_pins))
297 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
300 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
301 if (b->bank_num == num)
305 return ERR_PTR(-EINVAL);
316 return info->ngroups;
324 return info->groups[selector].name;
333 if (selector >= info->ngroups)
334 return -EINVAL;
336 *pins = info->groups[selector].pins;
337 *npins = info->groups[selector].npins;
348 struct device *dev = info->dev;
358 grp = pinctrl_name_to_group(info, np->name);
361 return -EINVAL;
364 map_num += grp->npins;
368 return -ENOMEM;
377 return -EINVAL;
380 new_map[0].data.mux.function = parent->name;
381 new_map[0].data.mux.group = np->name;
386 for (i = 0; i < grp->npins; i++) {
389 pin_get_name(pctldev, grp->pins[i]);
390 new_map[i].data.configs.configs = grp->data[i].configs;
391 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
395 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
726 struct rockchip_pinctrl *info = bank->drvdata;
727 struct rockchip_pin_ctrl *ctrl = info->ctrl;
731 for (i = 0; i < ctrl->niomux_recalced; i++) {
732 data = &ctrl->iomux_recalced[i];
733 if (data->num == bank->bank_num &&
734 data->pin == pin)
738 if (i >= ctrl->niomux_recalced)
741 *reg = data->reg;
742 *mask = data->mask;
743 *bit = data->bit;
747 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
748 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
749 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
750 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
751 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
752 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
753 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
754 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
755 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
756 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
757 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
758 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
759 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
760 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
761 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
762 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
763 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
764 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
765 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
766 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
767 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
768 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
769 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
770 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
771 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
772 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
773 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
774 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
775 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
776 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
777 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
778 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
779 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
780 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
781 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
782 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
783 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
784 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
785 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
786 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
787 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
788 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
789 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
790 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
791 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
792 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
793 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
794 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
895 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
896 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
897 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
898 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
899 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
900 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
901 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
905 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
906 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
910 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
911 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
912 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
913 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
914 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
915 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
916 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
917 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
918 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
919 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
920 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
921 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
922 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
923 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
924 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
925 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
926 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
927 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
941 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
942 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
943 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
944 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
945 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
946 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
947 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
948 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
954 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
955 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
1073 struct rockchip_pinctrl *info = bank->drvdata;
1074 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1078 for (i = 0; i < ctrl->niomux_routes; i++) {
1079 data = &ctrl->iomux_routes[i];
1080 if ((data->bank_num == bank->bank_num) &&
1081 (data->pin == pin) && (data->func == mux))
1085 if (i >= ctrl->niomux_routes)
1088 *loc = data->route_location;
1089 *reg = data->route_offset;
1090 *value = data->route_val;
1097 struct rockchip_pinctrl *info = bank->drvdata;
1098 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1106 return -EINVAL;
1108 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1109 dev_err(info->dev, "pin %d is unrouted\n", pin);
1110 return -EINVAL;
1113 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1116 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1117 regmap = info->regmap_pmu;
1118 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1119 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1121 regmap = info->regmap_base;
1124 mux_type = bank->iomux[iomux_num].type;
1125 reg = bank->iomux[iomux_num].offset;
1141 if (bank->recalced_mask & BIT(pin))
1144 if (ctrl->type == RK3576) {
1145 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1149 if (ctrl->type == RK3588) {
1150 if (bank->bank_num == 0) {
1154 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1163 regmap = info->regmap_base;
1165 } else if (bank->bank_num > 0) {
1180 struct rockchip_pinctrl *info = bank->drvdata;
1181 struct device *dev = info->dev;
1185 return -EINVAL;
1187 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1189 return -EINVAL;
1192 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1195 return -ENOTSUPP;
1217 struct rockchip_pinctrl *info = bank->drvdata;
1218 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1219 struct device *dev = info->dev;
1230 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1233 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1235 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1236 regmap = info->regmap_pmu;
1237 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1238 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1240 regmap = info->regmap_base;
1243 mux_type = bank->iomux[iomux_num].type;
1244 reg = bank->iomux[iomux_num].offset;
1260 if (bank->recalced_mask & BIT(pin))
1263 if (ctrl->type == RK3576) {
1264 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1268 if (ctrl->type == RK3588) {
1269 if (bank->bank_num == 0) {
1272 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
1280 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1290 regmap = info->regmap_base;
1300 } else if (bank->bank_num > 0) {
1306 return -EINVAL;
1308 if (bank->route_mask & BIT(pin)) {
1316 route_regmap = info->regmap_pmu;
1319 route_regmap = info->regmap_base;
1347 struct rockchip_pinctrl *info = bank->drvdata;
1349 /* The first 32 pins of the first bank are located in PMU */
1350 if (bank->bank_num == 0) {
1351 *regmap = info->regmap_pmu;
1354 *regmap = info->regmap_base;
1358 *reg -= 0x10;
1359 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1379 struct rockchip_pinctrl *info = bank->drvdata;
1381 /* The first 32 pins of the first bank are located in PMU */
1382 if (bank->bank_num == 0) {
1383 *regmap = info->regmap_pmu;
1386 *regmap = info->regmap_base;
1390 *reg -= 0x10;
1391 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1412 struct rockchip_pinctrl *info = bank->drvdata;
1415 if (bank->bank_num == 0) {
1416 *regmap = info->regmap_pmu;
1420 *regmap = info->regmap_base;
1423 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1442 struct rockchip_pinctrl *info = bank->drvdata;
1444 /* The first 24 pins of the first bank are located in PMU */
1445 if (bank->bank_num == 0) {
1446 *regmap = info->regmap_pmu;
1450 *regmap = info->regmap_base;
1452 *reg -= 0x10;
1453 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1473 struct rockchip_pinctrl *info = bank->drvdata;
1475 /* The first 24 pins of the first bank are located in PMU */
1476 if (bank->bank_num == 0) {
1477 *regmap = info->regmap_pmu;
1480 *regmap = info->regmap_base;
1484 *reg -= 0x10;
1485 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1506 struct rockchip_pinctrl *info = bank->drvdata;
1509 if (bank->bank_num == 0) {
1510 *regmap = info->regmap_pmu;
1514 *regmap = info->regmap_base;
1517 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1536 struct rockchip_pinctrl *info = bank->drvdata;
1538 /* The first 24 pins of the first bank are located in PMU */
1539 if (bank->bank_num == 0) {
1541 *regmap = info->regmap_base;
1543 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1548 *regmap = info->regmap_pmu;
1552 *regmap = info->regmap_base;
1553 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1573 struct rockchip_pinctrl *info = bank->drvdata;
1575 /* The first 24 pins of the first bank are located in PMU */
1576 if (bank->bank_num == 0) {
1578 *regmap = info->regmap_base;
1580 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1581 *reg -= 0x4;
1586 *regmap = info->regmap_pmu;
1589 *regmap = info->regmap_base;
1591 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1612 struct rockchip_pinctrl *info = bank->drvdata;
1615 if (bank->bank_num == 0) {
1617 *regmap = info->regmap_base;
1619 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1623 *regmap = info->regmap_pmu;
1627 *regmap = info->regmap_base;
1630 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1646 struct rockchip_pinctrl *info = bank->drvdata;
1648 *regmap = info->regmap_base;
1651 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1666 struct rockchip_pinctrl *info = bank->drvdata;
1668 *regmap = info->regmap_base;
1670 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1684 struct rockchip_pinctrl *info = bank->drvdata;
1686 *regmap = info->regmap_base;
1688 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1706 struct rockchip_pinctrl *info = bank->drvdata;
1709 if (bank->bank_num == 0 && pin_num < 12) {
1710 *regmap = info->regmap_pmu ? info->regmap_pmu
1711 : bank->regmap_pull;
1712 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1717 *regmap = info->regmap_pull ? info->regmap_pull
1718 : info->regmap_base;
1719 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1722 *reg -= 4;
1723 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1731 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1743 struct rockchip_pinctrl *info = bank->drvdata;
1745 /* The first 24 pins of the first bank are located in PMU */
1746 if (bank->bank_num == 0) {
1747 *regmap = info->regmap_pmu;
1754 *regmap = info->regmap_base;
1758 *reg -= 0x10;
1759 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1779 struct rockchip_pinctrl *info = bank->drvdata;
1781 /* The first 24 pins of the first bank are located in PMU */
1782 if (bank->bank_num == 0) {
1783 *regmap = info->regmap_pmu;
1790 *regmap = info->regmap_base;
1794 *reg -= 0x10;
1795 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1811 struct rockchip_pinctrl *info = bank->drvdata;
1813 *regmap = info->regmap_base;
1815 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1830 struct rockchip_pinctrl *info = bank->drvdata;
1832 *regmap = info->regmap_base;
1834 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1849 struct rockchip_pinctrl *info = bank->drvdata;
1851 *regmap = info->regmap_base;
1853 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1868 struct rockchip_pinctrl *info = bank->drvdata;
1870 *regmap = info->regmap_base;
1872 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1888 struct rockchip_pinctrl *info = bank->drvdata;
1890 /* The first 32 pins of the first bank are located in PMU */
1891 if (bank->bank_num == 0) {
1892 *regmap = info->regmap_pmu;
1899 *regmap = info->regmap_base;
1903 *reg -= 0x10;
1904 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1921 struct rockchip_pinctrl *info = bank->drvdata;
1923 /* The first 32 pins of the first bank are located in PMU */
1924 if (bank->bank_num == 0) {
1925 *regmap = info->regmap_pmu;
1932 *regmap = info->regmap_base;
1936 *reg -= 0x10;
1937 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1955 struct rockchip_pinctrl *info = bank->drvdata;
1957 /* The bank0:16 and bank1:32 pins are located in PMU */
1958 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1959 *regmap = info->regmap_pmu;
1962 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1968 *regmap = info->regmap_base;
1972 *reg -= 0x20;
1973 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1987 struct rockchip_pinctrl *info = bank->drvdata;
1990 /* The bank0:16 and bank1:32 pins are located in PMU */
1991 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1992 *regmap = info->regmap_pmu;
1994 *regmap = info->regmap_base;
1996 *reg = bank->drv[drv_num].offset;
1997 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1998 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2018 struct rockchip_pinctrl *info = bank->drvdata;
2020 *regmap = info->regmap_base;
2022 if (bank->bank_num == 0)
2024 else if (bank->bank_num == 1)
2026 else if (bank->bank_num == 2)
2028 else if (bank->bank_num == 3)
2030 else if (bank->bank_num == 4)
2033 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2054 struct rockchip_pinctrl *info = bank->drvdata;
2056 *regmap = info->regmap_base;
2058 if (bank->bank_num == 0)
2060 else if (bank->bank_num == 1)
2062 else if (bank->bank_num == 2)
2064 else if (bank->bank_num == 3)
2066 else if (bank->bank_num == 4)
2069 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2091 struct rockchip_pinctrl *info = bank->drvdata;
2093 *regmap = info->regmap_base;
2095 if (bank->bank_num == 0)
2097 else if (bank->bank_num == 1)
2099 else if (bank->bank_num == 2)
2101 else if (bank->bank_num == 3)
2103 else if (bank->bank_num == 4)
2106 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2127 struct rockchip_pinctrl *info = bank->drvdata;
2129 *regmap = info->regmap_base;
2130 switch (bank->bank_num) {
2152 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2175 struct rockchip_pinctrl *info = bank->drvdata;
2177 *regmap = info->regmap_base;
2178 switch (bank->bank_num) {
2200 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2224 struct rockchip_pinctrl *info = bank->drvdata;
2226 *regmap = info->regmap_base;
2227 switch (bank->bank_num) {
2249 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2270 struct rockchip_pinctrl *info = bank->drvdata;
2272 if (bank->bank_num == 0) {
2273 *regmap = info->regmap_pmu;
2275 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2281 *regmap = info->regmap_base;
2283 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
2303 struct rockchip_pinctrl *info = bank->drvdata;
2305 /* The first 32 pins of the first bank are located in PMU */
2306 if (bank->bank_num == 0) {
2307 *regmap = info->regmap_pmu;
2314 *regmap = info->regmap_base;
2316 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2341 struct rockchip_pinctrl *info = bank->drvdata;
2343 *regmap = info->regmap_base;
2345 if (bank->bank_num == 0 && pin_num < 12)
2347 else if (bank->bank_num == 0)
2348 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
2349 else if (bank->bank_num == 1)
2351 else if (bank->bank_num == 2)
2353 else if (bank->bank_num == 3)
2355 else if (bank->bank_num == 4 && pin_num < 16)
2357 else if (bank->bank_num == 4 && pin_num < 24)
2358 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
2359 else if (bank->bank_num == 4)
2360 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
2362 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2386 struct rockchip_pinctrl *info = bank->drvdata;
2388 *regmap = info->regmap_base;
2390 if (bank->bank_num == 0 && pin_num < 12)
2392 else if (bank->bank_num == 0)
2393 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
2394 else if (bank->bank_num == 1)
2396 else if (bank->bank_num == 2)
2398 else if (bank->bank_num == 3)
2400 else if (bank->bank_num == 4 && pin_num < 16)
2402 else if (bank->bank_num == 4 && pin_num < 24)
2403 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
2404 else if (bank->bank_num == 4)
2405 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
2407 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2432 struct rockchip_pinctrl *info = bank->drvdata;
2434 *regmap = info->regmap_base;
2436 if (bank->bank_num == 0 && pin_num < 12)
2438 else if (bank->bank_num == 0)
2439 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
2440 else if (bank->bank_num == 1)
2442 else if (bank->bank_num == 2)
2444 else if (bank->bank_num == 3)
2446 else if (bank->bank_num == 4 && pin_num < 16)
2448 else if (bank->bank_num == 4 && pin_num < 24)
2449 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
2450 else if (bank->bank_num == 4)
2451 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
2453 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2574 struct rockchip_pinctrl *info = bank->drvdata;
2575 u8 bank_num = bank->bank_num;
2579 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
2582 *regmap = info->regmap_base;
2589 return -EINVAL;
2599 struct rockchip_pinctrl *info = bank->drvdata;
2600 u8 bank_num = bank->bank_num;
2604 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
2607 *regmap = info->regmap_base;
2614 return -EINVAL;
2625 struct rockchip_pinctrl *info = bank->drvdata;
2626 u8 bank_num = bank->bank_num;
2630 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
2633 *regmap = info->regmap_base;
2640 return -EINVAL;
2644 { 2, 4, 8, 12, -1, -1, -1, -1 },
2645 { 3, 6, 9, 12, -1, -1, -1, -1 },
2646 { 5, 10, 15, 20, -1, -1, -1, -1 },
2654 struct rockchip_pinctrl *info = bank->drvdata;
2655 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2656 struct device *dev = info->dev;
2661 int drv_type = bank->drv[pin_num / 8].drv_type;
2663 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2677 * drive-strength offset is special, as it is
2701 bit -= 16;
2706 return -EINVAL;
2717 return -EINVAL;
2725 data &= (1 << rmask_bits) - 1;
2733 struct rockchip_pinctrl *info = bank->drvdata;
2734 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2735 struct device *dev = info->dev;
2740 int drv_type = bank->drv[pin_num / 8].drv_type;
2742 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2743 bank->bank_num, pin_num, strength);
2745 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2748 if (ctrl->type == RK3588) {
2752 } else if (ctrl->type == RK3528 ||
2753 ctrl->type == RK3562 ||
2754 ctrl->type == RK3568) {
2756 ret = (1 << (strength + 1)) - 1;
2758 } else if (ctrl->type == RK3576) {
2764 if (ctrl->type == RV1126) {
2770 ret = -EINVAL;
2796 * drive-strength offset is special, as it is spread
2818 bit -= 16;
2823 return -EINVAL;
2833 return -EINVAL;
2838 data = ((1 << rmask_bits) - 1) << (bit + 16);
2864 struct rockchip_pinctrl *info = bank->drvdata;
2865 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2866 struct device *dev = info->dev;
2873 if (ctrl->type == RK3066B)
2876 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2884 switch (ctrl->type) {
2890 case PX30:
2903 pull_type = bank->pull_type[pin_num / 8];
2905 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2907 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2910 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2918 return -EINVAL;
2925 struct rockchip_pinctrl *info = bank->drvdata;
2926 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2927 struct device *dev = info->dev;
2933 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2936 if (ctrl->type == RK3066B)
2937 return pull ? -EINVAL : 0;
2939 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2943 switch (ctrl->type) {
2951 case PX30:
2965 pull_type = bank->pull_type[pin_num / 8];
2966 ret = -EINVAL;
2975 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2978 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2989 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2997 return -EINVAL;
3013 struct rockchip_pinctrl *info = bank->drvdata;
3015 *regmap = info->regmap_base;
3018 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
3036 struct rockchip_pinctrl *info = bank->drvdata;
3038 if (bank->bank_num == 0) {
3039 *regmap = info->regmap_pmu;
3042 *regmap = info->regmap_base;
3044 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
3056 struct rockchip_pinctrl *info = bank->drvdata;
3057 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3063 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3072 switch (ctrl->type) {
3075 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
3086 struct rockchip_pinctrl *info = bank->drvdata;
3087 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3088 struct device *dev = info->dev;
3094 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
3095 bank->bank_num, pin_num, enable);
3097 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3102 switch (ctrl->type) {
3105 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
3126 return info->nfunctions;
3134 return info->functions[selector].name;
3143 *groups = info->functions[selector].groups;
3144 *num_groups = info->functions[selector].ngroups;
3153 const unsigned int *pins = info->groups[group].pins;
3154 const struct rockchip_pin_config *data = info->groups[group].data;
3155 struct device *dev = info->dev;
3160 info->functions[selector].name, info->groups[group].name);
3166 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
3168 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
3176 for (cnt--; cnt >= 0; cnt--) {
3178 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
3196 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
3214 switch (ctrl->type) {
3221 case PX30:
3248 return -ENOMEM;
3250 cfg->pin = pin;
3251 cfg->param = param;
3252 cfg->arg = arg;
3254 list_add_tail(&cfg->head, &bank->deferred_pins);
3265 struct gpio_chip *gpio = &bank->gpio_chip;
3278 * The lock makes sure that either gpio-probe has completed
3281 mutex_lock(&bank->deferred_lock);
3282 if (!gpio || !gpio->direction_output) {
3283 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
3285 mutex_unlock(&bank->deferred_lock);
3291 mutex_unlock(&bank->deferred_lock);
3296 rc = rockchip_set_pull(bank, pin - bank->pin_base,
3305 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
3306 return -ENOTSUPP;
3309 return -EINVAL;
3311 rc = rockchip_set_pull(bank, pin - bank->pin_base,
3317 rc = rockchip_set_mux(bank, pin - bank->pin_base,
3320 return -EINVAL;
3322 rc = gpio->direction_output(gpio, pin - bank->pin_base,
3328 rc = rockchip_set_mux(bank, pin - bank->pin_base,
3331 return -EINVAL;
3333 rc = gpio->direction_input(gpio, pin - bank->pin_base);
3338 /* rk3288 is the first with per-pin drive-strength */
3339 if (!info->ctrl->drv_calc_reg)
3340 return -ENOTSUPP;
3343 pin - bank->pin_base, arg);
3348 if (!info->ctrl->schmitt_calc_reg)
3349 return -ENOTSUPP;
3352 pin - bank->pin_base, arg);
3357 return -ENOTSUPP;
3371 struct gpio_chip *gpio = &bank->gpio_chip;
3378 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
3379 return -EINVAL;
3387 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
3388 return -ENOTSUPP;
3390 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
3391 return -EINVAL;
3396 rc = rockchip_get_mux(bank, pin - bank->pin_base);
3398 return -EINVAL;
3400 if (!gpio || !gpio->get) {
3405 rc = gpio->get(gpio, pin - bank->pin_base);
3412 /* rk3288 is the first with per-pin drive-strength */
3413 if (!info->ctrl->drv_calc_reg)
3414 return -ENOTSUPP;
3416 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
3423 if (!info->ctrl->schmitt_calc_reg)
3424 return -ENOTSUPP;
3426 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
3433 return -ENOTSUPP;
3449 { .compatible = "rockchip,gpio-bank" },
3450 { .compatible = "rockchip,rk3188-gpio-bank0" },
3463 info->nfunctions++;
3464 info->ngroups += of_get_child_count(child);
3473 struct device *dev = info->dev;
3484 grp->name = np->name;
3494 return dev_err_probe(dev, -EINVAL,
3498 grp->npins = size / 4;
3500 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
3501 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
3502 if (!grp->pins || !grp->data)
3503 return -ENOMEM;
3514 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
3515 grp->data[j].func = be32_to_cpu(*list++);
3519 return -EINVAL;
3523 &grp->data[j].configs, &grp->data[j].nconfigs);
3536 struct device *dev = info->dev;
3545 func = &info->functions[index];
3548 func->name = np->name;
3549 func->ngroups = of_get_child_count(np);
3550 if (func->ngroups <= 0)
3553 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
3554 if (!func->groups)
3555 return -ENOMEM;
3558 func->groups[i] = child->name;
3559 grp = &info->groups[grp_index++];
3571 struct device *dev = &pdev->dev;
3572 struct device_node *np = dev->of_node;
3578 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
3579 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3581 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
3582 if (!info->functions)
3583 return -ENOMEM;
3585 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
3586 if (!info->groups)
3587 return -ENOMEM;
3608 struct pinctrl_desc *ctrldesc = &info->pctl;
3611 struct device *dev = &pdev->dev;
3616 ctrldesc->name = "rockchip-pinctrl";
3617 ctrldesc->owner = THIS_MODULE;
3618 ctrldesc->pctlops = &rockchip_pctrl_ops;
3619 ctrldesc->pmxops = &rockchip_pmx_ops;
3620 ctrldesc->confops = &rockchip_pinconf_ops;
3622 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3624 return -ENOMEM;
3626 ctrldesc->pins = pindesc;
3627 ctrldesc->npins = info->ctrl->nr_pins;
3630 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
3631 pin_bank = &info->ctrl->pin_banks[bank];
3633 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
3637 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3638 pdesc->number = k;
3639 pdesc->name = pin_names[pin];
3643 INIT_LIST_HEAD(&pin_bank->deferred_pins);
3644 mutex_init(&pin_bank->deferred_lock);
3651 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
3652 if (IS_ERR(info->pctl_dev))
3653 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
3665 struct device *dev = &pdev->dev;
3666 struct device_node *node = dev->of_node;
3673 ctrl = (struct rockchip_pin_ctrl *)match->data;
3675 grf_offs = ctrl->grf_mux_offset;
3676 pmu_offs = ctrl->pmu_mux_offset;
3677 drv_pmu_offs = ctrl->pmu_drv_offset;
3678 drv_grf_offs = ctrl->grf_drv_offset;
3679 bank = ctrl->pin_banks;
3680 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3683 raw_spin_lock_init(&bank->slock);
3684 bank->drvdata = d;
3685 bank->pin_base = ctrl->nr_pins;
3686 ctrl->nr_pins += bank->nr_pins;
3690 struct rockchip_iomux *iom = &bank->iomux[j];
3691 struct rockchip_drv *drv = &bank->drv[j];
3694 if (bank_pins >= bank->nr_pins)
3698 if (iom->offset >= 0) {
3699 if ((iom->type & IOMUX_SOURCE_PMU) ||
3700 (iom->type & IOMUX_L_SOURCE_PMU))
3701 pmu_offs = iom->offset;
3703 grf_offs = iom->offset;
3705 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
3706 (iom->type & IOMUX_L_SOURCE_PMU)) ?
3711 if (drv->offset >= 0) {
3712 if (iom->type & IOMUX_SOURCE_PMU)
3713 drv_pmu_offs = drv->offset;
3715 drv_grf_offs = drv->offset;
3717 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3722 i, j, iom->offset, drv->offset);
3728 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3731 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3738 * 3bit drive-strenth'es are spread over two registers.
3740 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3741 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3746 if (iom->type & IOMUX_SOURCE_PMU)
3754 /* calculate the per-bank recalced_mask */
3755 for (j = 0; j < ctrl->niomux_recalced; j++) {
3758 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3759 pin = ctrl->iomux_recalced[j].pin;
3760 bank->recalced_mask |= BIT(pin);
3764 /* calculate the per-bank route_mask */
3765 for (j = 0; j < ctrl->niomux_routes; j++) {
3768 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3769 pin = ctrl->iomux_routes[j].pin;
3770 bank->route_mask |= BIT(pin);
3786 int ret = pinctrl_force_sleep(info->pctl_dev);
3795 if (info->ctrl->type == RK3288) {
3796 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3799 pinctrl_force_default(info->pctl_dev);
3812 if (info->ctrl->type == RK3288) {
3813 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3820 return pinctrl_force_default(info->pctl_dev);
3829 struct device *dev = &pdev->dev;
3830 struct device_node *np = dev->of_node, *node;
3836 if (!dev->of_node)
3837 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
3841 return -ENOMEM;
3843 info->dev = dev;
3847 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
3848 info->ctrl = ctrl;
3852 info->regmap_base = syscon_node_to_regmap(node);
3854 if (IS_ERR(info->regmap_base))
3855 return PTR_ERR(info->regmap_base);
3861 rockchip_regmap_config.max_register = resource_size(res) - 4;
3863 info->regmap_base =
3866 /* to check for the old dt-bindings */
3867 info->reg_size = resource_size(res);
3870 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3875 rockchip_regmap_config.max_register = resource_size(res) - 4;
3876 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3877 info->regmap_pull =
3882 /* try to find the optional reference to the pmu syscon */
3883 node = of_parse_phandle(np, "rockchip,pmu", 0);
3885 info->regmap_pmu = syscon_node_to_regmap(node);
3887 if (IS_ERR(info->regmap_pmu))
3888 return PTR_ERR(info->regmap_pmu);
3897 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
3911 of_platform_depopulate(&pdev->dev);
3913 for (i = 0; i < info->ctrl->nr_banks; i++) {
3914 bank = &info->ctrl->pin_banks[i];
3916 mutex_lock(&bank->deferred_lock);
3917 while (!list_empty(&bank->deferred_pins)) {
3918 cfg = list_first_entry(&bank->deferred_pins,
3920 list_del(&cfg->head);
3923 mutex_unlock(&bank->deferred_lock);
3953 .label = "PX30-GPIO",
3954 .type = PX30,
3977 .label = "RV1108-GPIO",
4017 .label = "RV1126-GPIO",
4040 .label = "RK2928-GPIO",
4055 .label = "RK3036-GPIO",
4073 .label = "RK3066a-GPIO",
4089 .label = "RK3066b-GPIO",
4104 .label = "RK3128-GPIO",
4124 .label = "RK3188-GPIO",
4142 .label = "RK3228-GPIO",
4186 .label = "RK3288-GPIO",
4222 .label = "RK3308-GPIO",
4251 .label = "RK3328-GPIO",
4277 .label = "RK3368-GPIO",
4297 -1,
4298 -1,
4341 .label = "RK3399-GPIO",
4389 .label = "RK3528-GPIO",
4432 .label = "RK3562-GPIO",
4465 .label = "RK3568-GPIO",
4502 .label = "RK3576-GPIO",
4525 .label = "RK3588-GPIO",
4533 { .compatible = "rockchip,px30-pinctrl",
4535 { .compatible = "rockchip,rv1108-pinctrl",
4537 { .compatible = "rockchip,rv1126-pinctrl",
4539 { .compatible = "rockchip,rk2928-pinctrl",
4541 { .compatible = "rockchip,rk3036-pinctrl",
4543 { .compatible = "rockchip,rk3066a-pinctrl",
4545 { .compatible = "rockchip,rk3066b-pinctrl",
4547 { .compatible = "rockchip,rk3128-pinctrl",
4549 { .compatible = "rockchip,rk3188-pinctrl",
4551 { .compatible = "rockchip,rk3228-pinctrl",
4553 { .compatible = "rockchip,rk3288-pinctrl",
4555 { .compatible = "rockchip,rk3308-pinctrl",
4557 { .compatible = "rockchip,rk3328-pinctrl",
4559 { .compatible = "rockchip,rk3368-pinctrl",
4561 { .compatible = "rockchip,rk3399-pinctrl",
4563 { .compatible = "rockchip,rk3528-pinctrl",
4565 { .compatible = "rockchip,rk3562-pinctrl",
4567 { .compatible = "rockchip,rk3568-pinctrl",
4569 { .compatible = "rockchip,rk3576-pinctrl",
4571 { .compatible = "rockchip,rk3588-pinctrl",
4580 .name = "rockchip-pinctrl",
4600 MODULE_ALIAS("platform:pinctrl-rockchip");