Lines Matching +full:mux +full:- +full:gpio2
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
124 { .drv_type = drv0, .offset = -1 }, \
125 { .drv_type = drv1, .offset = -1 }, \
126 { .drv_type = drv2, .offset = -1 }, \
127 { .drv_type = drv3, .offset = -1 }, \
137 { .offset = -1 }, \
138 { .offset = -1 }, \
139 { .offset = -1 }, \
140 { .offset = -1 }, \
143 { .drv_type = type0, .offset = -1 }, \
144 { .drv_type = type1, .offset = -1 }, \
145 { .drv_type = type2, .offset = -1 }, \
146 { .drv_type = type3, .offset = -1 }, \
158 { .type = iom0, .offset = -1 }, \
159 { .type = iom1, .offset = -1 }, \
160 { .type = iom2, .offset = -1 }, \
161 { .type = iom3, .offset = -1 }, \
177 { .offset = -1 }, \
178 { .offset = -1 }, \
179 { .offset = -1 }, \
180 { .offset = -1 }, \
183 { .drv_type = drv0, .offset = -1 }, \
184 { .drv_type = drv1, .offset = -1 }, \
185 { .drv_type = drv2, .offset = -1 }, \
186 { .drv_type = drv3, .offset = -1 }, \
218 { .type = iom0, .offset = -1 }, \
219 { .type = iom1, .offset = -1 }, \
220 { .type = iom2, .offset = -1 }, \
221 { .type = iom3, .offset = -1 }, \
242 { .type = iom0, .offset = -1 }, \
243 { .type = iom1, .offset = -1 }, \
244 { .type = iom2, .offset = -1 }, \
245 { .type = iom3, .offset = -1 }, \
277 { .drv_type = drv0, .offset = -1 }, \
278 { .drv_type = drv1, .offset = -1 }, \
279 { .drv_type = drv2, .offset = -1 }, \
280 { .drv_type = drv3, .offset = -1 }, \
322 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
323 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
324 return &info->groups[i]; in pinctrl_name_to_group()
337 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
339 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
349 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
352 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
353 if (b->bank_num == num) in bank_num_to_bank()
357 return ERR_PTR(-EINVAL); in bank_num_to_bank()
368 return info->ngroups; in rockchip_get_groups_count()
376 return info->groups[selector].name; in rockchip_get_group_name()
385 if (selector >= info->ngroups) in rockchip_get_group_pins()
386 return -EINVAL; in rockchip_get_group_pins()
388 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
389 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
400 struct device *dev = info->dev; in rockchip_dt_node_to_map()
410 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
413 return -EINVAL; in rockchip_dt_node_to_map()
416 map_num += grp->npins; in rockchip_dt_node_to_map()
420 return -ENOMEM; in rockchip_dt_node_to_map()
425 /* create mux map */ in rockchip_dt_node_to_map()
429 return -EINVAL; in rockchip_dt_node_to_map()
432 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
433 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
438 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
441 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
442 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
443 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
447 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
778 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
779 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux()
783 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
784 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
785 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
786 data->pin == pin) in rockchip_get_recalced_mux()
790 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
793 *reg = data->reg; in rockchip_get_recalced_mux()
794 *mask = data->mask; in rockchip_get_recalced_mux()
795 *bit = data->bit; in rockchip_get_recalced_mux()
799 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
800 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
801 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
802 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
803 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
804 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
805 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
806 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
807 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
808 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
809 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
810 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
811 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
812 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
813 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
814 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
815 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
816 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
817 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
818 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
819 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
820 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
821 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
822 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
823 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
824 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
825 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
826 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
827 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
828 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
829 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
830 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
831 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
832 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
833 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
834 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
835 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
836 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
837 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
838 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
839 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
840 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
841 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
842 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
843 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
844 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
845 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
846 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
947 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
948 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
949 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
950 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
951 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
952 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
953 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
957 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
958 …UTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
962 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
963 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
964 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
965 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
966 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
967 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
968 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
969 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
970 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
971 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
972 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
973 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
974 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
975 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
976 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
977 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
978 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
979 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
993 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
994 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
995 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
996 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
997 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
998 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
999 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
1000 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
1006 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
1007 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
1027 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
1028 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
1029 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
1030 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
1031 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
1032 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
1033 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
1034 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
1035 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
1036 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
1037 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
1038 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
1039 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
1040 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
1041 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
1042 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
1043 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
1044 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
1045 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
1046 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
1047 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
1048 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
1049 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
1050 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
1051 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1052 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1053 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1054 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1055 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1056 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1057 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1058 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1059 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1060 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1061 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1062 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1063 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1064 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1065 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1066 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1067 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1068 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1069 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1070 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1071 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1072 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1073 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1074 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1075 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1076 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1077 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1078 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1079 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1080 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1081 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1082 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1083 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1084 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1085 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1086 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1087 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1088 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1089 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1090 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1091 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1092 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1093 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1094 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1095 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1096 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1097 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1098 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1099 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1100 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1101 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1102 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1103 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1104 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1105 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1106 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1107 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1108 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1109 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1110 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1111 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1112 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1113 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1114 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1115 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1116 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1117 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1118 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1119 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1123 int mux, u32 *loc, u32 *reg, u32 *value) in rockchip_get_mux_route() argument
1125 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1126 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route()
1130 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1131 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1132 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1133 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1137 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1140 *loc = data->route_location; in rockchip_get_mux_route()
1141 *reg = data->route_offset; in rockchip_get_mux_route()
1142 *value = data->route_val; in rockchip_get_mux_route()
1149 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1150 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux()
1158 return -EINVAL; in rockchip_get_mux()
1160 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1161 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
1162 return -EINVAL; in rockchip_get_mux()
1165 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1168 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1169 regmap = info->regmap_pmu; in rockchip_get_mux()
1170 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_get_mux()
1171 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
1173 regmap = info->regmap_base; in rockchip_get_mux()
1175 if (ctrl->type == RK3506) { in rockchip_get_mux()
1176 if (bank->bank_num == 1) in rockchip_get_mux()
1177 regmap = info->regmap_ioc1; in rockchip_get_mux()
1178 else if (bank->bank_num == 4) in rockchip_get_mux()
1182 /* get basic quadrupel of mux registers and the correct reg inside */ in rockchip_get_mux()
1183 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1184 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1200 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1203 if (ctrl->type == RK3576) { in rockchip_get_mux()
1204 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) in rockchip_get_mux()
1208 if (ctrl->type == RK3588) { in rockchip_get_mux()
1209 if (bank->bank_num == 0) { in rockchip_get_mux()
1213 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_get_mux()
1222 regmap = info->regmap_base; in rockchip_get_mux()
1224 } else if (bank->bank_num > 0) { in rockchip_get_mux()
1237 int pin, int mux) in rockchip_verify_mux() argument
1239 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1240 struct device *dev = info->dev; in rockchip_verify_mux()
1244 return -EINVAL; in rockchip_verify_mux()
1246 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1248 return -EINVAL; in rockchip_verify_mux()
1251 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1252 if (mux != RK_FUNC_GPIO) { in rockchip_verify_mux()
1253 dev_err(dev, "pin %d only supports a gpio mux\n", pin); in rockchip_verify_mux()
1254 return -ENOTSUPP; in rockchip_verify_mux()
1262 * Set a new mux function for a pin.
1272 * @mux: new mux function to set
1274 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rockchip_set_mux() argument
1276 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1277 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_mux()
1278 struct device *dev = info->dev; in rockchip_set_mux()
1285 ret = rockchip_verify_mux(bank, pin, mux); in rockchip_set_mux()
1289 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1292 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rockchip_set_mux()
1294 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1295 regmap = info->regmap_pmu; in rockchip_set_mux()
1296 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_set_mux()
1297 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
1299 regmap = info->regmap_base; in rockchip_set_mux()
1301 if (ctrl->type == RK3506) { in rockchip_set_mux()
1302 if (bank->bank_num == 1) in rockchip_set_mux()
1303 regmap = info->regmap_ioc1; in rockchip_set_mux()
1304 else if (bank->bank_num == 4) in rockchip_set_mux()
1308 /* get basic quadrupel of mux registers and the correct reg inside */ in rockchip_set_mux()
1309 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1310 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1326 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1329 if (ctrl->type == RK3576) { in rockchip_set_mux()
1330 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) in rockchip_set_mux()
1334 if (ctrl->type == RK3588) { in rockchip_set_mux()
1335 if (bank->bank_num == 0) { in rockchip_set_mux()
1337 if (mux < 8) { in rockchip_set_mux()
1338 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1341 data |= (mux & mask) << bit; in rockchip_set_mux()
1346 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1355 data |= mux << bit; in rockchip_set_mux()
1356 regmap = info->regmap_base; in rockchip_set_mux()
1362 data |= (mux & mask) << bit; in rockchip_set_mux()
1366 } else if (bank->bank_num > 0) { in rockchip_set_mux()
1371 if (mux > mask) in rockchip_set_mux()
1372 return -EINVAL; in rockchip_set_mux()
1374 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1375 if (rockchip_get_mux_route(bank, pin, mux, &route_location, in rockchip_set_mux()
1382 route_regmap = info->regmap_pmu; in rockchip_set_mux()
1385 route_regmap = info->regmap_base; in rockchip_set_mux()
1397 data |= (mux & mask) << bit; in rockchip_set_mux()
1413 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1416 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1417 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
1420 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1424 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1425 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1445 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1448 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1449 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1452 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1456 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1457 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1478 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1481 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1482 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1486 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1489 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1508 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1511 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1512 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1516 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1518 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1519 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1539 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1542 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1543 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1546 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1550 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1551 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1572 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1575 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1576 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1580 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1583 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1602 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_pull_reg_and_bit()
1605 if (bank->bank_num == 0) { in rv1126_calc_pull_reg_and_bit()
1607 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1609 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); in rv1126_calc_pull_reg_and_bit()
1614 *regmap = info->regmap_pmu; in rv1126_calc_pull_reg_and_bit()
1618 *regmap = info->regmap_base; in rv1126_calc_pull_reg_and_bit()
1619 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; in rv1126_calc_pull_reg_and_bit()
1639 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_drv_reg_and_bit()
1642 if (bank->bank_num == 0) { in rv1126_calc_drv_reg_and_bit()
1644 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1646 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); in rv1126_calc_drv_reg_and_bit()
1647 *reg -= 0x4; in rv1126_calc_drv_reg_and_bit()
1652 *regmap = info->regmap_pmu; in rv1126_calc_drv_reg_and_bit()
1655 *regmap = info->regmap_base; in rv1126_calc_drv_reg_and_bit()
1657 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; in rv1126_calc_drv_reg_and_bit()
1678 struct rockchip_pinctrl *info = bank->drvdata; in rv1126_calc_schmitt_reg_and_bit()
1681 if (bank->bank_num == 0) { in rv1126_calc_schmitt_reg_and_bit()
1683 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1685 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); in rv1126_calc_schmitt_reg_and_bit()
1689 *regmap = info->regmap_pmu; in rv1126_calc_schmitt_reg_and_bit()
1693 *regmap = info->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
1696 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; in rv1126_calc_schmitt_reg_and_bit()
1712 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1714 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1717 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1732 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1734 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1736 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1750 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1752 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1754 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1772 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1775 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1776 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1777 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1778 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1783 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1784 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1785 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1788 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1789 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1797 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1809 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1812 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1813 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1820 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1824 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1825 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1845 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1848 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1849 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1856 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1860 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1861 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1877 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1879 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1881 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1896 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1898 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1900 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1915 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1917 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1919 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1934 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1936 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1938 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1954 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1957 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1958 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
1965 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
1969 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1970 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
1987 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
1990 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1991 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
1998 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
2002 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
2003 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
2021 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
2024 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
2025 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
2028 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2034 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
2038 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
2039 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2053 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
2057 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
2058 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
2060 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
2062 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
2063 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
2064 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
2085 struct rockchip_pinctrl *info = bank->drvdata; in rk3506_calc_drv_reg_and_bit()
2088 switch (bank->bank_num) { in rk3506_calc_drv_reg_and_bit()
2090 *regmap = info->regmap_pmu; in rk3506_calc_drv_reg_and_bit()
2092 ret = -EINVAL; in rk3506_calc_drv_reg_and_bit()
2104 *regmap = info->regmap_ioc1; in rk3506_calc_drv_reg_and_bit()
2108 ret = -EINVAL; in rk3506_calc_drv_reg_and_bit()
2112 *regmap = info->regmap_base; in rk3506_calc_drv_reg_and_bit()
2116 ret = -EINVAL; in rk3506_calc_drv_reg_and_bit()
2120 *regmap = info->regmap_base; in rk3506_calc_drv_reg_and_bit()
2124 ret = -EINVAL; in rk3506_calc_drv_reg_and_bit()
2128 *regmap = info->regmap_base; in rk3506_calc_drv_reg_and_bit()
2130 ret = -EINVAL; in rk3506_calc_drv_reg_and_bit()
2140 ret = -EINVAL; in rk3506_calc_drv_reg_and_bit()
2145 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); in rk3506_calc_drv_reg_and_bit()
2170 struct rockchip_pinctrl *info = bank->drvdata; in rk3506_calc_pull_reg_and_bit()
2173 switch (bank->bank_num) { in rk3506_calc_pull_reg_and_bit()
2175 *regmap = info->regmap_pmu; in rk3506_calc_pull_reg_and_bit()
2177 ret = -EINVAL; in rk3506_calc_pull_reg_and_bit()
2189 *regmap = info->regmap_ioc1; in rk3506_calc_pull_reg_and_bit()
2193 ret = -EINVAL; in rk3506_calc_pull_reg_and_bit()
2197 *regmap = info->regmap_base; in rk3506_calc_pull_reg_and_bit()
2201 ret = -EINVAL; in rk3506_calc_pull_reg_and_bit()
2205 *regmap = info->regmap_base; in rk3506_calc_pull_reg_and_bit()
2209 ret = -EINVAL; in rk3506_calc_pull_reg_and_bit()
2213 *regmap = info->regmap_base; in rk3506_calc_pull_reg_and_bit()
2215 ret = -EINVAL; in rk3506_calc_pull_reg_and_bit()
2225 ret = -EINVAL; in rk3506_calc_pull_reg_and_bit()
2230 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); in rk3506_calc_pull_reg_and_bit()
2256 struct rockchip_pinctrl *info = bank->drvdata; in rk3506_calc_schmitt_reg_and_bit()
2259 switch (bank->bank_num) { in rk3506_calc_schmitt_reg_and_bit()
2261 *regmap = info->regmap_pmu; in rk3506_calc_schmitt_reg_and_bit()
2263 ret = -EINVAL; in rk3506_calc_schmitt_reg_and_bit()
2275 *regmap = info->regmap_ioc1; in rk3506_calc_schmitt_reg_and_bit()
2279 ret = -EINVAL; in rk3506_calc_schmitt_reg_and_bit()
2283 *regmap = info->regmap_base; in rk3506_calc_schmitt_reg_and_bit()
2287 ret = -EINVAL; in rk3506_calc_schmitt_reg_and_bit()
2291 *regmap = info->regmap_base; in rk3506_calc_schmitt_reg_and_bit()
2295 ret = -EINVAL; in rk3506_calc_schmitt_reg_and_bit()
2299 *regmap = info->regmap_base; in rk3506_calc_schmitt_reg_and_bit()
2301 ret = -EINVAL; in rk3506_calc_schmitt_reg_and_bit()
2311 ret = -EINVAL; in rk3506_calc_schmitt_reg_and_bit()
2316 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); in rk3506_calc_schmitt_reg_and_bit()
2340 struct rockchip_pinctrl *info = bank->drvdata; in rk3528_calc_drv_reg_and_bit()
2342 *regmap = info->regmap_base; in rk3528_calc_drv_reg_and_bit()
2344 if (bank->bank_num == 0) in rk3528_calc_drv_reg_and_bit()
2346 else if (bank->bank_num == 1) in rk3528_calc_drv_reg_and_bit()
2348 else if (bank->bank_num == 2) in rk3528_calc_drv_reg_and_bit()
2350 else if (bank->bank_num == 3) in rk3528_calc_drv_reg_and_bit()
2352 else if (bank->bank_num == 4) in rk3528_calc_drv_reg_and_bit()
2355 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3528_calc_drv_reg_and_bit()
2376 struct rockchip_pinctrl *info = bank->drvdata; in rk3528_calc_pull_reg_and_bit()
2378 *regmap = info->regmap_base; in rk3528_calc_pull_reg_and_bit()
2380 if (bank->bank_num == 0) in rk3528_calc_pull_reg_and_bit()
2382 else if (bank->bank_num == 1) in rk3528_calc_pull_reg_and_bit()
2384 else if (bank->bank_num == 2) in rk3528_calc_pull_reg_and_bit()
2386 else if (bank->bank_num == 3) in rk3528_calc_pull_reg_and_bit()
2388 else if (bank->bank_num == 4) in rk3528_calc_pull_reg_and_bit()
2391 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3528_calc_pull_reg_and_bit()
2413 struct rockchip_pinctrl *info = bank->drvdata; in rk3528_calc_schmitt_reg_and_bit()
2415 *regmap = info->regmap_base; in rk3528_calc_schmitt_reg_and_bit()
2417 if (bank->bank_num == 0) in rk3528_calc_schmitt_reg_and_bit()
2419 else if (bank->bank_num == 1) in rk3528_calc_schmitt_reg_and_bit()
2421 else if (bank->bank_num == 2) in rk3528_calc_schmitt_reg_and_bit()
2423 else if (bank->bank_num == 3) in rk3528_calc_schmitt_reg_and_bit()
2425 else if (bank->bank_num == 4) in rk3528_calc_schmitt_reg_and_bit()
2428 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3528_calc_schmitt_reg_and_bit()
2449 struct rockchip_pinctrl *info = bank->drvdata; in rk3562_calc_drv_reg_and_bit()
2451 *regmap = info->regmap_base; in rk3562_calc_drv_reg_and_bit()
2452 switch (bank->bank_num) { in rk3562_calc_drv_reg_and_bit()
2474 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3562_calc_drv_reg_and_bit()
2497 struct rockchip_pinctrl *info = bank->drvdata; in rk3562_calc_pull_reg_and_bit()
2499 *regmap = info->regmap_base; in rk3562_calc_pull_reg_and_bit()
2500 switch (bank->bank_num) { in rk3562_calc_pull_reg_and_bit()
2522 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3562_calc_pull_reg_and_bit()
2546 struct rockchip_pinctrl *info = bank->drvdata; in rk3562_calc_schmitt_reg_and_bit()
2548 *regmap = info->regmap_base; in rk3562_calc_schmitt_reg_and_bit()
2549 switch (bank->bank_num) { in rk3562_calc_schmitt_reg_and_bit()
2571 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3562_calc_schmitt_reg_and_bit()
2592 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_pull_reg_and_bit()
2594 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
2595 *regmap = info->regmap_pmu; in rk3568_calc_pull_reg_and_bit()
2597 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
2603 *regmap = info->regmap_base; in rk3568_calc_pull_reg_and_bit()
2605 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
2625 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_drv_reg_and_bit()
2628 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
2629 *regmap = info->regmap_pmu; in rk3568_calc_drv_reg_and_bit()
2636 *regmap = info->regmap_base; in rk3568_calc_drv_reg_and_bit()
2638 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; in rk3568_calc_drv_reg_and_bit()
2663 struct rockchip_pinctrl *info = bank->drvdata; in rk3576_calc_drv_reg_and_bit()
2665 *regmap = info->regmap_base; in rk3576_calc_drv_reg_and_bit()
2667 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_drv_reg_and_bit()
2669 else if (bank->bank_num == 0) in rk3576_calc_drv_reg_and_bit()
2670 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; in rk3576_calc_drv_reg_and_bit()
2671 else if (bank->bank_num == 1) in rk3576_calc_drv_reg_and_bit()
2673 else if (bank->bank_num == 2) in rk3576_calc_drv_reg_and_bit()
2675 else if (bank->bank_num == 3) in rk3576_calc_drv_reg_and_bit()
2677 else if (bank->bank_num == 4 && pin_num < 16) in rk3576_calc_drv_reg_and_bit()
2679 else if (bank->bank_num == 4 && pin_num < 24) in rk3576_calc_drv_reg_and_bit()
2680 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; in rk3576_calc_drv_reg_and_bit()
2681 else if (bank->bank_num == 4) in rk3576_calc_drv_reg_and_bit()
2682 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; in rk3576_calc_drv_reg_and_bit()
2684 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3576_calc_drv_reg_and_bit()
2708 struct rockchip_pinctrl *info = bank->drvdata; in rk3576_calc_pull_reg_and_bit()
2710 *regmap = info->regmap_base; in rk3576_calc_pull_reg_and_bit()
2712 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_pull_reg_and_bit()
2714 else if (bank->bank_num == 0) in rk3576_calc_pull_reg_and_bit()
2715 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; in rk3576_calc_pull_reg_and_bit()
2716 else if (bank->bank_num == 1) in rk3576_calc_pull_reg_and_bit()
2718 else if (bank->bank_num == 2) in rk3576_calc_pull_reg_and_bit()
2720 else if (bank->bank_num == 3) in rk3576_calc_pull_reg_and_bit()
2722 else if (bank->bank_num == 4 && pin_num < 16) in rk3576_calc_pull_reg_and_bit()
2724 else if (bank->bank_num == 4 && pin_num < 24) in rk3576_calc_pull_reg_and_bit()
2725 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; in rk3576_calc_pull_reg_and_bit()
2726 else if (bank->bank_num == 4) in rk3576_calc_pull_reg_and_bit()
2727 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; in rk3576_calc_pull_reg_and_bit()
2729 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3576_calc_pull_reg_and_bit()
2754 struct rockchip_pinctrl *info = bank->drvdata; in rk3576_calc_schmitt_reg_and_bit()
2756 *regmap = info->regmap_base; in rk3576_calc_schmitt_reg_and_bit()
2758 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_schmitt_reg_and_bit()
2760 else if (bank->bank_num == 0) in rk3576_calc_schmitt_reg_and_bit()
2761 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; in rk3576_calc_schmitt_reg_and_bit()
2762 else if (bank->bank_num == 1) in rk3576_calc_schmitt_reg_and_bit()
2764 else if (bank->bank_num == 2) in rk3576_calc_schmitt_reg_and_bit()
2766 else if (bank->bank_num == 3) in rk3576_calc_schmitt_reg_and_bit()
2768 else if (bank->bank_num == 4 && pin_num < 16) in rk3576_calc_schmitt_reg_and_bit()
2770 else if (bank->bank_num == 4 && pin_num < 24) in rk3576_calc_schmitt_reg_and_bit()
2771 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; in rk3576_calc_schmitt_reg_and_bit()
2772 else if (bank->bank_num == 4) in rk3576_calc_schmitt_reg_and_bit()
2773 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; in rk3576_calc_schmitt_reg_and_bit()
2775 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); in rk3576_calc_schmitt_reg_and_bit()
2896 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_pull_reg_and_bit()
2897 u8 bank_num = bank->bank_num; in rk3588_calc_pull_reg_and_bit()
2901 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { in rk3588_calc_pull_reg_and_bit()
2904 *regmap = info->regmap_base; in rk3588_calc_pull_reg_and_bit()
2911 return -EINVAL; in rk3588_calc_pull_reg_and_bit()
2921 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_drv_reg_and_bit()
2922 u8 bank_num = bank->bank_num; in rk3588_calc_drv_reg_and_bit()
2926 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { in rk3588_calc_drv_reg_and_bit()
2929 *regmap = info->regmap_base; in rk3588_calc_drv_reg_and_bit()
2936 return -EINVAL; in rk3588_calc_drv_reg_and_bit()
2947 struct rockchip_pinctrl *info = bank->drvdata; in rk3588_calc_schmitt_reg_and_bit()
2948 u8 bank_num = bank->bank_num; in rk3588_calc_schmitt_reg_and_bit()
2952 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { in rk3588_calc_schmitt_reg_and_bit()
2955 *regmap = info->regmap_base; in rk3588_calc_schmitt_reg_and_bit()
2962 return -EINVAL; in rk3588_calc_schmitt_reg_and_bit()
2966 { 2, 4, 8, 12, -1, -1, -1, -1 },
2967 { 3, 6, 9, 12, -1, -1, -1, -1 },
2968 { 5, 10, 15, 20, -1, -1, -1, -1 },
2976 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2977 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin()
2978 struct device *dev = info->dev; in rockchip_get_drive_perpin()
2983 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2985 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2999 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
3023 bit -= 16; in rockchip_get_drive_perpin()
3028 return -EINVAL; in rockchip_get_drive_perpin()
3039 return -EINVAL; in rockchip_get_drive_perpin()
3047 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
3055 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
3056 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin()
3057 struct device *dev = info->dev; in rockchip_set_drive_perpin()
3062 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
3064 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
3065 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
3067 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
3070 if (ctrl->type == RK3588) { in rockchip_set_drive_perpin()
3074 } else if (ctrl->type == RK3506 || in rockchip_set_drive_perpin()
3075 ctrl->type == RK3528 || in rockchip_set_drive_perpin()
3076 ctrl->type == RK3562 || in rockchip_set_drive_perpin()
3077 ctrl->type == RK3568) { in rockchip_set_drive_perpin()
3079 ret = (1 << (strength + 1)) - 1; in rockchip_set_drive_perpin()
3081 } else if (ctrl->type == RK3576) { in rockchip_set_drive_perpin()
3087 if (ctrl->type == RV1126) { in rockchip_set_drive_perpin()
3093 ret = -EINVAL; in rockchip_set_drive_perpin()
3119 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
3141 bit -= 16; in rockchip_set_drive_perpin()
3146 return -EINVAL; in rockchip_set_drive_perpin()
3166 data &= (1 << 8) - 1; in rockchip_set_drive_perpin()
3170 return ret - 1; in rockchip_set_drive_perpin()
3172 return -EINVAL; in rockchip_set_drive_perpin()
3175 return -EINVAL; in rockchip_set_drive_perpin()
3179 if (ctrl->type == RK3506) { in rockchip_set_drive_perpin()
3180 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { in rockchip_set_drive_perpin()
3186 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
3212 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
3213 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull()
3214 struct device *dev = info->dev; in rockchip_get_pull()
3221 if (ctrl->type == RK3066B) in rockchip_get_pull()
3224 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
3232 switch (ctrl->type) { in rockchip_get_pull()
3251 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
3253 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
3255 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_get_pull()
3258 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_get_pull()
3266 return -EINVAL; in rockchip_get_pull()
3273 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
3274 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull()
3275 struct device *dev = info->dev; in rockchip_set_pull()
3281 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); in rockchip_set_pull()
3284 if (ctrl->type == RK3066B) in rockchip_set_pull()
3285 return pull ? -EINVAL : 0; in rockchip_set_pull()
3287 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
3291 switch (ctrl->type) { in rockchip_set_pull()
3314 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
3315 ret = -EINVAL; in rockchip_set_pull()
3324 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_set_pull()
3327 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
3338 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
3346 return -EINVAL; in rockchip_set_pull()
3362 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
3364 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
3367 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
3385 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_schmitt_reg_and_bit()
3387 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
3388 *regmap = info->regmap_pmu; in rk3568_calc_schmitt_reg_and_bit()
3391 *regmap = info->regmap_base; in rk3568_calc_schmitt_reg_and_bit()
3393 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; in rk3568_calc_schmitt_reg_and_bit()
3405 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
3406 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt()
3412 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
3421 switch (ctrl->type) { in rockchip_get_schmitt()
3424 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); in rockchip_get_schmitt()
3429 if (ctrl->type == RK3506) in rockchip_get_schmitt()
3430 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) in rockchip_get_schmitt()
3439 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
3440 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt()
3441 struct device *dev = info->dev; in rockchip_set_schmitt()
3447 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
3448 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
3450 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
3455 switch (ctrl->type) { in rockchip_set_schmitt()
3458 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_schmitt()
3468 if (ctrl->type == RK3506) { in rockchip_set_schmitt()
3469 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { in rockchip_set_schmitt()
3487 return info->nfunctions; in rockchip_pmx_get_funcs_count()
3495 return info->functions[selector].name; in rockchip_pmx_get_func_name()
3504 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
3505 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
3514 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
3515 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
3516 struct device *dev = info->dev; in rockchip_pmx_set()
3521 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
3527 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
3529 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
3537 for (cnt--; cnt >= 0; cnt--) { in rockchip_pmx_set()
3539 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
3557 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); in rockchip_pmx_gpio_set_direction()
3575 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
3610 return -ENOMEM; in rockchip_pinconf_defer_pin()
3612 cfg->pin = pin; in rockchip_pinconf_defer_pin()
3613 cfg->param = param; in rockchip_pinconf_defer_pin()
3614 cfg->arg = arg; in rockchip_pinconf_defer_pin()
3616 list_add_tail(&cfg->head, &bank->deferred_pins); in rockchip_pinconf_defer_pin()
3627 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_set()
3640 * The lock makes sure that either gpio-probe has completed in rockchip_pinconf_set()
3643 mutex_lock(&bank->deferred_lock); in rockchip_pinconf_set()
3644 if (!gpio || !gpio->direction_output) { in rockchip_pinconf_set()
3645 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, in rockchip_pinconf_set()
3647 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
3653 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
3658 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3667 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
3668 return -ENOTSUPP; in rockchip_pinconf_set()
3671 return -EINVAL; in rockchip_pinconf_set()
3673 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3679 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3682 return -EINVAL; in rockchip_pinconf_set()
3684 rc = gpio->direction_output(gpio, pin - bank->pin_base, in rockchip_pinconf_set()
3690 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
3693 return -EINVAL; in rockchip_pinconf_set()
3695 rc = gpio->direction_input(gpio, pin - bank->pin_base); in rockchip_pinconf_set()
3700 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
3701 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
3702 return -ENOTSUPP; in rockchip_pinconf_set()
3705 pin - bank->pin_base, arg); in rockchip_pinconf_set()
3710 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
3711 return -ENOTSUPP; in rockchip_pinconf_set()
3714 pin - bank->pin_base, arg); in rockchip_pinconf_set()
3719 return -ENOTSUPP; in rockchip_pinconf_set()
3733 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_get()
3740 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
3741 return -EINVAL; in rockchip_pinconf_get()
3749 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
3750 return -ENOTSUPP; in rockchip_pinconf_get()
3752 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
3753 return -EINVAL; in rockchip_pinconf_get()
3758 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
3760 return -EINVAL; in rockchip_pinconf_get()
3762 if (!gpio || !gpio->get) { in rockchip_pinconf_get()
3767 rc = gpio->get(gpio, pin - bank->pin_base); in rockchip_pinconf_get()
3774 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
3775 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
3776 return -ENOTSUPP; in rockchip_pinconf_get()
3778 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
3785 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
3786 return -ENOTSUPP; in rockchip_pinconf_get()
3788 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
3795 return -ENOTSUPP; in rockchip_pinconf_get()
3811 { .compatible = "rockchip,gpio-bank" },
3812 { .compatible = "rockchip,rk3188-gpio-bank0" },
3825 info->nfunctions++; in rockchip_pinctrl_child_count()
3826 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
3835 struct device *dev = info->dev; in rockchip_pinctrl_parse_groups()
3846 grp->name = np->name; in rockchip_pinctrl_parse_groups()
3849 * the binding format is rockchip,pins = <bank pin mux CONFIG>, in rockchip_pinctrl_parse_groups()
3856 return dev_err_probe(dev, -EINVAL, in rockchip_pinctrl_parse_groups()
3857 … "%pOF: rockchip,pins: expected one or more of <bank pin mux CONFIG>, got %d args instead\n", in rockchip_pinctrl_parse_groups()
3860 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
3862 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3863 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); in rockchip_pinctrl_parse_groups()
3864 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
3865 return -ENOMEM; in rockchip_pinctrl_parse_groups()
3876 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3877 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
3881 return -EINVAL; in rockchip_pinctrl_parse_groups()
3885 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
3898 struct device *dev = info->dev; in rockchip_pinctrl_parse_functions()
3907 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
3910 func->name = np->name; in rockchip_pinctrl_parse_functions()
3911 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
3912 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
3915 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
3916 if (!func->groups) in rockchip_pinctrl_parse_functions()
3917 return -ENOMEM; in rockchip_pinctrl_parse_functions()
3920 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
3921 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
3933 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
3934 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
3940 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
3941 dev_dbg(dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
3943 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3944 if (!info->functions) in rockchip_pinctrl_parse_dt()
3945 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3947 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in rockchip_pinctrl_parse_dt()
3948 if (!info->groups) in rockchip_pinctrl_parse_dt()
3949 return -ENOMEM; in rockchip_pinctrl_parse_dt()
3970 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
3973 struct device *dev = &pdev->dev; in rockchip_pinctrl_register()
3978 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
3979 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
3980 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
3981 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
3982 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
3984 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); in rockchip_pinctrl_register()
3986 return -ENOMEM; in rockchip_pinctrl_register()
3988 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
3989 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
3992 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3993 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3995 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); in rockchip_pinctrl_register()
3999 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
4000 pdesc->number = k; in rockchip_pinctrl_register()
4001 pdesc->name = pin_names[pin]; in rockchip_pinctrl_register()
4005 INIT_LIST_HEAD(&pin_bank->deferred_pins); in rockchip_pinctrl_register()
4006 mutex_init(&pin_bank->deferred_lock); in rockchip_pinctrl_register()
4013 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); in rockchip_pinctrl_register()
4014 if (IS_ERR(info->pctl_dev)) in rockchip_pinctrl_register()
4015 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
4027 struct device *dev = &pdev->dev; in rockchip_pinctrl_get_soc_data()
4028 struct device_node *node = dev->of_node; in rockchip_pinctrl_get_soc_data()
4035 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
4037 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
4038 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
4039 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
4040 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
4041 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
4042 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
4045 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
4046 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
4047 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
4048 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
4052 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
4053 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
4056 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
4060 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
4061 if ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
4062 (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
4063 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
4065 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
4067 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || in rockchip_pinctrl_get_soc_data()
4068 (iom->type & IOMUX_L_SOURCE_PMU)) ? in rockchip_pinctrl_get_soc_data()
4073 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
4074 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
4075 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
4077 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
4079 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
4084 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
4090 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
4093 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) in rockchip_pinctrl_get_soc_data()
4100 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
4102 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
4103 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
4108 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
4116 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
4117 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
4120 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
4121 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
4122 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
4126 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
4127 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
4130 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
4131 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
4132 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
4148 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
4154 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save in rockchip_pinctrl_suspend()
4157 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
4158 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
4161 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
4174 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_resume()
4175 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
4182 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
4191 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
4192 struct device_node *np = dev->of_node, *node; in rockchip_pinctrl_probe()
4198 if (!dev->of_node) in rockchip_pinctrl_probe()
4199 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); in rockchip_pinctrl_probe()
4203 return -ENOMEM; in rockchip_pinctrl_probe()
4205 info->dev = dev; in rockchip_pinctrl_probe()
4209 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); in rockchip_pinctrl_probe()
4210 info->ctrl = ctrl; in rockchip_pinctrl_probe()
4214 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
4216 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
4217 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
4223 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
4225 info->regmap_base = in rockchip_pinctrl_probe()
4228 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
4229 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
4232 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
4237 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
4238 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
4239 info->regmap_pull = in rockchip_pinctrl_probe()
4245 info->regmap_pmu = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,pmu"); in rockchip_pinctrl_probe()
4248 info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); in rockchip_pinctrl_probe()
4256 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); in rockchip_pinctrl_probe()
4270 of_platform_depopulate(&pdev->dev); in rockchip_pinctrl_remove()
4272 for (i = 0; i < info->ctrl->nr_banks; i++) { in rockchip_pinctrl_remove()
4273 bank = &info->ctrl->pin_banks[i]; in rockchip_pinctrl_remove()
4275 mutex_lock(&bank->deferred_lock); in rockchip_pinctrl_remove()
4276 while (!list_empty(&bank->deferred_pins)) { in rockchip_pinctrl_remove()
4277 cfg = list_first_entry(&bank->deferred_pins, in rockchip_pinctrl_remove()
4279 list_del(&cfg->head); in rockchip_pinctrl_remove()
4282 mutex_unlock(&bank->deferred_lock); in rockchip_pinctrl_remove()
4297 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4312 .label = "PX30-GPIO",
4329 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
4336 .label = "RV1108-GPIO",
4359 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
4376 .label = "RV1126-GPIO",
4378 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
4392 PIN_BANK(2, 32, "gpio2"),
4399 .label = "RK2928-GPIO",
4408 PIN_BANK(2, 32, "gpio2"),
4414 .label = "RK3036-GPIO",
4423 PIN_BANK(2, 32, "gpio2"),
4432 .label = "RK3066a-GPIO",
4441 PIN_BANK(2, 32, "gpio2"),
4448 .label = "RK3066b-GPIO",
4456 PIN_BANK(2, 32, "gpio2"),
4463 .label = "RK3128-GPIO",
4476 PIN_BANK(2, 32, "gpio2"),
4483 .label = "RK3188-GPIO",
4494 PIN_BANK(2, 32, "gpio2"),
4501 .label = "RK3228-GPIO",
4521 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4545 .label = "RK3288-GPIO",
4564 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4581 .label = "RK3308-GPIO",
4596 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4610 .label = "RK3328-GPIO",
4629 PIN_BANK(2, 32, "gpio2"),
4636 .label = "RK3368-GPIO",
4656 -1,
4657 -1,
4676 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4700 .label = "RK3399-GPIO",
4734 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
4770 .label = "RK3506-GPIO",
4790 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4813 .label = "RK3528-GPIO",
4833 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4856 .label = "RK3562-GPIO",
4872 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4889 .label = "RK3568-GPIO",
4918 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
4926 .label = "RK3576-GPIO",
4938 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
4949 .label = "RK3588-GPIO",
4957 { .compatible = "rockchip,px30-pinctrl",
4959 { .compatible = "rockchip,rv1108-pinctrl",
4961 { .compatible = "rockchip,rv1126-pinctrl",
4963 { .compatible = "rockchip,rk2928-pinctrl",
4965 { .compatible = "rockchip,rk3036-pinctrl",
4967 { .compatible = "rockchip,rk3066a-pinctrl",
4969 { .compatible = "rockchip,rk3066b-pinctrl",
4971 { .compatible = "rockchip,rk3128-pinctrl",
4973 { .compatible = "rockchip,rk3188-pinctrl",
4975 { .compatible = "rockchip,rk3228-pinctrl",
4977 { .compatible = "rockchip,rk3288-pinctrl",
4979 { .compatible = "rockchip,rk3308-pinctrl",
4981 { .compatible = "rockchip,rk3328-pinctrl",
4983 { .compatible = "rockchip,rk3368-pinctrl",
4985 { .compatible = "rockchip,rk3399-pinctrl",
4987 { .compatible = "rockchip,rk3506-pinctrl",
4989 { .compatible = "rockchip,rk3528-pinctrl",
4991 { .compatible = "rockchip,rk3562-pinctrl",
4993 { .compatible = "rockchip,rk3568-pinctrl",
4995 { .compatible = "rockchip,rk3576-pinctrl",
4997 { .compatible = "rockchip,rk3588-pinctrl",
5006 .name = "rockchip-pinctrl",
5026 MODULE_ALIAS("platform:pinctrl-rockchip");