1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
27 #define PADS_SCHMITT_EN_REG(pin)	(PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))  argument
28 #define PADS_SCHMITT_EN_BIT(pin)	BIT((pin) % 32)  argument
31 #define PADS_PU_PD_REG(pin)		(PADS_PU_PD0 + 0x4 * ((pin) / 16))  argument
32 #define PADS_PU_PD_SHIFT(pin)		(2 * ((pin) % 16))  argument
45 #define PADS_SLEW_RATE_REG(pin)		(PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))  argument
46 #define PADS_SLEW_RATE_BIT(pin)		BIT((pin) % 32)  argument
49 #define PADS_DRIVE_STRENGTH_REG(pin)					\  argument
50 	(PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
51 #define PADS_DRIVE_STRENGTH_SHIFT(pin)	(2 * ((pin) % 16))  argument
87 	unsigned int pin;  member
513 	PISTACHIO_FUNCTION_NONE = -1,
638 		.pin = PISTACHIO_PIN_##_pin,			\
644 		.mux_reg = -1,					\
645 		.mux_shift = -1,				\
646 		.mux_mask = -1,					\
652 		.pin = PISTACHIO_PIN_MFIO(_pin),		\
658 		.mux_reg = -1,					\
659 		.mux_shift = -1,				\
660 		.mux_mask = -1,					\
666 		.pin = PISTACHIO_PIN_MFIO(_pin),			\
834 	return readl(pctl->base + reg);  in pctl_readl()
837 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)  in pctl_writel()  argument
839 	writel(val, pctl->base + reg);  in pctl_writel()
849 	return readl(bank->base + reg);  in gpio_readl()
852 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,  in gpio_writel()  argument
855 	writel(val, bank->base + reg);  in gpio_writel()
859 				    u32 reg, unsigned int bit, u32 val)  in gpio_mask_writel()  argument
865 	gpio_writel(bank, (0x10000 | val) << bit, reg);  in gpio_mask_writel()
884 	return pctl->ngroups;  in pistachio_pinctrl_get_groups_count()
892 	return pctl->groups[group].name;  in pistachio_pinctrl_get_group_name()
902 	*pins = &pctl->groups[group].pin;  in pistachio_pinctrl_get_group_pins()
920 	return pctl->nfunctions;  in pistachio_pinmux_get_functions_count()
928 	return pctl->functions[func].name;  in pistachio_pinmux_get_function_name()
938 	*groups = pctl->functions[func].groups;  in pistachio_pinmux_get_function_groups()
939 	*num_groups = pctl->functions[func].ngroups;  in pistachio_pinmux_get_function_groups()
948 	const struct pistachio_pin_group *pg = &pctl->groups[group];  in pistachio_pinmux_enable()
949 	const struct pistachio_function *pf = &pctl->functions[func];  in pistachio_pinmux_enable()
952 	u32 val;  in pistachio_pinmux_enable()  local
954 	if (pg->mux_reg > 0) {  in pistachio_pinmux_enable()
955 		for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {  in pistachio_pinmux_enable()
956 			if (pg->mux_option[i] == func)  in pistachio_pinmux_enable()
959 		if (i == ARRAY_SIZE(pg->mux_option)) {  in pistachio_pinmux_enable()
960 			dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",  in pistachio_pinmux_enable()
962 			return -EINVAL;  in pistachio_pinmux_enable()
965 		val = pctl_readl(pctl, pg->mux_reg);  in pistachio_pinmux_enable()
966 		val &= ~(pg->mux_mask << pg->mux_shift);  in pistachio_pinmux_enable()
967 		val |= i << pg->mux_shift;  in pistachio_pinmux_enable()
968 		pctl_writel(pctl, val, pg->mux_reg);  in pistachio_pinmux_enable()
970 		if (pf->scenarios) {  in pistachio_pinmux_enable()
971 			for (i = 0; i < pf->nscenarios; i++) {  in pistachio_pinmux_enable()
972 				if (pf->scenarios[i] == group)  in pistachio_pinmux_enable()
975 			if (WARN_ON(i == pf->nscenarios))  in pistachio_pinmux_enable()
976 				return -EINVAL;  in pistachio_pinmux_enable()
978 			val = pctl_readl(pctl, pf->scenario_reg);  in pistachio_pinmux_enable()
979 			val &= ~(pf->scenario_mask << pf->scenario_shift);  in pistachio_pinmux_enable()
980 			val |= i << pf->scenario_shift;  in pistachio_pinmux_enable()
981 			pctl_writel(pctl, val, pf->scenario_reg);  in pistachio_pinmux_enable()
985 	range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);  in pistachio_pinmux_enable()
987 		gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base);  in pistachio_pinmux_enable()
999 static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,  in pistachio_pinconf_get()  argument
1004 	u32 val, arg;  in pistachio_pinconf_get()  local
1008 		val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_get()
1009 		arg = !!(val & PADS_SCHMITT_EN_BIT(pin));  in pistachio_pinconf_get()
1012 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1013 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1014 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;  in pistachio_pinconf_get()
1017 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1018 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1019 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;  in pistachio_pinconf_get()
1022 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1023 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1024 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;  in pistachio_pinconf_get()
1027 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1028 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1029 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;  in pistachio_pinconf_get()
1032 		val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_get()
1033 		arg = !!(val & PADS_SLEW_RATE_BIT(pin));  in pistachio_pinconf_get()
1036 		val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>  in pistachio_pinconf_get()
1037 			PADS_DRIVE_STRENGTH_SHIFT(pin);  in pistachio_pinconf_get()
1038 		switch (val & PADS_DRIVE_STRENGTH_MASK) {  in pistachio_pinconf_get()
1055 		dev_dbg(pctl->dev, "Property %u not supported\n", param);  in pistachio_pinconf_get()
1056 		return -ENOTSUPP;  in pistachio_pinconf_get()
1064 static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,  in pistachio_pinconf_set()  argument
1069 	u32 drv, val, arg;  in pistachio_pinconf_set()  local
1078 			val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_set()
1080 				val |= PADS_SCHMITT_EN_BIT(pin);  in pistachio_pinconf_set()
1082 				val &= ~PADS_SCHMITT_EN_BIT(pin);  in pistachio_pinconf_set()
1083 			pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_set()
1086 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1087 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1088 			val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1089 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1092 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1093 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1094 			val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1095 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1098 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1099 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1100 			val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1101 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1104 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1105 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1106 			val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1107 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1110 			val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_set()
1112 				val |= PADS_SLEW_RATE_BIT(pin);  in pistachio_pinconf_set()
1114 				val &= ~PADS_SLEW_RATE_BIT(pin);  in pistachio_pinconf_set()
1115 			pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_set()
1118 			val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));  in pistachio_pinconf_set()
1119 			val &= ~(PADS_DRIVE_STRENGTH_MASK <<  in pistachio_pinconf_set()
1120 				 PADS_DRIVE_STRENGTH_SHIFT(pin));  in pistachio_pinconf_set()
1135 				dev_err(pctl->dev,  in pistachio_pinconf_set()
1138 				return -EINVAL;  in pistachio_pinconf_set()
1140 			val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);  in pistachio_pinconf_set()
1141 			pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));  in pistachio_pinconf_set()
1144 			dev_err(pctl->dev, "Property %u not supported\n",  in pistachio_pinconf_set()
1146 			return -ENOTSUPP;  in pistachio_pinconf_set()
1160 	.name = "pistachio-pinctrl",
1224 	gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);  in pistachio_gpio_irq_ack()
1231 	gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);  in pistachio_gpio_irq_mask()
1232 	gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data));  in pistachio_gpio_irq_mask()
1239 	gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data));  in pistachio_gpio_irq_unmask()
1240 	gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);  in pistachio_gpio_irq_unmask()
1247 	pistachio_gpio_direction_input(chip, data->hwirq);  in pistachio_gpio_irq_startup()
1259 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);  in pistachio_gpio_irq_set_type()
1260 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1262 		gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,  in pistachio_gpio_irq_set_type()
1266 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);  in pistachio_gpio_irq_set_type()
1267 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1269 		gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,  in pistachio_gpio_irq_set_type()
1273 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1275 		gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,  in pistachio_gpio_irq_set_type()
1279 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);  in pistachio_gpio_irq_set_type()
1280 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1284 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);  in pistachio_gpio_irq_set_type()
1285 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1289 		return -EINVAL;  in pistachio_gpio_irq_set_type()
1306 	unsigned int pin;  in pistachio_gpio_irq_handler()  local
1311 	for_each_set_bit(pin, &pending, 16)  in pistachio_gpio_irq_handler()
1312 		generic_handle_domain_irq(gc->irq.domain, pin);  in pistachio_gpio_irq_handler()
1349 	seq_printf(p, "GPIO%d", bank->instance);  in pistachio_gpio_irq_print_chip()
1369 	for (i = 0; i < pctl->nbanks; i++) {  in pistachio_gpio_register()
1375 		child = device_get_named_child_node(pctl->dev, child_name);  in pistachio_gpio_register()
1377 			dev_err(pctl->dev, "No node for bank %u\n", i);  in pistachio_gpio_register()
1378 			ret = -ENODEV;  in pistachio_gpio_register()
1382 		if (!fwnode_property_present(child, "gpio-controller")) {  in pistachio_gpio_register()
1384 			dev_err(pctl->dev,  in pistachio_gpio_register()
1385 				"No gpio-controller property for bank %u\n", i);  in pistachio_gpio_register()
1386 			ret = -ENODEV;  in pistachio_gpio_register()
1393 			dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n", i);  in pistachio_gpio_register()
1398 			dev_err(pctl->dev, "No IRQ for bank %u\n", i);  in pistachio_gpio_register()
1399 			ret = -EINVAL;  in pistachio_gpio_register()
1404 		bank = &pctl->gpio_banks[i];  in pistachio_gpio_register()
1405 		bank->pctl = pctl;  in pistachio_gpio_register()
1406 		bank->base = pctl->base + GPIO_BANK_BASE(i);  in pistachio_gpio_register()
1408 		bank->gpio_chip.parent = pctl->dev;  in pistachio_gpio_register()
1409 		bank->gpio_chip.fwnode = child;  in pistachio_gpio_register()
1411 		girq = &bank->gpio_chip.irq;  in pistachio_gpio_register()
1413 		girq->parent_handler = pistachio_gpio_irq_handler;  in pistachio_gpio_register()
1414 		girq->num_parents = 1;  in pistachio_gpio_register()
1415 		girq->parents = devm_kcalloc(pctl->dev, 1,  in pistachio_gpio_register()
1416 					     sizeof(*girq->parents),  in pistachio_gpio_register()
1418 		if (!girq->parents) {  in pistachio_gpio_register()
1419 			ret = -ENOMEM;  in pistachio_gpio_register()
1422 		girq->parents[0] = irq;  in pistachio_gpio_register()
1423 		girq->default_type = IRQ_TYPE_NONE;  in pistachio_gpio_register()
1424 		girq->handler = handle_level_irq;  in pistachio_gpio_register()
1426 		ret = gpiochip_add_data(&bank->gpio_chip, bank);  in pistachio_gpio_register()
1428 			dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",  in pistachio_gpio_register()
1433 		ret = gpiochip_add_pin_range(&bank->gpio_chip,  in pistachio_gpio_register()
1434 					     dev_name(pctl->dev), 0,  in pistachio_gpio_register()
1435 					     bank->pin_base, bank->npins);  in pistachio_gpio_register()
1437 			dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",  in pistachio_gpio_register()
1439 			gpiochip_remove(&bank->gpio_chip);  in pistachio_gpio_register()
1446 	for (; i > 0; i--) {  in pistachio_gpio_register()
1447 		bank = &pctl->gpio_banks[i - 1];  in pistachio_gpio_register()
1448 		gpiochip_remove(&bank->gpio_chip);  in pistachio_gpio_register()
1454 	{ .compatible = "img,pistachio-system-pinctrl", },
1462 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);  in pistachio_pinctrl_probe()
1464 		return -ENOMEM;  in pistachio_pinctrl_probe()
1465 	pctl->dev = &pdev->dev;  in pistachio_pinctrl_probe()
1466 	dev_set_drvdata(&pdev->dev, pctl);  in pistachio_pinctrl_probe()
1468 	pctl->base = devm_platform_ioremap_resource(pdev, 0);  in pistachio_pinctrl_probe()
1469 	if (IS_ERR(pctl->base))  in pistachio_pinctrl_probe()
1470 		return PTR_ERR(pctl->base);  in pistachio_pinctrl_probe()
1472 	pctl->pins = pistachio_pins;  in pistachio_pinctrl_probe()
1473 	pctl->npins = ARRAY_SIZE(pistachio_pins);  in pistachio_pinctrl_probe()
1474 	pctl->functions = pistachio_functions;  in pistachio_pinctrl_probe()
1475 	pctl->nfunctions = ARRAY_SIZE(pistachio_functions);  in pistachio_pinctrl_probe()
1476 	pctl->groups = pistachio_groups;  in pistachio_pinctrl_probe()
1477 	pctl->ngroups = ARRAY_SIZE(pistachio_groups);  in pistachio_pinctrl_probe()
1478 	pctl->gpio_banks = pistachio_gpio_banks;  in pistachio_pinctrl_probe()
1479 	pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);  in pistachio_pinctrl_probe()
1481 	pistachio_pinctrl_desc.pins = pctl->pins;  in pistachio_pinctrl_probe()
1482 	pistachio_pinctrl_desc.npins = pctl->npins;  in pistachio_pinctrl_probe()
1484 	pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,  in pistachio_pinctrl_probe()
1486 	if (IS_ERR(pctl->pctldev)) {  in pistachio_pinctrl_probe()
1487 		dev_err(&pdev->dev, "Failed to register pinctrl device\n");  in pistachio_pinctrl_probe()
1488 		return PTR_ERR(pctl->pctldev);  in pistachio_pinctrl_probe()
1496 		.name = "pistachio-pinctrl",