Lines Matching +full:pic32mzda +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
15 #include <linux/pinctrl/pinconf-generic.h>
23 #include <asm/mach-pic32/pic32.h>
25 #include "pinctrl-utils.h"
26 #include "pinctrl-pic32.h"
65 struct clk *clk; member
80 struct clk *clk; member
1702 return &pctl->gpio_banks[pin / PINS_PER_BANK]; in pctl_to_bank()
1709 return pctl->ngroups; in pic32_pinctrl_get_groups_count()
1717 return pctl->groups[group].name; in pic32_pinctrl_get_group_name()
1727 *pins = &pctl->groups[group].pin; in pic32_pinctrl_get_group_pins()
1745 return pctl->nfunctions; in pic32_pinmux_get_functions_count()
1753 return pctl->functions[func].name; in pic32_pinmux_get_function_name()
1763 *groups = pctl->functions[func].groups; in pic32_pinmux_get_function_groups()
1764 *num_groups = pctl->functions[func].ngroups; in pic32_pinmux_get_function_groups()
1773 const struct pic32_pin_group *pg = &pctl->groups[group]; in pic32_pinmux_enable()
1774 const struct pic32_function *pf = &pctl->functions[func]; in pic32_pinmux_enable()
1775 const char *fname = pf->name; in pic32_pinmux_enable()
1776 struct pic32_desc_function *functions = pg->functions; in pic32_pinmux_enable()
1778 while (functions->name) { in pic32_pinmux_enable()
1779 if (!strcmp(functions->name, fname)) { in pic32_pinmux_enable()
1780 dev_dbg(pctl->dev, in pic32_pinmux_enable()
1782 fname, functions->muxreg, functions->muxval); in pic32_pinmux_enable()
1784 writel(functions->muxval, pctl->reg_base + functions->muxreg); in pic32_pinmux_enable()
1792 dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); in pic32_pinmux_enable()
1794 return -EINVAL; in pic32_pinmux_enable()
1802 struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc); in pic32_gpio_request_enable()
1803 u32 mask = BIT(offset - bank->gpio_chip.base); in pic32_gpio_request_enable()
1805 dev_dbg(pctl->dev, "requesting gpio %d in bank %d with mask 0x%x\n", in pic32_gpio_request_enable()
1806 offset, bank->gpio_chip.base, mask); in pic32_gpio_request_enable()
1808 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_gpio_request_enable()
1819 writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); in pic32_gpio_direction_input()
1828 return !!(readl(bank->reg_base + PORT_REG) & BIT(offset)); in pic32_gpio_get()
1838 writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); in pic32_gpio_set()
1840 writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); in pic32_gpio_set()
1852 writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); in pic32_gpio_direction_output()
1861 struct gpio_chip *chip = range->gc; in pic32_gpio_set_direction()
1886 u32 mask = BIT(pin - bank->gpio_chip.base); in pic32_pinconf_get()
1891 arg = !!(readl(bank->reg_base + CNPU_REG) & mask); in pic32_pinconf_get()
1894 arg = !!(readl(bank->reg_base + CNPD_REG) & mask); in pic32_pinconf_get()
1897 arg = !(readl(bank->reg_base + ANSEL_REG) & mask); in pic32_pinconf_get()
1900 arg = !!(readl(bank->reg_base + ANSEL_REG) & mask); in pic32_pinconf_get()
1903 arg = !!(readl(bank->reg_base + ODCU_REG) & mask); in pic32_pinconf_get()
1906 arg = !!(readl(bank->reg_base + TRIS_REG) & mask); in pic32_pinconf_get()
1909 arg = !(readl(bank->reg_base + TRIS_REG) & mask); in pic32_pinconf_get()
1912 dev_err(pctl->dev, "Property %u not supported\n", param); in pic32_pinconf_get()
1913 return -ENOTSUPP; in pic32_pinconf_get()
1929 u32 offset = pin - bank->gpio_chip.base; in pic32_pinconf_set()
1932 dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", in pic32_pinconf_set()
1933 pin, bank->gpio_chip.base, mask); in pic32_pinconf_set()
1941 dev_dbg(pctl->dev, " pullup\n"); in pic32_pinconf_set()
1942 writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); in pic32_pinconf_set()
1945 dev_dbg(pctl->dev, " pulldown\n"); in pic32_pinconf_set()
1946 writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); in pic32_pinconf_set()
1949 dev_dbg(pctl->dev, " digital\n"); in pic32_pinconf_set()
1950 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_pinconf_set()
1953 dev_dbg(pctl->dev, " analog\n"); in pic32_pinconf_set()
1954 writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); in pic32_pinconf_set()
1957 dev_dbg(pctl->dev, " opendrain\n"); in pic32_pinconf_set()
1958 writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); in pic32_pinconf_set()
1961 pic32_gpio_direction_input(&bank->gpio_chip, offset); in pic32_pinconf_set()
1964 pic32_gpio_direction_output(&bank->gpio_chip, in pic32_pinconf_set()
1968 dev_err(pctl->dev, "Property %u not supported\n", in pic32_pinconf_set()
1970 return -ENOTSUPP; in pic32_pinconf_set()
1984 .name = "pic32-pinctrl",
1995 if (readl(bank->reg_base + TRIS_REG) & BIT(offset)) in pic32_gpio_get_direction()
2005 writel(0, bank->reg_base + CNF_REG); in pic32_gpio_irq_ack()
2012 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); in pic32_gpio_irq_mask()
2013 gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); in pic32_gpio_irq_mask()
2020 gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); in pic32_gpio_irq_unmask()
2021 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_unmask()
2028 pic32_gpio_direction_input(chip, data->hwirq); in pic32_gpio_irq_startup()
2042 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2044 writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); in pic32_gpio_irq_set_type()
2046 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2050 writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); in pic32_gpio_irq_set_type()
2052 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2054 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2058 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2060 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2062 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2065 return -EINVAL; in pic32_gpio_irq_set_type()
2080 cnen_rise = readl(bank->reg_base + CNEN_REG); in pic32_gpio_get_pending()
2081 cnne_fall = readl(bank->reg_base + CNNE_REG); in pic32_gpio_get_pending()
2104 stat = readl(bank->reg_base + CNF_REG); in pic32_gpio_irq_handler()
2108 generic_handle_domain_irq(gc->irq.domain, pin); in pic32_gpio_irq_handler()
2149 seq_printf(p, "GPIO%d", bank->instance); in pic32_gpio_irq_print_chip()
2168 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); in pic32_pinctrl_probe()
2170 return -ENOMEM; in pic32_pinctrl_probe()
2171 pctl->dev = &pdev->dev; in pic32_pinctrl_probe()
2172 dev_set_drvdata(&pdev->dev, pctl); in pic32_pinctrl_probe()
2174 pctl->reg_base = devm_platform_ioremap_resource(pdev, 0); in pic32_pinctrl_probe()
2175 if (IS_ERR(pctl->reg_base)) in pic32_pinctrl_probe()
2176 return PTR_ERR(pctl->reg_base); in pic32_pinctrl_probe()
2178 pctl->clk = devm_clk_get(&pdev->dev, NULL); in pic32_pinctrl_probe()
2179 if (IS_ERR(pctl->clk)) { in pic32_pinctrl_probe()
2180 ret = PTR_ERR(pctl->clk); in pic32_pinctrl_probe()
2181 dev_err(&pdev->dev, "clk get failed\n"); in pic32_pinctrl_probe()
2185 ret = clk_prepare_enable(pctl->clk); in pic32_pinctrl_probe()
2187 dev_err(&pdev->dev, "clk enable failed\n"); in pic32_pinctrl_probe()
2191 pctl->pins = pic32_pins; in pic32_pinctrl_probe()
2192 pctl->npins = ARRAY_SIZE(pic32_pins); in pic32_pinctrl_probe()
2193 pctl->functions = pic32_functions; in pic32_pinctrl_probe()
2194 pctl->nfunctions = ARRAY_SIZE(pic32_functions); in pic32_pinctrl_probe()
2195 pctl->groups = pic32_groups; in pic32_pinctrl_probe()
2196 pctl->ngroups = ARRAY_SIZE(pic32_groups); in pic32_pinctrl_probe()
2197 pctl->gpio_banks = pic32_gpio_banks; in pic32_pinctrl_probe()
2198 pctl->nbanks = ARRAY_SIZE(pic32_gpio_banks); in pic32_pinctrl_probe()
2200 pic32_pinctrl_desc.pins = pctl->pins; in pic32_pinctrl_probe()
2201 pic32_pinctrl_desc.npins = pctl->npins; in pic32_pinctrl_probe()
2205 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pic32_pinctrl_desc, in pic32_pinctrl_probe()
2207 if (IS_ERR(pctl->pctldev)) { in pic32_pinctrl_probe()
2208 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); in pic32_pinctrl_probe()
2209 return PTR_ERR(pctl->pctldev); in pic32_pinctrl_probe()
2217 struct device_node *np = pdev->dev.of_node; in pic32_gpio_probe()
2223 if (of_property_read_u32(np, "microchip,gpio-bank", &id)) { in pic32_gpio_probe()
2224 dev_err(&pdev->dev, "microchip,gpio-bank property not found\n"); in pic32_gpio_probe()
2225 return -EINVAL; in pic32_gpio_probe()
2229 dev_err(&pdev->dev, "invalid microchip,gpio-bank property\n"); in pic32_gpio_probe()
2230 return -EINVAL; in pic32_gpio_probe()
2235 bank->reg_base = devm_platform_ioremap_resource(pdev, 0); in pic32_gpio_probe()
2236 if (IS_ERR(bank->reg_base)) in pic32_gpio_probe()
2237 return PTR_ERR(bank->reg_base); in pic32_gpio_probe()
2243 bank->clk = devm_clk_get(&pdev->dev, NULL); in pic32_gpio_probe()
2244 if (IS_ERR(bank->clk)) { in pic32_gpio_probe()
2245 ret = PTR_ERR(bank->clk); in pic32_gpio_probe()
2246 dev_err(&pdev->dev, "clk get failed\n"); in pic32_gpio_probe()
2250 ret = clk_prepare_enable(bank->clk); in pic32_gpio_probe()
2252 dev_err(&pdev->dev, "clk enable failed\n"); in pic32_gpio_probe()
2256 bank->gpio_chip.parent = &pdev->dev; in pic32_gpio_probe()
2258 girq = &bank->gpio_chip.irq; in pic32_gpio_probe()
2260 girq->parent_handler = pic32_gpio_irq_handler; in pic32_gpio_probe()
2261 girq->num_parents = 1; in pic32_gpio_probe()
2262 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), in pic32_gpio_probe()
2264 if (!girq->parents) in pic32_gpio_probe()
2265 return -ENOMEM; in pic32_gpio_probe()
2266 girq->default_type = IRQ_TYPE_NONE; in pic32_gpio_probe()
2267 girq->handler = handle_level_irq; in pic32_gpio_probe()
2268 girq->parents[0] = irq; in pic32_gpio_probe()
2269 ret = gpiochip_add_data(&bank->gpio_chip, bank); in pic32_gpio_probe()
2271 dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", in pic32_gpio_probe()
2279 { .compatible = "microchip,pic32mzda-pinctrl", },
2285 .name = "pic32-pinctrl",
2293 { .compatible = "microchip,pic32mzda-gpio", },
2299 .name = "pic32-gpio",