Lines Matching +full:sparx5 +full:- +full:sgpio +full:- +full:bank
1 // SPDX-License-Identifier: GPL-2.0-or-later
138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
144 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
160 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); in sgpio_readl()
171 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
172 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); in sgpio_writel()
181 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits()
182 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret); in sgpio_clrsetbits()
187 int width = priv->bitcount - 1; in sgpio_configure_bitstream()
190 switch (priv->properties->arch) { in sgpio_configure_bitstream()
216 switch (priv->properties->arch) { in sgpio_configure_clock()
243 switch (priv->properties->arch) { in sgpio_single_shot()
256 return -EINVAL; in sgpio_single_shot()
267 mutex_lock(&priv->poll_lock); in sgpio_single_shot()
268 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat, in sgpio_single_shot()
273 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl, in sgpio_single_shot()
277 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat); in sgpio_single_shot()
279 mutex_unlock(&priv->poll_lock); in sgpio_single_shot()
288 unsigned int bit = SGPIO_SRC_BITS * addr->bit; in sgpio_output_set()
289 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port); in sgpio_output_set()
294 switch (priv->properties->arch) { in sgpio_output_set()
308 return -EINVAL; in sgpio_output_set()
311 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, in sgpio_output_set()
328 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); in sgpio_output_get()
329 unsigned int bit = SGPIO_SRC_BITS * addr->bit; in sgpio_output_get()
331 switch (priv->properties->arch) { in sgpio_output_get()
351 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); in sgpio_input_get()
357 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_get() local
359 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_get()
367 val = bank->is_input; in sgpio_pinconf_get()
371 val = !bank->is_input; in sgpio_pinconf_get()
375 if (bank->is_input) in sgpio_pinconf_get()
376 return -EINVAL; in sgpio_pinconf_get()
381 return -ENOTSUPP; in sgpio_pinconf_get()
392 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_set() local
393 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_set()
406 if (bank->is_input) in sgpio_pinconf_set()
407 return -EINVAL; in sgpio_pinconf_set()
412 err = -ENOTSUPP; in sgpio_pinconf_set()
458 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_gpio_set_direction() local
460 return (input == bank->is_input) ? 0 : -EINVAL; in sgpio_gpio_set_direction()
467 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_gpio_request_enable() local
468 struct sgpio_priv *priv = bank->priv; in sgpio_gpio_request_enable()
473 if ((priv->ports & BIT(addr.port)) == 0) { in sgpio_gpio_request_enable()
474 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", in sgpio_gpio_request_enable()
476 return -EINVAL; in sgpio_gpio_request_enable()
493 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pctl_get_groups_count() local
495 return bank->pctl_desc.npins; in sgpio_pctl_get_groups_count()
501 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pctl_get_group_name() local
503 return bank->pctl_desc.pins[group].name; in sgpio_pctl_get_group_name()
511 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pctl_get_group_pins() local
513 *pins = &bank->pctl_desc.pins[group].number; in sgpio_pctl_get_group_pins()
529 struct sgpio_bank *bank = gpiochip_get_data(gc); in microchip_sgpio_direction_input() local
531 /* Fixed-position function */ in microchip_sgpio_direction_input()
532 return bank->is_input ? 0 : -EINVAL; in microchip_sgpio_direction_input()
538 struct sgpio_bank *bank = gpiochip_get_data(gc); in microchip_sgpio_direction_output() local
539 struct sgpio_priv *priv = bank->priv; in microchip_sgpio_direction_output()
542 /* Fixed-position function */ in microchip_sgpio_direction_output()
543 if (bank->is_input) in microchip_sgpio_direction_output()
544 return -EINVAL; in microchip_sgpio_direction_output()
553 struct sgpio_bank *bank = gpiochip_get_data(gc); in microchip_sgpio_get_direction() local
555 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; in microchip_sgpio_get_direction()
566 struct sgpio_bank *bank = gpiochip_get_data(gc); in microchip_sgpio_get_value() local
567 struct sgpio_priv *priv = bank->priv; in microchip_sgpio_get_value()
572 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); in microchip_sgpio_get_value()
579 struct sgpio_bank *bank = gpiochip_get_data(gc); in microchip_sgpio_of_xlate() local
580 struct sgpio_priv *priv = bank->priv; in microchip_sgpio_of_xlate()
587 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || in microchip_sgpio_of_xlate()
588 gpiospec->args[1] > priv->bitcount) in microchip_sgpio_of_xlate()
589 return -EINVAL; in microchip_sgpio_of_xlate()
591 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); in microchip_sgpio_of_xlate()
593 if (pin > gc->ngpio) in microchip_sgpio_of_xlate()
594 return -EINVAL; in microchip_sgpio_of_xlate()
597 *flags = gpiospec->args[2]; in microchip_sgpio_of_xlate()
604 const char *range_property_name = "microchip,sgpio-port-ranges"; in microchip_sgpio_get_ports()
605 struct device *dev = priv->dev; in microchip_sgpio_get_ports()
613 nranges == -EINVAL ? "Missing" : "Invalid", in microchip_sgpio_get_ports()
615 return -EINVAL; in microchip_sgpio_get_ports()
631 dev_err(dev, "Ill-formed port-range [%d:%d]\n", in microchip_sgpio_get_ports()
634 priv->ports |= GENMASK(end, start); in microchip_sgpio_get_ports()
645 struct sgpio_bank *bank = gpiochip_get_data(chip); in microchip_sgpio_irq_settype() local
651 sgpio_pin_to_addr(bank->priv, gpio, &addr); in microchip_sgpio_irq_settype()
653 spin_lock_irqsave(&bank->priv->lock, flags); in microchip_sgpio_irq_settype()
656 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); in microchip_sgpio_irq_settype()
657 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); in microchip_sgpio_irq_settype()
660 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, in microchip_sgpio_irq_settype()
662 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, in microchip_sgpio_irq_settype()
666 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, in microchip_sgpio_irq_settype()
669 /* Possibly re-enable interrupts */ in microchip_sgpio_irq_settype()
670 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); in microchip_sgpio_irq_settype()
672 spin_unlock_irqrestore(&bank->priv->lock, flags); in microchip_sgpio_irq_settype()
680 struct sgpio_bank *bank = gpiochip_get_data(chip); in microchip_sgpio_irq_setreg() local
684 sgpio_pin_to_addr(bank->priv, gpio, &addr); in microchip_sgpio_irq_setreg()
687 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); in microchip_sgpio_irq_setreg()
689 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); in microchip_sgpio_irq_setreg()
697 gpiochip_disable_irq(chip, data->hwirq); in microchip_sgpio_irq_mask()
704 gpiochip_enable_irq(chip, data->hwirq); in microchip_sgpio_irq_unmask()
711 struct sgpio_bank *bank = gpiochip_get_data(chip); in microchip_sgpio_irq_ack() local
715 sgpio_pin_to_addr(bank->priv, gpio, &addr); in microchip_sgpio_irq_ack()
717 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit); in microchip_sgpio_irq_ack()
744 return -EINVAL; in microchip_sgpio_irq_set_type()
764 struct sgpio_bank *bank = gpiochip_get_data(chip); in sgpio_irq_handler() local
765 struct sgpio_priv *priv = bank->priv; in sgpio_irq_handler()
769 for (bit = 0; bit < priv->bitcount; bit++) { in sgpio_irq_handler()
778 generic_handle_domain_irq(chip->irq.domain, gpio); in sgpio_irq_handler()
793 struct sgpio_bank *bank; in microchip_sgpio_register_bank() local
798 /* Get overall bank struct */ in microchip_sgpio_register_bank()
799 bank = (bankno == 0) ? &priv->in : &priv->out; in microchip_sgpio_register_bank()
800 bank->priv = priv; in microchip_sgpio_register_bank()
803 dev_info(dev, "failed to get number of gpios for bank%d\n", in microchip_sgpio_register_bank()
808 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; in microchip_sgpio_register_bank()
809 if (priv->bitcount > SGPIO_MAX_BITS) { in microchip_sgpio_register_bank()
812 return -EINVAL; in microchip_sgpio_register_bank()
815 pctl_desc = &bank->pctl_desc; in microchip_sgpio_register_bank()
816 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", in microchip_sgpio_register_bank()
818 bank->is_input ? "in" : "out"); in microchip_sgpio_register_bank()
819 if (!pctl_desc->name) in microchip_sgpio_register_bank()
820 return -ENOMEM; in microchip_sgpio_register_bank()
822 pctl_desc->pctlops = &sgpio_pctl_ops; in microchip_sgpio_register_bank()
823 pctl_desc->pmxops = &sgpio_pmx_ops; in microchip_sgpio_register_bank()
824 pctl_desc->confops = &sgpio_confops; in microchip_sgpio_register_bank()
825 pctl_desc->owner = THIS_MODULE; in microchip_sgpio_register_bank()
829 return -ENOMEM; in microchip_sgpio_register_bank()
831 pctl_desc->npins = ngpios; in microchip_sgpio_register_bank()
832 pctl_desc->pins = pins; in microchip_sgpio_register_bank()
842 bank->is_input ? 'I' : 'O', in microchip_sgpio_register_bank()
845 return -ENOMEM; in microchip_sgpio_register_bank()
848 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); in microchip_sgpio_register_bank()
852 gc = &bank->gpio; in microchip_sgpio_register_bank()
853 gc->label = pctl_desc->name; in microchip_sgpio_register_bank()
854 gc->parent = dev; in microchip_sgpio_register_bank()
855 gc->fwnode = fwnode; in microchip_sgpio_register_bank()
856 gc->owner = THIS_MODULE; in microchip_sgpio_register_bank()
857 gc->get_direction = microchip_sgpio_get_direction; in microchip_sgpio_register_bank()
858 gc->direction_input = microchip_sgpio_direction_input; in microchip_sgpio_register_bank()
859 gc->direction_output = microchip_sgpio_direction_output; in microchip_sgpio_register_bank()
860 gc->get = microchip_sgpio_get_value; in microchip_sgpio_register_bank()
861 gc->set = microchip_sgpio_set_value; in microchip_sgpio_register_bank()
862 gc->request = gpiochip_generic_request; in microchip_sgpio_register_bank()
863 gc->free = gpiochip_generic_free; in microchip_sgpio_register_bank()
864 gc->of_xlate = microchip_sgpio_of_xlate; in microchip_sgpio_register_bank()
865 gc->of_gpio_n_cells = 3; in microchip_sgpio_register_bank()
866 gc->base = -1; in microchip_sgpio_register_bank()
867 gc->ngpio = ngpios; in microchip_sgpio_register_bank()
868 gc->can_sleep = !bank->is_input; in microchip_sgpio_register_bank()
870 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { in microchip_sgpio_register_bank()
875 struct gpio_irq_chip *girq = &gc->irq; in microchip_sgpio_register_bank()
878 girq->parent_handler = sgpio_irq_handler; in microchip_sgpio_register_bank()
879 girq->num_parents = 1; in microchip_sgpio_register_bank()
880 girq->parents = devm_kcalloc(dev, 1, in microchip_sgpio_register_bank()
881 sizeof(*girq->parents), in microchip_sgpio_register_bank()
883 if (!girq->parents) in microchip_sgpio_register_bank()
884 return -ENOMEM; in microchip_sgpio_register_bank()
885 girq->parents[0] = irq; in microchip_sgpio_register_bank()
886 girq->default_type = IRQ_TYPE_NONE; in microchip_sgpio_register_bank()
887 girq->handler = handle_bad_irq; in microchip_sgpio_register_bank()
897 ret = devm_gpiochip_add_data(dev, gc, bank); in microchip_sgpio_register_bank()
907 struct device *dev = &pdev->dev; in microchip_sgpio_probe()
921 return -ENOMEM; in microchip_sgpio_probe()
923 priv->dev = dev; in microchip_sgpio_probe()
924 spin_lock_init(&priv->lock); in microchip_sgpio_probe()
925 mutex_init(&priv->poll_lock); in microchip_sgpio_probe()
927 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); in microchip_sgpio_probe()
937 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) in microchip_sgpio_probe()
938 priv->clock = 12500000; in microchip_sgpio_probe()
939 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { in microchip_sgpio_probe()
940 dev_err(dev, "Invalid frequency %d\n", priv->clock); in microchip_sgpio_probe()
941 return -EINVAL; in microchip_sgpio_probe()
944 priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config); in microchip_sgpio_probe()
945 if (IS_ERR(priv->regs)) in microchip_sgpio_probe()
946 return PTR_ERR(priv->regs); in microchip_sgpio_probe()
948 priv->properties = device_get_match_data(dev); in microchip_sgpio_probe()
949 priv->in.is_input = true; in microchip_sgpio_probe()
959 return -EINVAL; in microchip_sgpio_probe()
971 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { in microchip_sgpio_probe()
973 return -ERANGE; in microchip_sgpio_probe()
978 val = max(2U, div_clock / priv->clock); in microchip_sgpio_probe()
983 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); in microchip_sgpio_probe()
990 .compatible = "microchip,sparx5-sgpio",
993 .compatible = "mscc,luton-sgpio",
996 .compatible = "mscc,ocelot-sgpio",
1006 .name = "pinctrl-microchip-sgpio",
1014 MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");