1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
173 		(!(enabled_socs & GENMASK(version - 1, 0))  in is_soc_or_above()
174 		 || jzpc->info->version >= version);  in is_soc_or_above()
212 	INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
213 	INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
214 	INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
215 	INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
216 	INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
217 	INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
218 	INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
219 	INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
220 	INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
221 	INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
222 	INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
223 	INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
224 	INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
225 	INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
226 	INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
227 	INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
232 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
233 static const char *jz4730_uart0_groups[] = { "uart0-data", };
234 static const char *jz4730_uart1_groups[] = { "uart1-data", };
235 static const char *jz4730_uart2_groups[] = { "uart2-data", };
236 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
238 	"lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
241 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
308 	INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
309 	INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
310 	INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
311 	INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
312 	INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
313 	INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
314 	INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
315 	INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
316 	INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
317 	INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
318 	INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
319 	INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
320 	INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
321 	INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
322 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
333 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
334 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
335 static const char *jz4740_uart1_groups[] = { "uart1-data", };
337 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
340 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
411 	INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
412 	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
414 	INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
415 	INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
416 	INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
417 	INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
418 	INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
419 	INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
420 	INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
421 	INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
422 	INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
423 	INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
424 	INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
425 	INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
426 	INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
427 	INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
428 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
437 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
438 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
439 static const char *jz4725b_uart_groups[] = { "uart-data", };
441 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
442 	"lcd-special", "lcd-generic",
445 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
446 	"nand-cle-ale", "nand-fre-fwe",
530 	INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
531 	INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
532 	INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
533 	INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
534 	INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
535 	INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
536 	INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
537 	INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
538 	INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
539 	INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
540 	INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
541 	INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
542 	INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
543 	INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
544 	INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
545 	INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
546 	INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
547 	INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
548 	INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
549 	INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
550 	INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
551 	INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
552 	INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
553 	INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
554 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
563 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
564 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
565 static const char *jz4750_uart2_groups[] = { "uart2-data", };
566 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
568 	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
570 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
571 static const char *jz4750_i2c_groups[] = { "i2c-data", };
572 static const char *jz4750_cim_groups[] = { "cim-data", };
574 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
575 	"lcd-special", "lcd-generic",
578 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
679 	INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
680 	INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
681 	INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
682 	INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
683 	INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
684 	INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
685 	INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
686 	INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
687 	INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
688 	INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
689 	INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
690 	INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
691 	INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
692 	INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
693 	INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
694 	INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
695 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
697 	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
699 	INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
700 	INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
701 	INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
702 	INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
703 	INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
704 	INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
705 	INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
706 	INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
708 	INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
709 	INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
710 	INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
711 	INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
712 	INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
713 	INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
714 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
723 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
724 static const char *jz4755_uart1_groups[] = { "uart1-data", };
725 static const char *jz4755_uart2_groups[] = { "uart2-data", };
727 	"ssi-dt-b", "ssi-dt-f",
728 	"ssi-dr-b", "ssi-dr-f",
729 	"ssi-clk-b", "ssi-clk-f",
730 	"ssi-gpc-b", "ssi-gpc-f",
731 	"ssi-ce0-b", "ssi-ce0-f",
732 	"ssi-ce1-b", "ssi-ce1-f",
734 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
735 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
736 static const char *jz4755_i2c_groups[] = { "i2c-data", };
737 static const char *jz4755_cim_groups[] = { "cim-data", };
739 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
740 	"lcd-special", "lcd-generic",
743 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
918 	INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
919 	INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
920 	INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
921 	INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
922 	INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
923 	INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
924 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
926 	INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
927 	INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
928 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
929 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
930 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
931 	INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
932 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
933 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
934 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
935 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
936 	INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
937 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
938 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
939 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
940 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
941 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
942 	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
943 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
944 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
945 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
946 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
947 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
948 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
949 	INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
950 	INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
951 	INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
952 	INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
953 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
954 	INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
955 	INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
956 	INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
957 	INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
958 	INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
959 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
960 	INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
961 	INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
962 	INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
963 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
964 	INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
965 	INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
966 	INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
967 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
968 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
969 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
970 	INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
971 	INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
972 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
973 	INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
974 	INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
975 	INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
976 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
977 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
978 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
979 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
981 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
982 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
983 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
984 	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
985 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
986 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
987 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
988 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
989 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
990 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
991 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
992 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
993 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
994 	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
995 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
996 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
997 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
998 	INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
999 	INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
1000 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
1001 	INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
1002 	INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
1003 	INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
1004 	INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
1005 	INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
1006 	INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
1007 	INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
1008 	INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
1009 	INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
1010 	INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
1011 	INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
1012 	INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
1013 	INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
1014 	INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
1015 	INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
1016 	INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
1025 	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1028 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1029 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1030 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1031 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1033 	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1034 	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1035 	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1036 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1037 	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1038 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1041 	"ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1042 	"ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1043 	"ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1044 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1045 	"ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1046 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1049 	"mmc0-1bit-a", "mmc0-4bit-a",
1050 	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1053 	"mmc1-1bit-d", "mmc1-4bit-d",
1054 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1057 	"mmc2-1bit-b", "mmc2-4bit-b",
1058 	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1061 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1062 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1064 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1065 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1066 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1067 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1068 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1069 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1070 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1071 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1072 static const char *jz4760_cim_groups[] = { "cim-data", };
1074 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1075 	"lcd-special", "lcd-generic",
1085 static const char *jz4760_otg_groups[] = { "otg-vbus", };
1098 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1),
1099 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2),
1100 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3),
1101 	INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4),
1102 	INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5),
1103 	INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6),
1263 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1264 	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1265 	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1266 	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1267 	INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1268 	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1269 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1271 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1272 	INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1273 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1274 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1275 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1276 	INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1277 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1278 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1279 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1280 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1281 	INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1282 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1283 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1284 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1285 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1286 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1287 	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1288 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1289 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1290 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1291 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1292 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1293 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1294 	INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1295 	INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1296 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1297 	INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1298 	INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1299 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1300 	INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1301 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1302 	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1303 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1304 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1305 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1306 	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1307 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1308 	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1309 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1310 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1311 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1312 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1314 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1315 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1316 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1317 	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1318 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1319 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1320 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1321 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1322 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1323 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1324 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1325 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1326 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1327 	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1328 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1329 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1330 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1331 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1332 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1333 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1334 	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1335 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1336 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1337 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1338 	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1339 	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1340 	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1341 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1342 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1343 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1344 	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1345 	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1346 	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1347 	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1348 	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1349 	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1350 	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1351 	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1360 	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1361 	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1362 	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1365 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1366 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1367 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1368 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1370 	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1371 	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1372 	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1373 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1374 	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1375 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1378 	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1379 	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1380 	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1381 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1382 	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1383 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1386 	"mmc0-1bit-a", "mmc0-4bit-a",
1387 	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1390 	"mmc1-1bit-d", "mmc1-4bit-d",
1391 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1394 	"mmc2-1bit-b", "mmc2-4bit-b",
1395 	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1398 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1399 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1401 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1402 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1403 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1404 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1405 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1406 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1407 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1408 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1409 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1410 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1412 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1413 	"lcd-special", "lcd-generic",
1423 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1436 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1437 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1438 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1439 	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1440 	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1441 	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1582 	INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1583 	INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1584 	INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1585 	INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1586 	INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1587 	INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1588 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1590 	INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1591 	INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1592 	INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1593 	INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1594 	INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1595 	INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1596 	INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1597 	INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1598 	INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1599 	INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1600 	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1601 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1602 	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1603 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1604 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1605 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1606 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1607 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1608 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1609 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1610 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1611 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1612 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1613 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1614 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1615 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1616 	INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1617 	INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1618 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1619 	INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1620 	INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1621 	INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1622 	INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1623 	INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1624 	INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1625 	INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1626 	INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1627 	INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1628 	INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1629 	INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1631 	INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1632 	INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1633 	INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1634 	INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1635 	INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1636 	INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1637 	INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1642 	INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1643 	INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1645 	INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1647 	INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1649 	INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1652 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1653 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1654 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1655 static const char *jz4775_uart3_groups[] = { "uart3-data", };
1657 	"ssi-dt-a", "ssi-dt-d",
1658 	"ssi-dr-a", "ssi-dr-d",
1659 	"ssi-clk-a", "ssi-clk-d",
1660 	"ssi-gpc",
1661 	"ssi-ce0-a", "ssi-ce0-d",
1662 	"ssi-ce1",
1665 	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1666 	"mmc0-1bit-e", "mmc0-4bit-e",
1669 	"mmc1-1bit-d", "mmc1-4bit-d",
1670 	"mmc1-1bit-e", "mmc1-4bit-e",
1673 	"mmc2-1bit-b", "mmc2-4bit-b",
1674 	"mmc2-1bit-e", "mmc2-4bit-e",
1677 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1678 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1680 static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1681 static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1682 static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1683 static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1684 static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1685 static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1687 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1690 static const char *jz4775_cim_groups[] = { "cim-data", };
1692 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1693 	"lcd-special", "lcd-generic",
1700 	"mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1702 static const char *jz4775_otg_groups[] = { "otg-vbus", };
1714 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1),
1715 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2),
1716 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3),
1720 	INGENIC_PIN_FUNCTION("i2s", jz4775_i2s),
1803 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1804 	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1805 	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1806 	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1807 	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1808 	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1809 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1811 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1812 	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1813 	INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1814 	INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1815 	INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1816 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1817 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1818 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1819 	INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1820 	INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1821 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1822 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1823 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1824 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1825 	INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1826 	INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1827 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1828 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1829 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1830 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1831 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1832 	INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1833 	INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1834 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1835 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1836 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1837 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1838 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1839 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1840 	INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1841 	INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1842 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1843 	INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1844 	INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1845 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1846 	INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1847 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1848 	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1849 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1850 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1851 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1852 	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1853 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1854 	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1855 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1856 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1857 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1858 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1860 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1861 	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1862 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1863 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1864 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1865 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1866 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1867 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1868 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1869 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1870 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1871 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1872 	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1873 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1874 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1875 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1876 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1877 	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1878 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1879 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1880 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1881 	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1882 	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1883 	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1884 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1885 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1886 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1887 	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1888 	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1889 	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1890 	INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1891 	INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1892 	INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1894 	INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1895 	INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1897 	INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1898 	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1899 	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1900 	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1901 	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1902 	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1903 	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1904 	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1905 	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1916 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1917 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1919 	"ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1920 	"ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1921 	"ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1922 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1923 	"ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1924 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1927 	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1928 	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1929 	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1930 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1931 	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1932 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1935 	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1936 	"mmc0-1bit-e", "mmc0-4bit-e",
1939 	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1942 	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1945 	"nemc-data", "nemc-cle-ale", "nemc-addr",
1946 	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1948 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1949 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1951 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1954 static const char *jz4780_cim_groups[] = { "cim-data", };
1955 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1969 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1970 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1971 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1972 	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1973 	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1974 	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1980 	INGENIC_PIN_FUNCTION("i2s", jz4780_i2s),
1992 	INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc),
2091 	INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2092 	INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2093 	INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2094 	INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2095 	INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2096 	INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2097 	INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2098 	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2099 	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2100 	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2101 	INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2102 	INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2103 	INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2104 	INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2105 	INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2106 	INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2107 	INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2108 	INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2109 	INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2110 	INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2111 	INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2112 	INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2113 	INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2114 	INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2115 	INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2116 	INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2117 	INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2118 	INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2119 	INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2120 	INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2121 	INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2122 	INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2123 	INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2124 	INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2125 	INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2126 	INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2127 	INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2128 	INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2129 	INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2130 	INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2131 	INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2132 	INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2133 	INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2134 	INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2135 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2136 	INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2137 	INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2138 	INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2139 	INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2140 	INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2141 	INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2150 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2152 	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
2154 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2155 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2157 	"ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2158 	"ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2159 	"ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2160 	"ssi-gpc-a-20", "ssi-gpc-a-31",
2161 	"ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2162 	"ssi-ce1-a-21", "ssi-ce1-a-30",
2165 	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2168 	"mmc1-1bit", "mmc1-4bit",
2171 	"emc-8bit-data", "emc-16bit-data",
2172 	"emc-addr", "emc-rd-we", "emc-wait",
2174 static const char *x1000_cs1_groups[] = { "emc-cs1", };
2175 static const char *x1000_cs2_groups[] = { "emc-cs2", };
2176 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2177 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2178 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2180 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2182 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2183 static const char *x1000_cim_groups[] = { "cim-data", };
2184 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2201 	INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1),
2202 	INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2),
2206 	INGENIC_PIN_FUNCTION("i2s", x1000_i2s),
2219 	regmap_reg_range(0x000, 0x400 - 4),
2220 	regmap_reg_range(0x700, 0x800 - 4),
2272 	INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2273 	INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2274 	INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2275 	INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2276 	INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2277 	INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2278 	INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2279 	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2280 	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2281 	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2282 	INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2283 	INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2284 	INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2285 	INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2286 	INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2287 	INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2288 	INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2289 	INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2290 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2291 	INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2292 	INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2293 	INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2294 	INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2302 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2304 	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
2306 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2307 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2308 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2309 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2310 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2312 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2314 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2315 static const char *x1500_cim_groups[] = { "cim-data", };
2331 	INGENIC_PIN_FUNCTION("i2s", x1500_i2s),
2436 	INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2437 	INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2438 	INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2439 	INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2440 	INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2441 	INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2442 	INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2443 	INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2444 	INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2445 	INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2446 	INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2447 	INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2448 	INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2449 	INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2450 	INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2451 	INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2452 	INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2453 	INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2454 	INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2455 	INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2456 	INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2457 	INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2458 	INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2459 	INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2460 	INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2461 	INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2462 	INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2463 	INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2464 	INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2465 	INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2466 	INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2467 	INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2468 	INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2469 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2470 	INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2471 	INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2472 	INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2473 	INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2474 	INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2475 	INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2476 	INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2477 	INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2478 	INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2479 	INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2480 	INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2481 	INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2482 	INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2483 	INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2484 	INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2485 	INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2486 	INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2487 	INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2488 	INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2489 	INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2490 	INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2491 	INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2492 	INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2493 	INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2497 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2498 static const char *x1830_uart1_groups[] = { "uart1-data", };
2499 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2501 	"ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2504 	"ssi1-dt-c", "ssi1-dt-d",
2505 	"ssi1-dr-c", "ssi1-dr-d",
2506 	"ssi1-clk-c", "ssi1-clk-d",
2507 	"ssi1-gpc-c", "ssi1-gpc-d",
2508 	"ssi1-ce0-c", "ssi1-ce0-d",
2509 	"ssi1-ce1-c", "ssi1-ce1-d",
2511 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2512 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2513 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2514 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2515 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2517 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2519 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2521 	"lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2523 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2524 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2525 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2526 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2527 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2528 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2529 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2530 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2544 	INGENIC_PIN_FUNCTION("i2s", x1830_i2s),
2559 	regmap_reg_range(0x0000, 0x4000 - 4),
2560 	regmap_reg_range(0x7000, 0x8000 - 4),
2757 	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2758 	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2759 	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
2760 	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
2761 	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
2762 	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
2763 	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
2764 	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
2765 	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
2766 	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
2767 	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
2768 	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
2769 	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
2770 	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
2771 	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
2772 	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
2773 	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
2774 	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
2775 	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
2776 	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
2777 	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
2778 	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
2779 	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
2780 	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
2781 	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
2782 	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
2783 	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
2784 	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
2785 	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
2786 	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
2787 	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
2788 	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
2789 	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
2790 	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
2791 	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
2792 	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
2793 	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
2794 	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
2795 	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
2796 	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
2797 	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
2798 	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
2799 	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
2800 	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
2801 	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
2802 	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
2803 	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
2804 	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
2805 	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
2806 	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
2807 	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
2808 	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
2809 	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
2810 	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
2811 	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
2812 	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
2813 	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
2814 	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
2815 	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
2816 	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
2817 	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
2818 	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
2819 	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
2820 	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
2821 	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
2822 	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
2823 	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
2824 	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
2825 	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
2826 	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
2827 	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
2828 	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
2829 	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
2830 	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
2831 	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
2832 	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
2833 	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
2834 	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
2835 	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
2836 	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
2837 	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
2838 	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
2839 	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
2840 	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
2841 	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
2842 	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
2843 	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
2844 	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
2845 	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
2846 	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
2847 	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
2848 	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
2849 	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
2850 	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
2851 	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
2852 	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
2853 	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
2855 	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
2856 	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
2857 	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
2858 	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
2859 	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
2860 	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
2861 	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
2862 	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
2863 	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
2864 	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
2865 	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
2866 	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
2867 	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
2868 	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
2869 	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
2870 	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
2871 	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
2872 	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
2873 	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
2874 	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
2875 	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
2876 	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
2877 	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
2886 	INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
2887 	INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
2888 	INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
2889 	INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
2890 	INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
2893 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2894 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2895 static const char *x2000_uart2_groups[] = { "uart2-data", };
2897 	"uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
2900 	"uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
2902 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
2903 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
2904 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
2905 static const char *x2000_uart8_groups[] = { "uart8-data", };
2906 static const char *x2000_uart9_groups[] = { "uart9-data", };
2908 	"sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
2909 	"sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
2912 	"ssi0-dt-b", "ssi0-dt-d",
2913 	"ssi0-dr-b", "ssi0-dr-d",
2914 	"ssi0-clk-b", "ssi0-clk-d",
2915 	"ssi0-ce-b", "ssi0-ce-d",
2918 	"ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
2919 	"ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
2920 	"ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
2921 	"ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
2923 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
2924 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2925 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
2927 	"emc-8bit-data", "emc-16bit-data",
2928 	"emc-addr", "emc-rd-we", "emc-wait",
2930 static const char *x2000_cs1_groups[] = { "emc-cs1", };
2931 static const char *x2000_cs2_groups[] = { "emc-cs2", };
2932 static const char *x2000_i2c0_groups[] = { "i2c0-data", };
2933 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
2934 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
2935 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
2936 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
2937 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
2939 	"i2s1-data-tx", "i2s1-data-rx",
2940 	"i2s1-clk-tx", "i2s1-clk-rx",
2941 	"i2s1-sysclk-tx", "i2s1-sysclk-rx",
2944 	"i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
2945 	"i2s2-clk-rx", "i2s2-sysclk-rx",
2948 	"i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
2949 	"i2s3-clk-tx", "i2s3-sysclk-tx",
2952 	"dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
2954 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
2956 	"lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
2957 	"lcd-slcd-8bit", "lcd-slcd-16bit",
2959 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
2960 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
2961 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
2962 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
2963 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
2964 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
2965 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
2966 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
2975 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
2976 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
2977 static const char *x2000_otg_groups[] = { "otg-vbus", };
2997 	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
2998 	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3033 	regmap_reg_range(0x000, 0x500 - 4),
3034 	regmap_reg_range(0x700, 0x800 - 4),
3069 	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3070 	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3071 	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3072 	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3073 	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3074 	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3075 	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3076 	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3077 	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3078 	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3079 	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3080 	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3081 	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3082 	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3083 	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3084 	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3085 	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3086 	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3087 	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3088 	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3089 	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3090 	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3091 	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3092 	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3093 	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3094 	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3095 	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3096 	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3097 	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3098 	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3099 	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3100 	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3101 	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3102 	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3103 	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3104 	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3105 	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3106 	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3107 	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3108 	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3109 	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3110 	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3111 	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3112 	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3113 	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3114 	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3115 	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3116 	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3117 	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3118 	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3119 	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3120 	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3121 	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3122 	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3123 	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3124 	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3125 	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3126 	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3127 	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3128 	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3129 	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3130 	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3131 	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3132 	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3133 	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3134 	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3135 	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3136 	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3137 	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3138 	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3139 	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3140 	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3141 	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3142 	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3143 	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3144 	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3145 	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3146 	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3147 	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3148 	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3149 	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3150 	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3151 	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3152 	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3153 	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3154 	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3155 	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3156 	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3157 	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3158 	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3159 	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3160 	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3161 	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3162 	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3163 	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3164 	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3165 	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3167 	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3168 	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3169 	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3170 	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3171 	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3172 	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3173 	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3174 	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3175 	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3176 	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3177 	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3178 	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3179 	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3180 	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3181 	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3182 	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3183 	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3184 	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3185 	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3186 	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3187 	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3188 	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3189 	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3221 	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
3222 	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3271 	regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);  in ingenic_gpio_read_reg()
3279 	if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {  in ingenic_gpio_set_bit()
3280 		regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,  in ingenic_gpio_set_bit()
3290 	regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));  in ingenic_gpio_set_bit()
3301 	regmap_write(jzgc->jzpc->map, REG_PZ_BASE(  in ingenic_gpio_shadow_set_bit()
3302 			jzgc->jzpc->info->reg_offset) + reg, BIT(offset));  in ingenic_gpio_shadow_set_bit()
3307 	regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(  in ingenic_gpio_shadow_set_bit_load()
3308 			jzgc->jzpc->info->reg_offset),  in ingenic_gpio_shadow_set_bit_load()
3309 			jzgc->gc.base / PINS_PER_GPIO_CHIP);  in ingenic_gpio_shadow_set_bit_load()
3316 	 * JZ4730 function and IRQ registers support two-bits-per-pin  in jz4730_gpio_set_bits()
3323 	regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));  in jz4730_gpio_set_bits()
3337 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_set_value()
3339 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_set_value()
3374 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {  in irq_set_type()
3377 	} else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {  in irq_set_type()
3387 	if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {  in irq_set_type()
3392 	} else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {  in irq_set_type()
3408 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_mask()
3420 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_unmask()
3434 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_enable()
3436 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_enable()
3452 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_disable()
3454 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_disable()
3470 	    !is_soc_or_above(jzgc->jzpc, ID_X2000)) {  in ingenic_gpio_irq_ack()
3482 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_ack()
3484 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_ack()
3510 	if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {  in ingenic_gpio_irq_set_type()
3513 		 * best we can do is to set up a single-edge interrupt and then  in ingenic_gpio_irq_set_type()
3530 	return irq_set_irq_wake(jzgc->irq, on);  in ingenic_gpio_irq_set_wake()
3537 	struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);  in ingenic_gpio_irq_handler()
3542 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_handler()
3544 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_handler()
3550 		generic_handle_domain_irq(gc->irq.domain, i);  in ingenic_gpio_irq_handler()
3584 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3587 			regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3591 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3594 			regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3604 	regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +  in ingenic_shadow_config_pin()
3611 	regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),  in ingenic_shadow_config_pin_load()
3619 	 * JZ4730 function and IRQ registers support two-bits-per-pin  in jz4730_config_pin_function()
3627 	regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,  in jz4730_config_pin_function()
3638 	regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);  in ingenic_get_pin_config()
3646 	struct ingenic_pinctrl *jzpc = jzgc->jzpc;  in ingenic_gpio_get_direction()
3647 	unsigned int pin = gc->base + offset;  in ingenic_gpio_get_direction()
3702 	seq_printf(p, "%s", gpio_chip->label);  in ingenic_gpio_irq_print_chip()
3725 	dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",  in ingenic_pinmux_set_pin_fn()
3763 		return -EINVAL;  in ingenic_pinmux_set_mux()
3767 		return -EINVAL;  in ingenic_pinmux_set_mux()
3769 	dev_dbg(pctldev->dev, "enable function %s group %s\n",  in ingenic_pinmux_set_mux()
3770 		func->func.name, grp->grp.name);  in ingenic_pinmux_set_mux()
3772 	mode = (uintptr_t)grp->data;  in ingenic_pinmux_set_mux()
3774 		for (i = 0; i < grp->grp.npins; i++)  in ingenic_pinmux_set_mux()
3775 			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode);  in ingenic_pinmux_set_mux()
3777 		pin_modes = grp->data;  in ingenic_pinmux_set_mux()
3779 		for (i = 0; i < grp->grp.npins; i++)  in ingenic_pinmux_set_mux()
3780 			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]);  in ingenic_pinmux_set_mux()
3794 	dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",  in ingenic_pinmux_gpio_set_direction()
3841 				(jzpc->info->pull_ups[offt] & BIT(idx));  in ingenic_pinconf_get()
3844 				(jzpc->info->pull_downs[offt] & BIT(idx));  in ingenic_pinconf_get()
3851 			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_pinconf_get()
3854 			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_pinconf_get()
3859 		pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));  in ingenic_pinconf_get()
3860 		pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));  in ingenic_pinconf_get()
3870 		pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));  in ingenic_pinconf_get()
3871 		pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));  in ingenic_pinconf_get()
3877 			return -EINVAL;  in ingenic_pinconf_get()
3883 			return -EINVAL;  in ingenic_pinconf_get()
3889 			return -EINVAL;  in ingenic_pinconf_get()
3899 			return -EINVAL;  in ingenic_pinconf_get()
3910 			return -EINVAL;  in ingenic_pinconf_get()
3916 		return -ENOTSUPP;  in ingenic_pinconf_get()
3951 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
3953 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
3956 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
3958 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
4019 			return -ENOTSUPP;  in ingenic_pinconf_set()
4028 			dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",  in ingenic_pinconf_set()
4034 			if (!(jzpc->info->pull_ups[offt] & BIT(idx)))  in ingenic_pinconf_set()
4035 				return -EINVAL;  in ingenic_pinconf_set()
4036 			dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",  in ingenic_pinconf_set()
4042 			if (!(jzpc->info->pull_downs[offt] & BIT(idx)))  in ingenic_pinconf_set()
4043 				return -EINVAL;  in ingenic_pinconf_set()
4044 			dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",  in ingenic_pinconf_set()
4051 				return -EINVAL;  in ingenic_pinconf_set()
4057 			ret = pinctrl_gpio_direction_output(jzpc->gc,  in ingenic_pinconf_set()
4058 							pin - jzpc->gc->base);  in ingenic_pinconf_set()
4067 				return -EINVAL;  in ingenic_pinconf_set()
4094 			return -ENOTSUPP;  in ingenic_pinconf_group_get()
4098 			return -ENOTSUPP;  in ingenic_pinconf_group_get()
4143 	{ .compatible = "ingenic,jz4730-gpio" },
4144 	{ .compatible = "ingenic,jz4740-gpio" },
4145 	{ .compatible = "ingenic,jz4725b-gpio" },
4146 	{ .compatible = "ingenic,jz4750-gpio" },
4147 	{ .compatible = "ingenic,jz4755-gpio" },
4148 	{ .compatible = "ingenic,jz4760-gpio" },
4149 	{ .compatible = "ingenic,jz4770-gpio" },
4150 	{ .compatible = "ingenic,jz4775-gpio" },
4151 	{ .compatible = "ingenic,jz4780-gpio" },
4152 	{ .compatible = "ingenic,x1000-gpio" },
4153 	{ .compatible = "ingenic,x1830-gpio" },
4154 	{ .compatible = "ingenic,x2000-gpio" },
4155 	{ .compatible = "ingenic,x2100-gpio" },
4163 	struct device *dev = jzpc->dev;  in ingenic_gpio_probe()
4176 		return -ENOMEM;  in ingenic_gpio_probe()
4178 	jzpc->gc = &jzgc->gc;  in ingenic_gpio_probe()
4180 	jzgc->jzpc = jzpc;  in ingenic_gpio_probe()
4181 	jzgc->reg_base = bank * jzpc->info->reg_offset;  in ingenic_gpio_probe()
4183 	jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);  in ingenic_gpio_probe()
4184 	if (!jzgc->gc.label)  in ingenic_gpio_probe()
4185 		return -ENOMEM;  in ingenic_gpio_probe()
4191 	jzgc->gc.base = bank * 32;  in ingenic_gpio_probe()
4193 	jzgc->gc.ngpio = 32;  in ingenic_gpio_probe()
4194 	jzgc->gc.parent = dev;  in ingenic_gpio_probe()
4195 	jzgc->gc.fwnode = fwnode;  in ingenic_gpio_probe()
4196 	jzgc->gc.owner = THIS_MODULE;  in ingenic_gpio_probe()
4198 	jzgc->gc.set = ingenic_gpio_set;  in ingenic_gpio_probe()
4199 	jzgc->gc.get = ingenic_gpio_get;  in ingenic_gpio_probe()
4200 	jzgc->gc.direction_input = pinctrl_gpio_direction_input;  in ingenic_gpio_probe()
4201 	jzgc->gc.direction_output = ingenic_gpio_direction_output;  in ingenic_gpio_probe()
4202 	jzgc->gc.get_direction = ingenic_gpio_get_direction;  in ingenic_gpio_probe()
4203 	jzgc->gc.request = gpiochip_generic_request;  in ingenic_gpio_probe()
4204 	jzgc->gc.free = gpiochip_generic_free;  in ingenic_gpio_probe()
4210 		return -EINVAL;  in ingenic_gpio_probe()
4211 	jzgc->irq = err;  in ingenic_gpio_probe()
4213 	girq = &jzgc->gc.irq;  in ingenic_gpio_probe()
4215 	girq->parent_handler = ingenic_gpio_irq_handler;  in ingenic_gpio_probe()
4216 	girq->num_parents = 1;  in ingenic_gpio_probe()
4217 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),  in ingenic_gpio_probe()
4219 	if (!girq->parents)  in ingenic_gpio_probe()
4220 		return -ENOMEM;  in ingenic_gpio_probe()
4222 	girq->parents[0] = jzgc->irq;  in ingenic_gpio_probe()
4223 	girq->default_type = IRQ_TYPE_NONE;  in ingenic_gpio_probe()
4224 	girq->handler = handle_level_irq;  in ingenic_gpio_probe()
4226 	err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);  in ingenic_gpio_probe()
4235 	struct device *dev = &pdev->dev;  in ingenic_pinctrl_probe()
4248 		return -EINVAL;  in ingenic_pinctrl_probe()
4253 		return -ENOMEM;  in ingenic_pinctrl_probe()
4260 	if (chip_info->access_table) {  in ingenic_pinctrl_probe()
4261 		regmap_config.rd_table = chip_info->access_table;  in ingenic_pinctrl_probe()
4262 		regmap_config.wr_table = chip_info->access_table;  in ingenic_pinctrl_probe()
4264 		regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;  in ingenic_pinctrl_probe()
4267 	jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);  in ingenic_pinctrl_probe()
4268 	if (IS_ERR(jzpc->map)) {  in ingenic_pinctrl_probe()
4270 		return PTR_ERR(jzpc->map);  in ingenic_pinctrl_probe()
4273 	jzpc->dev = dev;  in ingenic_pinctrl_probe()
4274 	jzpc->info = chip_info;  in ingenic_pinctrl_probe()
4276 	pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);  in ingenic_pinctrl_probe()
4278 		return -ENOMEM;  in ingenic_pinctrl_probe()
4281 	pctl_desc->name = dev_name(dev);  in ingenic_pinctrl_probe()
4282 	pctl_desc->owner = THIS_MODULE;  in ingenic_pinctrl_probe()
4283 	pctl_desc->pctlops = &ingenic_pctlops;  in ingenic_pinctrl_probe()
4284 	pctl_desc->pmxops = &ingenic_pmxops;  in ingenic_pinctrl_probe()
4285 	pctl_desc->confops = &ingenic_confops;  in ingenic_pinctrl_probe()
4286 	pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;  in ingenic_pinctrl_probe()
4287 	pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,  in ingenic_pinctrl_probe()
4288 			pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);  in ingenic_pinctrl_probe()
4289 	if (!jzpc->pdesc)  in ingenic_pinctrl_probe()
4290 		return -ENOMEM;  in ingenic_pinctrl_probe()
4292 	for (i = 0; i < pctl_desc->npins; i++) {  in ingenic_pinctrl_probe()
4293 		jzpc->pdesc[i].number = i;  in ingenic_pinctrl_probe()
4294 		jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",  in ingenic_pinctrl_probe()
4299 	jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);  in ingenic_pinctrl_probe()
4300 	if (IS_ERR(jzpc->pctl)) {  in ingenic_pinctrl_probe()
4302 		return PTR_ERR(jzpc->pctl);  in ingenic_pinctrl_probe()
4305 	for (i = 0; i < chip_info->num_groups; i++) {  in ingenic_pinctrl_probe()
4306 		const struct group_desc *group = &chip_info->groups[i];  in ingenic_pinctrl_probe()
4307 		const struct pingroup *grp = &group->grp;  in ingenic_pinctrl_probe()
4309 		err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins,  in ingenic_pinctrl_probe()
4310 						group->data);  in ingenic_pinctrl_probe()
4312 			dev_err(dev, "Failed to register group %s\n", grp->name);  in ingenic_pinctrl_probe()
4317 	for (i = 0; i < chip_info->num_functions; i++) {  in ingenic_pinctrl_probe()
4318 		const struct function_desc *function = &chip_info->functions[i];  in ingenic_pinctrl_probe()
4319 		const struct pinfunction *func = &function->func;  in ingenic_pinctrl_probe()
4321 		err = pinmux_generic_add_function(jzpc->pctl, func->name,  in ingenic_pinctrl_probe()
4322 						  func->groups, func->ngroups,  in ingenic_pinctrl_probe()
4323 						  function->data);  in ingenic_pinctrl_probe()
4325 			dev_err(dev, "Failed to register function %s\n", func->name);  in ingenic_pinctrl_probe()
4330 	dev_set_drvdata(dev, jzpc->map);  in ingenic_pinctrl_probe()
4349 		.compatible = "ingenic,jz4730-pinctrl",
4353 		.compatible = "ingenic,jz4740-pinctrl",
4357 		.compatible = "ingenic,jz4725b-pinctrl",
4361 		.compatible = "ingenic,jz4750-pinctrl",
4365 		.compatible = "ingenic,jz4755-pinctrl",
4369 		.compatible = "ingenic,jz4760-pinctrl",
4373 		.compatible = "ingenic,jz4760b-pinctrl",
4377 		.compatible = "ingenic,jz4770-pinctrl",
4381 		.compatible = "ingenic,jz4775-pinctrl",
4385 		.compatible = "ingenic,jz4780-pinctrl",
4389 		.compatible = "ingenic,x1000-pinctrl",
4393 		.compatible = "ingenic,x1000e-pinctrl",
4397 		.compatible = "ingenic,x1500-pinctrl",
4401 		.compatible = "ingenic,x1830-pinctrl",
4405 		.compatible = "ingenic,x2000-pinctrl",
4409 		.compatible = "ingenic,x2000e-pinctrl",
4413 		.compatible = "ingenic,x2100-pinctrl",
4421 		.name = "pinctrl-ingenic",