Lines Matching +full:gemini +full:- +full:pci

2  * Driver for the Gemini pin controller
6 * This is a group-only pin controller.
19 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define DRIVER_NAME "pinctrl-gemini"
29 * struct gemini_pin_conf - information about configuring a pin
41 * struct gemini_pmx - state holder for the gemini pin controller
64 * struct gemini_pin_group - describes a Gemini pin group
67 * from the driver-local pin enumeration space
85 /* Some straight-forward control registers */
95 * This register controls all Gemini pad/pin multiplexing
98 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
101 * - For the bits named *_DISABLE, once you enable something, it cannot be
136 "PCI",
143 "PCI CLK",
165 PINCTRL_PIN(13, "A14 PCI GNT1 N"),
166 PINCTRL_PIN(14, "A15 PCI REQ9 N"),
167 PINCTRL_PIN(15, "A16 PCI REQ2 N"),
168 PINCTRL_PIN(16, "A17 PCI REQ3 N"),
169 PINCTRL_PIN(17, "A18 PCI AD31"),
184 PINCTRL_PIN(31, "B14 PCI GNT0 N"),
185 PINCTRL_PIN(32, "B15 PCI GNT3 N"),
186 PINCTRL_PIN(33, "B16 PCI REQ1 N"),
187 PINCTRL_PIN(34, "B17 PCI AD30"),
188 PINCTRL_PIN(35, "B18 PCI AD29"),
202 PINCTRL_PIN(48, "C13 PCI INT0 N"),
204 PINCTRL_PIN(50, "C15 PCI GNT2 N"),
205 PINCTRL_PIN(51, "C16 PCI AD28"),
206 PINCTRL_PIN(52, "C17 PCI AD27"),
207 PINCTRL_PIN(53, "C18 PCI AD26"),
221 PINCTRL_PIN(66, "D13 PCI INTC N"),
222 PINCTRL_PIN(67, "D14 PCI CLK"),
223 PINCTRL_PIN(68, "D15 PCI AD25"),
224 PINCTRL_PIN(69, "D16 PCI AD24"),
225 PINCTRL_PIN(70, "D17 PCI CBE3 N"),
226 PINCTRL_PIN(71, "D18 PCI AD23"),
239 PINCTRL_PIN(83, "E12 PCI INTA N"),
240 PINCTRL_PIN(84, "E13 PCI INTB N"),
242 PINCTRL_PIN(86, "E15 PCI AD22"),
243 PINCTRL_PIN(87, "E16 PCI AD21"),
244 PINCTRL_PIN(88, "E17 PCI AD20"),
245 PINCTRL_PIN(89, "E18 PCI AD19"),
260 PINCTRL_PIN(103, "F14 PCI AD18"),
261 PINCTRL_PIN(104, "F15 PCI AD17"),
262 PINCTRL_PIN(105, "F16 PCI AD16"),
263 PINCTRL_PIN(106, "F17 PCI CBE2 N"),
264 PINCTRL_PIN(107, "F18 PCI FRAME N"),
279 PINCTRL_PIN(121, "G14 PCI IRDY N"),
280 PINCTRL_PIN(122, "G15 PCI TRDY N"),
281 PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
282 PINCTRL_PIN(124, "G17 PCI STOP N"),
283 PINCTRL_PIN(125, "G18 PCI PAR"),
298 PINCTRL_PIN(139, "H14 PCI CBE1 N"),
299 PINCTRL_PIN(140, "H15 PCI AD15"),
300 PINCTRL_PIN(141, "H16 PCI AD14"),
301 PINCTRL_PIN(142, "H17 PCI AD13"),
302 PINCTRL_PIN(143, "H18 PCI AD12"),
317 PINCTRL_PIN(157, "J14 PCI AD11"),
318 PINCTRL_PIN(158, "J15 PCI AD10"),
319 PINCTRL_PIN(159, "J16 PCI AD9"),
320 PINCTRL_PIN(160, "J17 PCI AD8"),
321 PINCTRL_PIN(161, "J18 PCI CBE0 N"),
336 PINCTRL_PIN(175, "K14 PCI AD3"),
337 PINCTRL_PIN(176, "K15 PCI AD4"),
338 PINCTRL_PIN(177, "K16 PCI AD5"),
339 PINCTRL_PIN(178, "K17 PCI AD6"),
340 PINCTRL_PIN(179, "K18 PCI AD7"),
357 PINCTRL_PIN(195, "L16 PCI AD0"),
358 PINCTRL_PIN(196, "L17 PCI AD1"),
359 PINCTRL_PIN(197, "L18 PCI AD2"),
552 * PCI needs to be active at the same time.
612 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
620 * The parallel flash can be set up in a 26-bit address bus mode exposing
621 * A[0-15] (A[15] takes the place of ALE), but it has the
640 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
643 /* The GPIO0C (5-7) pins overlap with ICE */
649 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
670 /* The GPIO0L (26-29) pins overlap with parallel flash */
676 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
679 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
684 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
690 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
693 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
696 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
699 /* The GPIO2C (8-31) pins overlap with PCI */
1010 /* Conflict with PCI */
1035 PINCTRL_PIN(17, "A18 PCI INTA N"),
1036 PINCTRL_PIN(18, "A19 PCI INTB N"),
1037 PINCTRL_PIN(19, "A20 PCI INTC N"),
1058 PINCTRL_PIN(39, "B20 PCI GNT0 N"),
1078 PINCTRL_PIN(58, "C19 PCI GNT1 N"),
1079 PINCTRL_PIN(59, "C20 PCI REQ2 N"),
1099 PINCTRL_PIN(78, "D19 PCI REQ1 N"),
1100 PINCTRL_PIN(79, "D20 PCI REQ3 N"),
1118 PINCTRL_PIN(96, "E17 PCI INTD N"),
1119 PINCTRL_PIN(97, "E18 PCI GNT3 N"),
1120 PINCTRL_PIN(98, "E19 PCI AD29"),
1121 PINCTRL_PIN(99, "E20 PCI AD28"),
1138 PINCTRL_PIN(115, "F16 PCI CLK"),
1139 PINCTRL_PIN(116, "F17 PCI GNT2 N"),
1140 PINCTRL_PIN(117, "F18 PCI AD31"),
1141 PINCTRL_PIN(118, "F19 PCI AD26"),
1142 PINCTRL_PIN(119, "F20 PCI CBE3 N"),
1159 PINCTRL_PIN(135, "G16 PCI REQ0 N"),
1160 PINCTRL_PIN(136, "G17 PCI AD30"),
1161 PINCTRL_PIN(137, "G18 PCI AD24"),
1162 PINCTRL_PIN(138, "G19 PCI AD23"),
1163 PINCTRL_PIN(139, "G20 PCI AD21"),
1180 PINCTRL_PIN(155, "H16 PCI AD27"),
1181 PINCTRL_PIN(156, "H17 PCI AD25"),
1182 PINCTRL_PIN(157, "H18 PCI AD22"),
1183 PINCTRL_PIN(158, "H19 PCI AD18"),
1184 PINCTRL_PIN(159, "H20 PCI AD17"),
1201 PINCTRL_PIN(175, "J16 PCI AD19"),
1202 PINCTRL_PIN(176, "J17 PCI AD20"),
1203 PINCTRL_PIN(177, "J18 PCI AD16"),
1204 PINCTRL_PIN(178, "J19 PCI CBE2 N"),
1205 PINCTRL_PIN(179, "J20 PCI FRAME N"),
1222 PINCTRL_PIN(195, "K16 PCI TRDY N"),
1223 PINCTRL_PIN(196, "K17 PCI IRDY N"),
1224 PINCTRL_PIN(197, "K18 PCI DEVSEL N"),
1225 PINCTRL_PIN(198, "K19 PCI STOP N"),
1226 PINCTRL_PIN(199, "K20 PCI PAR"),
1243 PINCTRL_PIN(215, "L16 PCI AD12"),
1244 PINCTRL_PIN(216, "L17 PCI AD13"),
1245 PINCTRL_PIN(217, "L18 PCI AD14"),
1246 PINCTRL_PIN(218, "L19 PCI AD15"),
1247 PINCTRL_PIN(219, "L20 PCI CBE1 N"),
1264 PINCTRL_PIN(235, "M16 PCI AD7"),
1265 PINCTRL_PIN(236, "M17 PCI AD6"),
1266 PINCTRL_PIN(237, "M18 PCI AD9"),
1267 PINCTRL_PIN(238, "M19 PCI AD10"),
1268 PINCTRL_PIN(239, "M20 PCI AD11"),
1285 PINCTRL_PIN(255, "N16 PCI CLKRUN N"),
1286 PINCTRL_PIN(256, "N17 PCI AD0"),
1287 PINCTRL_PIN(257, "N18 PCI AD4"),
1288 PINCTRL_PIN(258, "N19 PCI CBE0 N"),
1289 PINCTRL_PIN(259, "N20 PCI AD8"),
1308 PINCTRL_PIN(277, "P18 PCI AD1"),
1309 PINCTRL_PIN(278, "P19 PCI AD3"),
1310 PINCTRL_PIN(279, "P20 PCI AD5"),
1331 PINCTRL_PIN(299, "R20 PCI AD2"),
1501 * PCI needs to be active at the same time.
1561 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1569 * The parallel flash can be set up in a 26-bit address bus mode exposing
1570 * A[0-15] (A[15] takes the place of ALE), but it has the
1586 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1589 /* The GPIO0B (5-7) pins overlap with ICE */
1592 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1604 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1622 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1625 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1628 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1634 /* The GPIO1D (28-31) pins overlap with TVC */
1637 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1640 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1643 /* The GPIO2C (8-31) pins overlap with PCI */
1953 /* Conflict with PCI */
1962 if (pmx->is_3512) in gemini_get_groups_count()
1964 if (pmx->is_3516) in gemini_get_groups_count()
1974 if (pmx->is_3512) in gemini_get_group_name()
1976 if (pmx->is_3516) in gemini_get_group_name()
1989 if (pmx->flash_pin && in gemini_get_group_pins()
1990 pmx->is_3512 && in gemini_get_group_pins()
1996 if (pmx->flash_pin && in gemini_get_group_pins()
1997 pmx->is_3516 && in gemini_get_group_pins()
2003 if (pmx->is_3512) { in gemini_get_group_pins()
2007 if (pmx->is_3516) { in gemini_get_group_pins()
2030 * struct gemini_pmx_func - describes Gemini pinmux functions
2127 .name = "pci",
2203 if (pmx->is_3512) in gemini_pmx_set_mux()
2205 else if (pmx->is_3516) in gemini_pmx_set_mux()
2208 dev_err(pmx->dev, "invalid SoC type\n"); in gemini_pmx_set_mux()
2209 return -ENODEV; in gemini_pmx_set_mux()
2212 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2214 func->name, grp->name); in gemini_pmx_set_mux()
2216 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); in gemini_pmx_set_mux()
2217 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, in gemini_pmx_set_mux()
2218 grp->mask | grp->value, in gemini_pmx_set_mux()
2219 grp->value); in gemini_pmx_set_mux()
2220 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); in gemini_pmx_set_mux()
2225 expected = before &= ~grp->mask; in gemini_pmx_set_mux()
2226 expected |= grp->value; in gemini_pmx_set_mux()
2230 tmp = grp->mask; in gemini_pmx_set_mux()
2236 dev_err(pmx->dev, in gemini_pmx_set_mux()
2241 dev_err(pmx->dev, in gemini_pmx_set_mux()
2245 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2252 tmp = grp->value; in gemini_pmx_set_mux()
2258 dev_err(pmx->dev, in gemini_pmx_set_mux()
2263 dev_err(pmx->dev, in gemini_pmx_set_mux()
2267 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2371 for (i = 0; i < pmx->nconfs; i++) { in gemini_get_pin_conf()
2372 retconf = &pmx->confs[i]; in gemini_get_pin_conf()
2373 if (retconf->pin == pin) in gemini_get_pin_conf()
2391 return -ENOTSUPP; in gemini_pinconf_get()
2392 regmap_read(pmx->map, conf->reg, &val); in gemini_pinconf_get()
2393 val &= conf->mask; in gemini_pinconf_get()
2394 val >>= (ffs(conf->mask) - 1); in gemini_pinconf_get()
2398 return -ENOTSUPP; in gemini_pinconf_get()
2421 return -EINVAL; in gemini_pinconf_set()
2424 dev_err(pmx->dev, in gemini_pinconf_set()
2426 return -ENOTSUPP; in gemini_pinconf_set()
2428 arg <<= (ffs(conf->mask) - 1); in gemini_pinconf_set()
2429 dev_dbg(pmx->dev, in gemini_pinconf_set()
2431 pin, conf->mask, arg); in gemini_pinconf_set()
2432 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); in gemini_pinconf_set()
2435 dev_err(pmx->dev, "Invalid config param %04x\n", param); in gemini_pinconf_set()
2436 return -ENOTSUPP; in gemini_pinconf_set()
2455 if (pmx->is_3512) in gemini_pinconf_group_set()
2457 if (pmx->is_3516) in gemini_pinconf_group_set()
2461 if (!grp->driving_mask) { in gemini_pinconf_group_set()
2462 dev_err(pmx->dev, "pin config group \"%s\" does " in gemini_pinconf_group_set()
2464 grp->name); in gemini_pinconf_group_set()
2465 return -EINVAL; in gemini_pinconf_group_set()
2488 dev_err(pmx->dev, in gemini_pinconf_group_set()
2491 return -ENOTSUPP; in gemini_pinconf_group_set()
2493 val <<= (ffs(grp->driving_mask) - 1); in gemini_pinconf_group_set()
2494 regmap_update_bits(pmx->map, GLOBAL_IODRIVE, in gemini_pinconf_group_set()
2495 grp->driving_mask, in gemini_pinconf_group_set()
2497 dev_dbg(pmx->dev, in gemini_pinconf_group_set()
2499 grp->name, arg, grp->driving_mask, val); in gemini_pinconf_group_set()
2502 dev_err(pmx->dev, "invalid config param %04x\n", param); in gemini_pinconf_group_set()
2503 return -ENOTSUPP; in gemini_pinconf_group_set()
2529 struct device *dev = &pdev->dev; in gemini_pmx_probe()
2537 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in gemini_pmx_probe()
2539 return -ENOMEM; in gemini_pmx_probe()
2541 pmx->dev = &pdev->dev; in gemini_pmx_probe()
2542 parent = dev->parent; in gemini_pmx_probe()
2545 return -ENODEV; in gemini_pmx_probe()
2547 map = syscon_node_to_regmap(parent->of_node); in gemini_pmx_probe()
2552 pmx->map = map; in gemini_pmx_probe()
2563 pmx->is_3512 = true; in gemini_pmx_probe()
2564 pmx->confs = gemini_confs_3512; in gemini_pmx_probe()
2565 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); in gemini_pmx_probe()
2570 pmx->is_3516 = true; in gemini_pmx_probe()
2571 pmx->confs = gemini_confs_3516; in gemini_pmx_probe()
2572 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); in gemini_pmx_probe()
2578 return -ENODEV; in gemini_pmx_probe()
2596 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); in gemini_pmx_probe()
2597 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); in gemini_pmx_probe()
2599 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); in gemini_pmx_probe()
2600 if (IS_ERR(pmx->pctl)) { in gemini_pmx_probe()
2602 return PTR_ERR(pmx->pctl); in gemini_pmx_probe()
2605 dev_info(dev, "initialized Gemini pin control driver\n"); in gemini_pmx_probe()
2611 { .compatible = "cortina,gemini-pinctrl" },