Lines Matching +full:pin +full:- +full:val
1 // SPDX-License-Identifier: GPL-2.0-only
5 * The registers are located in a syscon region called OLB. There are two pin
7 * pull-down, pull-up, drive strength and muxing.
9 * For each pin, muxing is between two functions: (0) GPIO or (1) another one
10 * that is pin-dependent. Functions are declared statically in this driver.
13 * single pin, and its index/selector is the pin number.
15 * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
33 #include <linux/pinctrl/pinconf-generic.h>
39 #include "pinctrl-utils.h"
69 * Drive strength; two bits per pin.
74 * Comments to the right of each pin are the "signal name" in the datasheet.
203 u32 mask, u32 val) in eq5p_update_bits() argument
205 void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg]; in eq5p_update_bits()
207 writel((readl(ptr) & ~mask) | (val & mask), ptr); in eq5p_update_bits()
213 u32 val = readl(pctrl->base + eq5p_regs[bank][reg]); in eq5p_test_bit() local
218 return (val & BIT(offset)) != 0; in eq5p_test_bit()
221 static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin) in eq5p_pin_to_bank() argument
223 if (pin < EQ5P_PIN_OFFSET_BANK_B) in eq5p_pin_to_bank()
229 static unsigned int eq5p_pin_to_offset(unsigned int pin) in eq5p_pin_to_offset() argument
231 if (pin < EQ5P_PIN_OFFSET_BANK_B) in eq5p_pin_to_offset()
232 return pin; in eq5p_pin_to_offset()
234 return pin - EQ5P_PIN_OFFSET_BANK_B; in eq5p_pin_to_offset()
245 return pctldev->desc->pins[selector].name; in eq5p_pinctrl_get_group_name()
253 *pins = &pctldev->desc->pins[selector].number; in eq5p_pinctrl_get_group_pins()
258 static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, in eq5p_pinconf_get() argument
263 unsigned int offset = eq5p_pin_to_offset(pin); in eq5p_pinconf_get()
264 enum eq5p_bank bank = eq5p_pin_to_bank(pin); in eq5p_pinconf_get()
282 offset *= 2; /* two bits per pin */ in eq5p_pinconf_get()
284 val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]); in eq5p_pinconf_get()
285 offset -= 32; in eq5p_pinconf_get()
287 val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]); in eq5p_pinconf_get()
292 return -ENOTSUPP; in eq5p_pinconf_get()
301 unsigned int pin) in eq5p_pinctrl_pin_dbg_show() argument
304 const char *pin_name = pctrl->desc.pins[pin].name; in eq5p_pinctrl_pin_dbg_show()
305 unsigned int offset = eq5p_pin_to_offset(pin); in eq5p_pinctrl_pin_dbg_show()
306 enum eq5p_bank bank = eq5p_pin_to_bank(pin); in eq5p_pinctrl_pin_dbg_show()
338 * We have not found the function attached to this pin, this in eq5p_pinctrl_pin_dbg_show()
361 eq5p_pinconf_get(pctldev, pin, &ds_config); in eq5p_pinctrl_pin_dbg_show()
399 unsigned int func_selector, unsigned int pin) in eq5p_pinmux_set_mux() argument
403 const char *group_name = pctldev->desc->pins[pin].name; in eq5p_pinmux_set_mux()
405 unsigned int offset = eq5p_pin_to_offset(pin); in eq5p_pinmux_set_mux()
406 enum eq5p_bank bank = eq5p_pin_to_bank(pin); in eq5p_pinmux_set_mux()
407 u32 mask, val; in eq5p_pinmux_set_mux() local
409 dev_dbg(pctldev->dev, "func=%s group=%s\n", func_name, group_name); in eq5p_pinmux_set_mux()
412 val = is_gpio ? 0 : mask; in eq5p_pinmux_set_mux()
413 eq5p_update_bits(pctrl, bank, EQ5P_IOCR, mask, val); in eq5p_pinmux_set_mux()
419 unsigned int pin) in eq5p_pinmux_gpio_request_enable() argument
421 /* Pin numbers and group selectors are the same thing in our case. */ in eq5p_pinmux_gpio_request_enable()
422 return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin); in eq5p_pinmux_gpio_request_enable()
435 unsigned int pin, u32 arg) in eq5p_pinconf_set_drive_strength() argument
438 unsigned int offset = eq5p_pin_to_offset(pin); in eq5p_pinconf_set_drive_strength()
439 enum eq5p_bank bank = eq5p_pin_to_bank(pin); in eq5p_pinconf_set_drive_strength()
441 u32 mask, val; in eq5p_pinconf_set_drive_strength() local
444 dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg); in eq5p_pinconf_set_drive_strength()
445 return -EINVAL; in eq5p_pinconf_set_drive_strength()
448 offset *= 2; /* two bits per pin */ in eq5p_pinconf_set_drive_strength()
452 offset -= 32; in eq5p_pinconf_set_drive_strength()
458 val = arg << offset; in eq5p_pinconf_set_drive_strength()
459 eq5p_update_bits(pctrl, bank, reg, mask, val); in eq5p_pinconf_set_drive_strength()
463 static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, in eq5p_pinconf_set() argument
467 const char *pin_name = pctldev->desc->pins[pin].name; in eq5p_pinconf_set()
468 unsigned int offset = eq5p_pin_to_offset(pin); in eq5p_pinconf_set()
469 enum eq5p_bank bank = eq5p_pin_to_bank(pin); in eq5p_pinconf_set()
470 struct device *dev = pctldev->dev; in eq5p_pinconf_set()
471 u32 val = BIT(offset); in eq5p_pinconf_set() local
480 dev_dbg(dev, "pin=%s bias_disable\n", pin_name); in eq5p_pinconf_set()
482 eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0); in eq5p_pinconf_set()
483 eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0); in eq5p_pinconf_set()
487 dev_dbg(dev, "pin=%s bias_pull_down arg=%u\n", in eq5p_pinconf_set()
491 return -ENOTSUPP; in eq5p_pinconf_set()
493 eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val); in eq5p_pinconf_set()
494 eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0); in eq5p_pinconf_set()
498 dev_dbg(dev, "pin=%s bias_pull_up arg=%u\n", in eq5p_pinconf_set()
502 return -ENOTSUPP; in eq5p_pinconf_set()
504 eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0); in eq5p_pinconf_set()
505 eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val); in eq5p_pinconf_set()
509 dev_dbg(dev, "pin=%s drive_strength arg=%u\n", in eq5p_pinconf_set()
512 eq5p_pinconf_set_drive_strength(pctldev, pin, arg); in eq5p_pinconf_set()
517 return -ENOTSUPP; in eq5p_pinconf_set()
536 struct device *dev = &adev->dev; in eq5p_probe()
543 return -ENOMEM; in eq5p_probe()
545 pctrl->base = (void __iomem *)dev_get_platdata(dev); in eq5p_probe()
546 pctrl->desc.name = dev_name(dev); in eq5p_probe()
547 pctrl->desc.pins = eq5p_pins; in eq5p_probe()
548 pctrl->desc.npins = ARRAY_SIZE(eq5p_pins); in eq5p_probe()
549 pctrl->desc.pctlops = &eq5p_pinctrl_ops; in eq5p_probe()
550 pctrl->desc.pmxops = &eq5p_pinmux_ops; in eq5p_probe()
551 pctrl->desc.confops = &eq5p_pinconf_ops; in eq5p_probe()
552 pctrl->desc.owner = THIS_MODULE; in eq5p_probe()
554 ret = devm_pinctrl_register_and_init(dev, &pctrl->desc, pctrl, &pctldev); in eq5p_probe()