Lines Matching +full:gpio +full:- +full:pin +full:- +full:ic
1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/gpio/driver.h>
11 #include <linux/pinctrl/pinconf-generic.h>
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT "io-%d"
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
45 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
47 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
49 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
59 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_ack_irq()
60 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); in eqbr_gpio_ack_irq()
61 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_ack_irq()
85 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_type_cfg()
86 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type); in eqbr_irq_type_cfg()
87 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type); in eqbr_irq_type_cfg()
88 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type); in eqbr_irq_type_cfg()
89 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_type_cfg()
138 return -EINVAL; in eqbr_gpio_set_irq_type()
154 struct irq_chip *ic = irq_desc_get_chip(desc); in eqbr_irq_handler() local
157 chained_irq_enter(ic, desc); in eqbr_irq_handler()
158 pins = readl(gctrl->membase + GPIO_IRNCR); in eqbr_irq_handler()
160 for_each_set_bit(offset, &pins, gc->ngpio) in eqbr_irq_handler()
161 generic_handle_domain_irq(gc->irq.domain, offset); in eqbr_irq_handler()
163 chained_irq_exit(ic, desc); in eqbr_irq_handler()
182 gc = &gctrl->chip; in gpiochip_setup()
183 gc->label = gctrl->name; in gpiochip_setup()
184 gc->fwnode = gctrl->fwnode; in gpiochip_setup()
185 gc->request = gpiochip_generic_request; in gpiochip_setup()
186 gc->free = gpiochip_generic_free; in gpiochip_setup()
188 if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) { in gpiochip_setup()
190 gctrl->name); in gpiochip_setup()
194 girq = &gctrl->chip.irq; in gpiochip_setup()
196 girq->parent_handler = eqbr_irq_handler; in gpiochip_setup()
197 girq->num_parents = 1; in gpiochip_setup()
198 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL); in gpiochip_setup()
199 if (!girq->parents) in gpiochip_setup()
200 return -ENOMEM; in gpiochip_setup()
202 girq->default_type = IRQ_TYPE_NONE; in gpiochip_setup()
203 girq->handler = handle_bad_irq; in gpiochip_setup()
204 girq->parents[0] = gctrl->virq; in gpiochip_setup()
211 struct device *dev = drvdata->dev; in gpiolib_reg()
217 for (i = 0; i < drvdata->nr_gpio_ctrls; i++) { in gpiolib_reg()
218 gctrl = drvdata->gpio_ctrls + i; in gpiolib_reg()
219 np = to_of_node(gctrl->fwnode); in gpiolib_reg()
221 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i); in gpiolib_reg()
222 if (!gctrl->name) in gpiolib_reg()
223 return -ENOMEM; in gpiolib_reg()
226 dev_err(dev, "Failed to get GPIO register address\n"); in gpiolib_reg()
227 return -ENXIO; in gpiolib_reg()
230 gctrl->membase = devm_ioremap_resource(dev, &res); in gpiolib_reg()
231 if (IS_ERR(gctrl->membase)) in gpiolib_reg()
232 return PTR_ERR(gctrl->membase); in gpiolib_reg()
234 gctrl->virq = irq_of_parse_and_map(np, 0); in gpiolib_reg()
235 if (!gctrl->virq) { in gpiolib_reg()
237 gctrl->name); in gpiolib_reg()
238 return -ENXIO; in gpiolib_reg()
240 raw_spin_lock_init(&gctrl->lock); in gpiolib_reg()
242 ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8, in gpiolib_reg()
243 gctrl->membase + GPIO_IN, in gpiolib_reg()
244 gctrl->membase + GPIO_OUTSET, in gpiolib_reg()
245 gctrl->membase + GPIO_OUTCLR, in gpiolib_reg()
246 gctrl->membase + GPIO_DIR, in gpiolib_reg()
249 dev_err(dev, "unable to init generic GPIO\n"); in gpiolib_reg()
257 ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl); in gpiolib_reg()
266 *find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin) in find_pinbank_via_pin() argument
271 for (i = 0; i < pctl->nr_banks; i++) { in find_pinbank_via_pin()
272 bank = &pctl->pin_banks[i]; in find_pinbank_via_pin()
273 if (pin >= bank->pin_base && in find_pinbank_via_pin()
274 (pin - bank->pin_base) < bank->nr_pins) in find_pinbank_via_pin()
290 unsigned int pmx, unsigned int pin) in eqbr_set_pin_mux() argument
297 bank = find_pinbank_via_pin(pctl, pin); in eqbr_set_pin_mux()
299 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); in eqbr_set_pin_mux()
300 return -ENODEV; in eqbr_set_pin_mux()
302 mem = bank->membase; in eqbr_set_pin_mux()
303 offset = pin - bank->pin_base; in eqbr_set_pin_mux()
305 if (!(bank->aval_pinmap & BIT(offset))) { in eqbr_set_pin_mux()
306 dev_err(pctl->dev, in eqbr_set_pin_mux()
307 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n", in eqbr_set_pin_mux()
308 pin, bank->pin_base, bank->aval_pinmap); in eqbr_set_pin_mux()
309 return -ENODEV; in eqbr_set_pin_mux()
312 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_set_pin_mux()
314 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_set_pin_mux()
329 return -EINVAL; in eqbr_pinmux_set_mux()
333 return -EINVAL; in eqbr_pinmux_set_mux()
335 pinmux = grp->data; in eqbr_pinmux_set_mux()
336 for (i = 0; i < grp->grp.npins; i++) in eqbr_pinmux_set_mux()
337 eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]); in eqbr_pinmux_set_mux()
344 unsigned int pin) in eqbr_pinmux_gpio_request() argument
348 return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin); in eqbr_pinmux_gpio_request()
362 unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/ in get_drv_cur()
374 for (i = 0; i < pctl->nr_gpio_ctrls; i++) { in get_gpio_ctrls_via_bank()
375 if (pctl->gpio_ctrls[i].bank == bank) in get_gpio_ctrls_via_bank()
376 return &pctl->gpio_ctrls[i]; in get_gpio_ctrls_via_bank()
382 static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, in eqbr_pinconf_get() argument
394 bank = find_pinbank_via_pin(pctl, pin); in eqbr_pinconf_get()
396 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); in eqbr_pinconf_get()
397 return -ENODEV; in eqbr_pinconf_get()
399 mem = bank->membase; in eqbr_pinconf_get()
400 offset = pin - bank->pin_base; in eqbr_pinconf_get()
402 if (!(bank->aval_pinmap & BIT(offset))) { in eqbr_pinconf_get()
403 dev_err(pctl->dev, in eqbr_pinconf_get()
404 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n", in eqbr_pinconf_get()
405 pin, bank->pin_base, bank->aval_pinmap); in eqbr_pinconf_get()
406 return -ENODEV; in eqbr_pinconf_get()
409 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_pinconf_get()
429 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", in eqbr_pinconf_get()
430 bank->pin_base, pin); in eqbr_pinconf_get()
431 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
432 return -ENODEV; in eqbr_pinconf_get()
434 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset)); in eqbr_pinconf_get()
437 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
438 return -ENOTSUPP; in eqbr_pinconf_get()
440 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
446 static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, in eqbr_pinconf_set() argument
464 bank = find_pinbank_via_pin(pctl, pin); in eqbr_pinconf_set()
466 dev_err(pctl->dev, in eqbr_pinconf_set()
467 "Couldn't find pin bank for pin %u\n", pin); in eqbr_pinconf_set()
468 return -ENODEV; in eqbr_pinconf_set()
470 mem = bank->membase; in eqbr_pinconf_set()
471 offset = pin - bank->pin_base; in eqbr_pinconf_set()
498 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", in eqbr_pinconf_set()
499 bank->pin_base, pin); in eqbr_pinconf_set()
500 return -ENODEV; in eqbr_pinconf_set()
502 gc = &gctrl->chip; in eqbr_pinconf_set()
503 gc->direction_output(gc, offset, 0); in eqbr_pinconf_set()
506 return -ENOTSUPP; in eqbr_pinconf_set()
509 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_pinconf_set()
513 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_set()
532 return -ENOTSUPP; in eqbr_pinconf_group_get()
535 return -ENOTSUPP; in eqbr_pinconf_group_get()
592 struct device_node *node = dev->of_node; in funcs_utils()
608 (char *)prop->value); in funcs_utils()
634 groups[j] = prop->value; in funcs_utils()
639 return -EINVAL; in funcs_utils()
649 struct device *dev = drvdata->dev; in eqbr_build_functions()
660 return -ENOMEM; in eqbr_build_functions()
677 return -ENOMEM; in eqbr_build_functions()
690 ret = pinmux_generic_add_pinfunction(drvdata->pctl_dev, in eqbr_build_functions()
704 struct device *dev = drvdata->dev; in eqbr_build_groups()
705 struct device_node *node = dev->of_node; in eqbr_build_groups()
718 dev_err(dev, "No pins in the group: %s\n", prop->name); in eqbr_build_groups()
721 grp->npins = err; in eqbr_build_groups()
722 grp->name = prop->value; in eqbr_build_groups()
723 pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL); in eqbr_build_groups()
725 return -ENOMEM; in eqbr_build_groups()
727 grp->pins = pins; in eqbr_build_groups()
729 pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL); in eqbr_build_groups()
731 return -ENOMEM; in eqbr_build_groups()
733 for (j = 0; j < grp->npins; j++) { in eqbr_build_groups()
736 grp->name); in eqbr_build_groups()
737 return -EINVAL; in eqbr_build_groups()
739 if (pin_id >= drvdata->pctl_desc.npins) { in eqbr_build_groups()
740 dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n", in eqbr_build_groups()
741 grp->name, j, pin_id); in eqbr_build_groups()
742 return -EINVAL; in eqbr_build_groups()
747 grp->name); in eqbr_build_groups()
748 return -EINVAL; in eqbr_build_groups()
753 err = pinctrl_generic_add_group(drvdata->pctl_dev, in eqbr_build_groups()
754 grp->name, grp->pins, grp->npins, in eqbr_build_groups()
757 dev_err(dev, "Failed to register group %s\n", grp->name); in eqbr_build_groups()
776 dev = drvdata->dev; in pinctrl_reg()
777 pctl_desc = &drvdata->pctl_desc; in pinctrl_reg()
778 pctl_desc->name = "eqbr-pinctrl"; in pinctrl_reg()
779 pctl_desc->owner = THIS_MODULE; in pinctrl_reg()
780 pctl_desc->pctlops = &eqbr_pctl_ops; in pinctrl_reg()
781 pctl_desc->pmxops = &eqbr_pinmux_ops; in pinctrl_reg()
782 pctl_desc->confops = &eqbr_pinconf_ops; in pinctrl_reg()
783 raw_spin_lock_init(&drvdata->lock); in pinctrl_reg()
785 for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++) in pinctrl_reg()
786 nr_pins += drvdata->pin_banks[i].nr_pins; in pinctrl_reg()
790 return -ENOMEM; in pinctrl_reg()
793 return -ENOMEM; in pinctrl_reg()
801 pctl_desc->pins = pdesc; in pinctrl_reg()
802 pctl_desc->npins = nr_pins; in pinctrl_reg()
803 dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins); in pinctrl_reg()
806 &drvdata->pctl_dev); in pinctrl_reg()
822 return pinctrl_enable(drvdata->pctl_dev); in pinctrl_reg()
829 struct device *dev = drvdata->dev; in pinbank_init()
833 bank->membase = drvdata->membase + id * PAD_REG_OFF; in pinbank_init()
835 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec); in pinbank_init()
837 dev_err(dev, "gpio-range not available!\n"); in pinbank_init()
841 bank->pin_base = spec.args[1]; in pinbank_init()
842 bank->nr_pins = spec.args[2]; in pinbank_init()
844 bank->aval_pinmap = readl(bank->membase + REG_AVAIL); in pinbank_init()
845 bank->id = id; in pinbank_init()
847 dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n", in pinbank_init()
848 id, bank->membase, bank->pin_base, in pinbank_init()
849 bank->nr_pins, bank->aval_pinmap); in pinbank_init()
856 struct device *dev = drvdata->dev; in pinbank_probe()
862 /* Count gpio bank number */ in pinbank_probe()
864 for_each_node_by_name(np_gpio, "gpio") { in pinbank_probe()
870 dev_err(dev, "NO pin bank available!\n"); in pinbank_probe()
871 return -ENODEV; in pinbank_probe()
874 /* Count pin bank number and gpio controller number */ in pinbank_probe()
877 return -ENOMEM; in pinbank_probe()
881 return -ENOMEM; in pinbank_probe()
883 dev_dbg(dev, "found %d gpio controller!\n", nr_gpio); in pinbank_probe()
885 /* Initialize Pin bank */ in pinbank_probe()
887 for_each_node_by_name(np_gpio, "gpio") { in pinbank_probe()
898 drvdata->pin_banks = banks; in pinbank_probe()
899 drvdata->nr_banks = nr_gpio; in pinbank_probe()
900 drvdata->gpio_ctrls = gctrls; in pinbank_probe()
901 drvdata->nr_gpio_ctrls = nr_gpio; in pinbank_probe()
909 struct device *dev = &pdev->dev; in eqbr_pinctrl_probe()
914 return -ENOMEM; in eqbr_pinctrl_probe()
916 drvdata->dev = dev; in eqbr_pinctrl_probe()
918 drvdata->membase = devm_platform_ioremap_resource(pdev, 0); in eqbr_pinctrl_probe()
919 if (IS_ERR(drvdata->membase)) in eqbr_pinctrl_probe()
920 return PTR_ERR(drvdata->membase); in eqbr_pinctrl_probe()
939 { .compatible = "intel,lgm-io" },
947 .name = "eqbr-pinctrl",