Lines Matching +full:port +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0-only
3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
28 #include <linux/pinctrl/pinconf-generic.h>
41 /* Port Select configures the port */
44 /* Port settings, write PORTSEL first */
73 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
96 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
121 * Since first controller (gpio-sch.c) and second
122 * (gpio-dwapb.c) are at the fixed bases, we may safely
134 * struct cy8c95x0_pinctrl - driver data
139 * @irq_trig_raise: I/O bits affected by raising voltage level
140 * @irq_trig_fall: I/O bits affected by falling voltage level
141 * @irq_trig_low: I/O bits affected by a low voltage level
142 * @irq_trig_high: I/O bits affected by a high voltage level
332 * Only 12 registers are present per port (see Table 6 in the datasheet). in cy8c95x0_readable_register()
349 * Only 12 registers are present per port (see Table 6 in the datasheet). in cy8c95x0_writeable_register()
483 unsigned int reg, unsigned int port, in cy8c95x0_regmap_update_bits_base() argument
491 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); in cy8c95x0_regmap_update_bits_base()
493 /* Quick path direct access registers honor the port argument */ in cy8c95x0_regmap_update_bits_base()
495 off = reg + port; in cy8c95x0_regmap_update_bits_base()
499 guard(mutex)(&chip->i2c_lock); in cy8c95x0_regmap_update_bits_base()
501 ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force); in cy8c95x0_regmap_update_bits_base()
507 * Allows to mark the registers as non-volatile and reduces I/O cycles. in cy8c95x0_regmap_update_bits_base()
511 regcache_cache_only(chip->regmap, true); in cy8c95x0_regmap_update_bits_base()
516 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port); in cy8c95x0_regmap_update_bits_base()
517 regmap_clear_bits(chip->regmap, off, mask & val); in cy8c95x0_regmap_update_bits_base()
519 regcache_cache_only(chip->regmap, false); in cy8c95x0_regmap_update_bits_base()
526 * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache
530 * @port: The port to be used for muxed registers or quick path direct access
544 unsigned int port, unsigned int mask, unsigned int val) in cy8c95x0_regmap_write_bits() argument
546 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true); in cy8c95x0_regmap_write_bits()
550 * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache
554 * @port: The port to be used for muxed registers or quick path direct access
568 unsigned int port, unsigned int mask, unsigned int val) in cy8c95x0_regmap_update_bits() argument
570 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false); in cy8c95x0_regmap_update_bits()
574 * cy8c95x0_regmap_read_bits() - reads a register using the regmap cache
577 * @port: The port to be used for muxed registers or quick path direct access
591 unsigned int port, unsigned int mask, unsigned int *val) in cy8c95x0_regmap_read_bits() argument
599 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); in cy8c95x0_regmap_read_bits()
601 /* Quick path direct access registers honor the port argument */ in cy8c95x0_regmap_read_bits()
603 off = reg + port; in cy8c95x0_regmap_read_bits()
608 scoped_guard(mutex, &chip->i2c_lock) in cy8c95x0_regmap_read_bits()
609 ret = regmap_read(chip->regmap, off, &tmp); in cy8c95x0_regmap_read_bits()
627 bitmap_scatter(tmask, mask, chip->map, MAX_LINE); in cy8c95x0_write_regs_mask()
628 bitmap_scatter(tval, val, chip->map, MAX_LINE); in cy8c95x0_write_regs_mask()
630 for_each_set_clump8(offset, bits, tmask, chip->tpin) { in cy8c95x0_write_regs_mask()
637 dev_err(chip->dev, "failed writing register %d, port %u: err %d\n", reg, i, ret); in cy8c95x0_write_regs_mask()
655 bitmap_scatter(tmask, mask, chip->map, MAX_LINE); in cy8c95x0_read_regs_mask()
656 bitmap_scatter(tval, val, chip->map, MAX_LINE); in cy8c95x0_read_regs_mask()
658 for_each_set_clump8(offset, bits, tmask, chip->tpin) { in cy8c95x0_read_regs_mask()
663 dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret); in cy8c95x0_read_regs_mask()
672 bitmap_gather(val, tval, chip->map, MAX_LINE); in cy8c95x0_read_regs_mask()
679 u8 port = cypress_get_port(chip, pin); in cy8c95x0_pinmux_direction() local
683 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); in cy8c95x0_pinmux_direction()
689 * the direction register isn't sufficient in Push-Pull mode. in cy8c95x0_pinmux_direction()
691 if (input && test_bit(pin, chip->push_pull)) { in cy8c95x0_pinmux_direction()
692 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); in cy8c95x0_pinmux_direction()
696 __clear_bit(pin, chip->push_pull); in cy8c95x0_pinmux_direction()
711 u8 port = cypress_get_port(chip, off); in cy8c95x0_gpio_direction_output() local
715 /* Set output level */ in cy8c95x0_gpio_direction_output()
716 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); in cy8c95x0_gpio_direction_output()
726 u8 port = cypress_get_port(chip, off); in cy8c95x0_gpio_get_value() local
731 ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_INPUT, port, bit, ®_val); in cy8c95x0_gpio_get_value()
749 u8 port = cypress_get_port(chip, off); in cy8c95x0_gpio_set_value() local
752 cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); in cy8c95x0_gpio_set_value()
758 u8 port = cypress_get_port(chip, off); in cy8c95x0_gpio_get_direction() local
763 ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_DIRECTION, port, bit, ®_val); in cy8c95x0_gpio_get_direction()
778 u8 port = cypress_get_port(chip, off); in cy8c95x0_gpio_get_pincfg() local
832 return -ENOTSUPP; in cy8c95x0_gpio_get_pincfg()
838 ret = cy8c95x0_regmap_read_bits(chip, reg, port, bit, ®_val); in cy8c95x0_gpio_get_pincfg()
855 u8 port = cypress_get_port(chip, off); in cy8c95x0_gpio_set_pincfg() local
863 __clear_bit(off, chip->push_pull); in cy8c95x0_gpio_set_pincfg()
867 __clear_bit(off, chip->push_pull); in cy8c95x0_gpio_set_pincfg()
871 __clear_bit(off, chip->push_pull); in cy8c95x0_gpio_set_pincfg()
875 __clear_bit(off, chip->push_pull); in cy8c95x0_gpio_set_pincfg()
879 __clear_bit(off, chip->push_pull); in cy8c95x0_gpio_set_pincfg()
883 __set_bit(off, chip->push_pull); in cy8c95x0_gpio_set_pincfg()
894 return -ENOTSUPP; in cy8c95x0_gpio_set_pincfg()
900 return cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit); in cy8c95x0_gpio_set_pincfg()
922 struct device *dev = chip->dev; in cy8c95x0_add_pin_ranges()
925 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin); in cy8c95x0_add_pin_ranges()
934 struct gpio_chip *gc = &chip->gpio_chip; in cy8c95x0_setup_gpiochip()
936 gc->request = gpiochip_generic_request; in cy8c95x0_setup_gpiochip()
937 gc->free = gpiochip_generic_free; in cy8c95x0_setup_gpiochip()
938 gc->direction_input = cy8c95x0_gpio_direction_input; in cy8c95x0_setup_gpiochip()
939 gc->direction_output = cy8c95x0_gpio_direction_output; in cy8c95x0_setup_gpiochip()
940 gc->get = cy8c95x0_gpio_get_value; in cy8c95x0_setup_gpiochip()
941 gc->set = cy8c95x0_gpio_set_value; in cy8c95x0_setup_gpiochip()
942 gc->get_direction = cy8c95x0_gpio_get_direction; in cy8c95x0_setup_gpiochip()
943 gc->get_multiple = cy8c95x0_gpio_get_multiple; in cy8c95x0_setup_gpiochip()
944 gc->set_multiple = cy8c95x0_gpio_set_multiple; in cy8c95x0_setup_gpiochip()
945 gc->set_config = gpiochip_generic_config; in cy8c95x0_setup_gpiochip()
946 gc->can_sleep = true; in cy8c95x0_setup_gpiochip()
947 gc->add_pin_ranges = cy8c95x0_add_pin_ranges; in cy8c95x0_setup_gpiochip()
949 gc->base = -1; in cy8c95x0_setup_gpiochip()
950 gc->ngpio = chip->tpin; in cy8c95x0_setup_gpiochip()
952 gc->parent = chip->dev; in cy8c95x0_setup_gpiochip()
953 gc->owner = THIS_MODULE; in cy8c95x0_setup_gpiochip()
954 gc->names = NULL; in cy8c95x0_setup_gpiochip()
956 gc->label = dev_name(chip->dev); in cy8c95x0_setup_gpiochip()
958 return devm_gpiochip_add_data(chip->dev, gc, chip); in cy8c95x0_setup_gpiochip()
967 set_bit(hwirq, chip->irq_mask); in cy8c95x0_irq_mask()
978 clear_bit(hwirq, chip->irq_mask); in cy8c95x0_irq_unmask()
986 mutex_lock(&chip->irq_lock); in cy8c95x0_irq_bus_lock()
999 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones); in cy8c95x0_irq_bus_sync_unlock()
1002 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask); in cy8c95x0_irq_bus_sync_unlock()
1003 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE); in cy8c95x0_irq_bus_sync_unlock()
1009 mutex_unlock(&chip->irq_lock); in cy8c95x0_irq_bus_sync_unlock()
1032 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type); in cy8c95x0_irq_set_type()
1033 return -EINVAL; in cy8c95x0_irq_set_type()
1036 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING); in cy8c95x0_irq_set_type()
1037 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING); in cy8c95x0_irq_set_type()
1038 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW); in cy8c95x0_irq_set_type()
1039 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH); in cy8c95x0_irq_set_type()
1050 clear_bit(hwirq, chip->irq_trig_raise); in cy8c95x0_irq_shutdown()
1051 clear_bit(hwirq, chip->irq_trig_fall); in cy8c95x0_irq_shutdown()
1052 clear_bit(hwirq, chip->irq_trig_low); in cy8c95x0_irq_shutdown()
1053 clear_bit(hwirq, chip->irq_trig_high); in cy8c95x0_irq_shutdown()
1057 .name = "cy8c95x0-irq",
1086 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, in cy8c95x0_irq_pending()
1097 struct gpio_chip *gc = &chip->gpio_chip; in cy8c95x0_irq_handler()
1099 int nested_irq, level; in cy8c95x0_irq_handler() local
1107 for_each_set_bit(level, pending, MAX_LINE) { in cy8c95x0_irq_handler()
1109 nested_irq = irq_find_mapping(gc->irq.domain, level); in cy8c95x0_irq_handler()
1112 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); in cy8c95x0_irq_handler()
1116 if (test_bit(level, chip->irq_trig_low)) in cy8c95x0_irq_handler()
1117 while (!cy8c95x0_gpio_get_value(gc, level)) in cy8c95x0_irq_handler()
1119 else if (test_bit(level, chip->irq_trig_high)) in cy8c95x0_irq_handler()
1120 while (cy8c95x0_gpio_get_value(gc, level)) in cy8c95x0_irq_handler()
1135 return chip->tpin; in cy8c95x0_pinctrl_get_groups_count()
1208 *num_groups = chip->tpin; in cy8c95x0_get_function_groups()
1214 u8 port = cypress_get_port(chip, off); in cy8c95x0_set_mode() local
1217 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0); in cy8c95x0_set_mode()
1223 u8 port = cypress_get_port(chip, group); in cy8c95x0_pinmux_mode() local
1235 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit); in cy8c95x0_pinmux_mode()
1239 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit); in cy8c95x0_pinmux_mode()
1310 struct gpio_irq_chip *girq = &chip->gpio_chip.irq; in cy8c95x0_irq_setup()
1314 mutex_init(&chip->irq_lock); in cy8c95x0_irq_setup()
1321 dev_err(chip->dev, "failed to clear irq status register\n"); in cy8c95x0_irq_setup()
1326 bitmap_fill(chip->irq_mask, MAX_LINE); in cy8c95x0_irq_setup()
1331 girq->parent_handler = NULL; in cy8c95x0_irq_setup()
1332 girq->num_parents = 0; in cy8c95x0_irq_setup()
1333 girq->parents = NULL; in cy8c95x0_irq_setup()
1334 girq->default_type = IRQ_TYPE_NONE; in cy8c95x0_irq_setup()
1335 girq->handler = handle_simple_irq; in cy8c95x0_irq_setup()
1336 girq->threaded = true; in cy8c95x0_irq_setup()
1338 ret = devm_request_threaded_irq(chip->dev, irq, in cy8c95x0_irq_setup()
1341 dev_name(chip->dev), chip); in cy8c95x0_irq_setup()
1343 dev_err(chip->dev, "failed to request irq %d\n", irq); in cy8c95x0_irq_setup()
1346 dev_info(chip->dev, "Registered threaded IRQ\n"); in cy8c95x0_irq_setup()
1353 struct pinctrl_desc *pd = &chip->pinctrl_desc; in cy8c95x0_setup_pinctrl()
1355 pd->pctlops = &cy8c95x0_pinctrl_ops; in cy8c95x0_setup_pinctrl()
1356 pd->confops = &cy8c95x0_pinconf_ops; in cy8c95x0_setup_pinctrl()
1357 pd->pmxops = &cy8c95x0_pmxops; in cy8c95x0_setup_pinctrl()
1358 pd->name = dev_name(chip->dev); in cy8c95x0_setup_pinctrl()
1359 pd->pins = cy8c9560_pins; in cy8c95x0_setup_pinctrl()
1360 pd->npins = chip->tpin; in cy8c95x0_setup_pinctrl()
1361 pd->owner = THIS_MODULE; in cy8c95x0_setup_pinctrl()
1363 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); in cy8c95x0_setup_pinctrl()
1364 if (IS_ERR(chip->pctldev)) in cy8c95x0_setup_pinctrl()
1365 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), in cy8c95x0_setup_pinctrl()
1374 struct i2c_adapter *adapter = client->adapter; in cy8c95x0_detect()
1379 return -ENODEV; in cy8c95x0_detect()
1395 return -ENODEV; in cy8c95x0_detect()
1398 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); in cy8c95x0_detect()
1399 strscpy(info->type, name); in cy8c95x0_detect()
1406 struct device *dev = &client->dev; in cy8c95x0_probe()
1414 return -ENOMEM; in cy8c95x0_probe()
1416 chip->dev = dev; in cy8c95x0_probe()
1419 chip->driver_data = (uintptr_t)i2c_get_match_data(client); in cy8c95x0_probe()
1420 if (!chip->driver_data) in cy8c95x0_probe()
1421 return -ENODEV; in cy8c95x0_probe()
1423 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; in cy8c95x0_probe()
1424 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); in cy8c95x0_probe()
1428 switch (chip->tpin) { in cy8c95x0_probe()
1430 strscpy(chip->name, cy8c95x0_id[0].name); in cy8c95x0_probe()
1431 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1; in cy8c95x0_probe()
1434 strscpy(chip->name, cy8c95x0_id[1].name); in cy8c95x0_probe()
1435 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1; in cy8c95x0_probe()
1438 strscpy(chip->name, cy8c95x0_id[2].name); in cy8c95x0_probe()
1439 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1; in cy8c95x0_probe()
1442 return -ENODEV; in cy8c95x0_probe()
1450 chip->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); in cy8c95x0_probe()
1451 if (IS_ERR(chip->gpio_reset)) in cy8c95x0_probe()
1452 return dev_err_probe(dev, PTR_ERR(chip->gpio_reset), "Failed to get GPIO 'reset'\n"); in cy8c95x0_probe()
1453 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); in cy8c95x0_probe()
1454 if (chip->gpio_reset) { in cy8c95x0_probe()
1456 gpiod_set_value_cansleep(chip->gpio_reset, 0); in cy8c95x0_probe()
1466 chip->regmap = devm_regmap_init_i2c(client, ®map_conf); in cy8c95x0_probe()
1467 if (IS_ERR(chip->regmap)) in cy8c95x0_probe()
1468 return PTR_ERR(chip->regmap); in cy8c95x0_probe()
1470 bitmap_zero(chip->push_pull, MAX_LINE); in cy8c95x0_probe()
1473 bitmap_fill(chip->map, MAX_LINE); in cy8c95x0_probe()
1474 bitmap_clear(chip->map, 20, 4); in cy8c95x0_probe()
1476 mutex_init(&chip->i2c_lock); in cy8c95x0_probe()
1479 ret = cy8c95x0_acpi_get_irq(&client->dev); in cy8c95x0_probe()
1481 client->irq = ret; in cy8c95x0_probe()
1484 if (client->irq) { in cy8c95x0_probe()
1485 ret = cy8c95x0_irq_setup(chip, client->irq); in cy8c95x0_probe()
1505 .name = "cy8c95x0-pinctrl",