Lines Matching +full:gpo +full:- +full:config +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/pinctrl/pinconf-generic.h>
123 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
125 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
133 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
135 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
143 ioread32(bank->base + NPCM8XX_GP_N_DIN), in npcmgpio_dbg_show()
144 ioread32(bank->base + NPCM8XX_GP_N_DOUT), in npcmgpio_dbg_show()
145 ioread32(bank->base + NPCM8XX_GP_N_IEM), in npcmgpio_dbg_show()
146 ioread32(bank->base + NPCM8XX_GP_N_OE)); in npcmgpio_dbg_show()
148 ioread32(bank->base + NPCM8XX_GP_N_PU), in npcmgpio_dbg_show()
149 ioread32(bank->base + NPCM8XX_GP_N_PD), in npcmgpio_dbg_show()
150 ioread32(bank->base + NPCM8XX_GP_N_DBNC), in npcmgpio_dbg_show()
151 ioread32(bank->base + NPCM8XX_GP_N_POL)); in npcmgpio_dbg_show()
153 ioread32(bank->base + NPCM8XX_GP_N_EVTYP), in npcmgpio_dbg_show()
154 ioread32(bank->base + NPCM8XX_GP_N_EVBE), in npcmgpio_dbg_show()
155 ioread32(bank->base + NPCM8XX_GP_N_EVEN), in npcmgpio_dbg_show()
156 ioread32(bank->base + NPCM8XX_GP_N_EVST)); in npcmgpio_dbg_show()
158 ioread32(bank->base + NPCM8XX_GP_N_OTYP), in npcmgpio_dbg_show()
159 ioread32(bank->base + NPCM8XX_GP_N_OSRC), in npcmgpio_dbg_show()
160 ioread32(bank->base + NPCM8XX_GP_N_ODSC)); in npcmgpio_dbg_show()
162 ioread32(bank->base + NPCM8XX_GP_N_OBL0), in npcmgpio_dbg_show()
163 ioread32(bank->base + NPCM8XX_GP_N_OBL1), in npcmgpio_dbg_show()
164 ioread32(bank->base + NPCM8XX_GP_N_OBL2), in npcmgpio_dbg_show()
165 ioread32(bank->base + NPCM8XX_GP_N_OBL3)); in npcmgpio_dbg_show()
167 ioread32(bank->base + NPCM8XX_GP_N_SPLCK), in npcmgpio_dbg_show()
168 ioread32(bank->base + NPCM8XX_GP_N_MPLCK)); in npcmgpio_dbg_show()
180 return bank->direction_input(chip, offset); in npcmgpio_direction_input()
193 return bank->direction_output(chip, offset, value); in npcmgpio_direction_output()
205 return bank->request(chip, offset); in npcmgpio_gpio_request()
220 sts = ioread32(bank->base + NPCM8XX_GP_N_EVST); in npcmgpio_irq_handler()
221 en = ioread32(bank->base + NPCM8XX_GP_N_EVEN); in npcmgpio_irq_handler()
224 generic_handle_domain_irq(gc->irq.domain, bit); in npcmgpio_irq_handler()
236 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
237 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
240 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
241 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
244 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
245 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
248 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
251 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
254 return -EINVAL; in npcmgpio_set_irq_type()
258 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
261 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
274 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST); in npcmgpio_irq_ack()
283 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC); in npcmgpio_irq_mask()
292 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS); in npcmgpio_irq_unmask()
300 /* active-high, input, clear interrupt, enable interrupt */ in npcmgpio_irq_startup()
309 .name = "NPCM8XX-GPIO-IRQ",
449 static const int smb6c_pins[] = { 0, 1 };
469 static const int smb18_pins[] = { 0, 1 };
520 static const int iox1_pins[] = { 0, 1, 2, 3 };
1295 #define GPI BIT(0) /* Not GPO */
1296 #define GPO BIT(1) /* Not GPI */ macro
1310 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 FLAGS */
1312 …NPCM8XX_PINCFG(1, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none,…
1339 …NPCM8XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0,…
1340 …NPCM8XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0,…
1353 …42, bmcuart0a, MFSEL1, 9, cp1utxd, MFSEL6, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR…
1354 …(43, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1355 …b, MFSEL1, 28, nbu1crts, MFSEL6, 15, jtag2, MFSEL4, 0, tp_jtag3, MFSEL7, 13, j2j3, MFSEL5, 2, GPO),
1356 …5, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
1357 …6, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
1359 …PINCFG(48, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0,…
1360 …PINCFG(49, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0,…
1361 …(50, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
1362 …(51, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
1363 …PINCFG(52, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1364 …PINCFG(53, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1365 …PINCFG(54, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1366 …PINCFG(55, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1367 …NCFG(56, r1err, MFSEL1, 12, r1oen, MFSEL5, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1372 …_PINCFG(61, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1373 …b, MFSEL1, 28, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, nbu1crts, MFSEL6, 15, tp_jtag3, MFSEL7, 13, GPO),
1374 …(63, hsi1a, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1375 …PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1376 …NPCM8XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, …
1377 …PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1378 …PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1379 …PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1380 …PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1381 …PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1382 …PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1383 …PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1384 …PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1385 …NCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1386 …NCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1387 …NCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1388 …NCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1389 …NCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1390 …NCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1398 …X_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1399 …X_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1400 …X_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1401 …CFG(90, r2err, MFSEL1, 15, r2oen, MFSEL5, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1403 …NPCM8XX_PINCFG(92, r2md, MFSEL1, 16, cp1gpio7, MFSEL6, 9, tp_gpio1, MFSEL7, 1, none, NONE, 0, non…
1482 …NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0…
1483 …NPCM8XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0…
1492 …X_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1493 …X_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1507 …NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NO…
1511 …_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1512 …X_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1513 …NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NO…
1533 … NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLE…
1536 …SEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLE…
1537 …SEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLE…
1551 …NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0…
1560 PINCTRL_PIN(1, "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"),
1811 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || in npcm8xx_setfunc()
1812 cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) { in npcm8xx_setfunc()
1813 if (cfg->reg0) in npcm8xx_setfunc()
1814 regmap_update_bits(gcr_regmap, cfg->reg0, in npcm8xx_setfunc()
1815 BIT(cfg->bit0), in npcm8xx_setfunc()
1816 (cfg->fn0 == mode) ? in npcm8xx_setfunc()
1817 BIT(cfg->bit0) : 0); in npcm8xx_setfunc()
1818 if (cfg->reg1) in npcm8xx_setfunc()
1819 regmap_update_bits(gcr_regmap, cfg->reg1, in npcm8xx_setfunc()
1820 BIT(cfg->bit1), in npcm8xx_setfunc()
1821 (cfg->fn1 == mode) ? in npcm8xx_setfunc()
1822 BIT(cfg->bit1) : 0); in npcm8xx_setfunc()
1823 if (cfg->reg2) in npcm8xx_setfunc()
1824 regmap_update_bits(gcr_regmap, cfg->reg2, in npcm8xx_setfunc()
1825 BIT(cfg->bit2), in npcm8xx_setfunc()
1826 (cfg->fn2 == mode) ? in npcm8xx_setfunc()
1827 BIT(cfg->bit2) : 0); in npcm8xx_setfunc()
1828 if (cfg->reg3) in npcm8xx_setfunc()
1829 regmap_update_bits(gcr_regmap, cfg->reg3, in npcm8xx_setfunc()
1830 BIT(cfg->bit3), in npcm8xx_setfunc()
1831 (cfg->fn3 == mode) ? in npcm8xx_setfunc()
1832 BIT(cfg->bit3) : 0); in npcm8xx_setfunc()
1833 if (cfg->reg4) in npcm8xx_setfunc()
1834 regmap_update_bits(gcr_regmap, cfg->reg4, in npcm8xx_setfunc()
1835 BIT(cfg->bit4), in npcm8xx_setfunc()
1836 (cfg->fn4 == mode) ? in npcm8xx_setfunc()
1837 BIT(cfg->bit4) : 0); in npcm8xx_setfunc()
1845 int gpio = pin % bank->gc.ngpio; in npcm8xx_get_slew_rate()
1850 return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask; in npcm8xx_get_slew_rate()
1857 return -EINVAL; in npcm8xx_get_slew_rate()
1864 void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC; in npcm8xx_set_slew_rate()
1865 int gpio = BIT(pin % bank->gc.ngpio); in npcm8xx_set_slew_rate()
1870 npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio); in npcm8xx_set_slew_rate()
1872 case 1: in npcm8xx_set_slew_rate()
1873 npcm_gpio_set(&bank->gc, OSRC_Offset, gpio); in npcm8xx_set_slew_rate()
1876 return -EINVAL; in npcm8xx_set_slew_rate()
1881 return -EINVAL; in npcm8xx_set_slew_rate()
1888 case 1: in npcm8xx_set_slew_rate()
1893 return -EINVAL; in npcm8xx_set_slew_rate()
1904 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_get_drive_strength()
1905 int gpio = pin % bank->gc.ngpio; in npcm8xx_get_drive_strength()
1912 return -EINVAL; in npcm8xx_get_drive_strength()
1914 val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask; in npcm8xx_get_drive_strength()
1916 dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds); in npcm8xx_get_drive_strength()
1925 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_set_drive_strength()
1926 int gpio = BIT(pin % bank->gc.ngpio); in npcm8xx_set_drive_strength()
1932 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); in npcm8xx_set_drive_strength()
1934 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); in npcm8xx_set_drive_strength()
1936 return -ENOTSUPP; in npcm8xx_set_drive_strength()
2016 npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins, in npcm8xx_pinmux_set_mux()
2033 npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode); in npcm8xx_gpio_request_enable()
2045 virq = irq_find_mapping(npcm->domain, offset); in npcm8xx_gpio_request_free()
2056 &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK]; in npcm_gpio_set_direction()
2057 int gpio = BIT(offset % bank->gc.ngpio); in npcm_gpio_set_direction()
2060 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); in npcm_gpio_set_direction()
2062 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); in npcm_gpio_set_direction()
2080 void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4); in debounce_timing_setting()
2085 if (bank->debounce.set_val[i]) { in debounce_timing_setting()
2086 if (bank->debounce.nanosec_val[i] == nanosecs) { in debounce_timing_setting()
2088 npcm_gpio_set(&bank->gc, DBNCS_offset, in debounce_timing_setting()
2093 bank->debounce.set_val[i] = true; in debounce_timing_setting()
2094 bank->debounce.nanosec_val[i] = nanosecs; in debounce_timing_setting()
2096 npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select); in debounce_timing_setting()
2098 case 1 ... 1040: in debounce_timing_setting()
2099 iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2102 iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2105 iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2108 iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2111 iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2114 iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2117 iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2120 iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2125 return -ENOTSUPP; in debounce_timing_setting()
2130 bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); in debounce_timing_setting()
2138 return -ENOTSUPP; in debounce_timing_setting()
2147 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm_set_debounce()
2148 int gpio = BIT(pin % bank->gc.ngpio); in npcm_set_debounce()
2152 ret = debounce_timing_setting(bank, pin % bank->gc.ngpio, in npcm_set_debounce()
2155 …dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debo… in npcm_set_debounce()
2157 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, in npcm_set_debounce()
2162 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio); in npcm_set_debounce()
2169 unsigned long *config) in npcm8xx_config_get() argument
2171 enum pin_config_param param = pinconf_to_config_param(*config); in npcm8xx_config_get()
2174 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_config_get()
2175 int gpio = pin % bank->gc.ngpio; in npcm8xx_config_get()
2184 pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask; in npcm8xx_config_get()
2185 pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask; in npcm8xx_config_get()
2195 ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask; in npcm8xx_config_get()
2196 oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask; in npcm8xx_config_get()
2203 rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask); in npcm8xx_config_get()
2206 rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask; in npcm8xx_config_get()
2209 rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask; in npcm8xx_config_get()
2214 *config = pinconf_to_config_packed(param, rc); in npcm8xx_config_get()
2217 rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin); in npcm8xx_config_get()
2219 *config = pinconf_to_config_packed(param, rc); in npcm8xx_config_get()
2222 return -ENOTSUPP; in npcm8xx_config_get()
2226 return -EINVAL; in npcm8xx_config_get()
2232 unsigned int pin, unsigned long config) in npcm8xx_config_set_one() argument
2234 enum pin_config_param param = pinconf_to_config_param(config); in npcm8xx_config_set_one()
2236 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; in npcm8xx_config_set_one()
2237 u32 arg = pinconf_to_config_argument(config); in npcm8xx_config_set_one()
2238 int gpio = BIT(pin % bank->gc.ngpio); in npcm8xx_config_set_one()
2242 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); in npcm8xx_config_set_one()
2243 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); in npcm8xx_config_set_one()
2246 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); in npcm8xx_config_set_one()
2247 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); in npcm8xx_config_set_one()
2250 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); in npcm8xx_config_set_one()
2251 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); in npcm8xx_config_set_one()
2254 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); in npcm8xx_config_set_one()
2255 bank->direction_input(&bank->gc, pin % bank->gc.ngpio); in npcm8xx_config_set_one()
2258 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); in npcm8xx_config_set_one()
2259 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); in npcm8xx_config_set_one()
2262 npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); in npcm8xx_config_set_one()
2265 npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); in npcm8xx_config_set_one()
2270 return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); in npcm8xx_config_set_one()
2274 return -ENOTSUPP; in npcm8xx_config_set_one()
2286 while (num_configs--) { in npcm8xx_config_set()
2303 .name = "npcm8xx-pinctrl",
2316 return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent), in npcmgpio_add_pin_ranges()
2317 bank->pinctrl_id, bank->gc.base, in npcmgpio_add_pin_ranges()
2318 bank->gc.ngpio); in npcmgpio_add_pin_ranges()
2324 struct device *dev = pctrl->dev; in npcm8xx_gpio_fw()
2326 int ret = -ENXIO; in npcm8xx_gpio_fw()
2330 pctrl->gpio_bank[id].base = fwnode_iomap(child, 0); in npcm8xx_gpio_fw()
2331 if (!pctrl->gpio_bank[id].base) in npcm8xx_gpio_fw()
2332 return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id); in npcm8xx_gpio_fw()
2334 ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, in npcm8xx_gpio_fw()
2335 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, in npcm8xx_gpio_fw()
2336 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, in npcm8xx_gpio_fw()
2339 pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, in npcm8xx_gpio_fw()
2344 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); in npcm8xx_gpio_fw()
2346 return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id); in npcm8xx_gpio_fw()
2352 pctrl->gpio_bank[id].irq = ret; in npcm8xx_gpio_fw()
2353 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; in npcm8xx_gpio_fw()
2354 pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; in npcm8xx_gpio_fw()
2355 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; in npcm8xx_gpio_fw()
2356 pctrl->gpio_bank[id].gc.base = -1; in npcm8xx_gpio_fw()
2357 pctrl->gpio_bank[id].gc.ngpio = args.args[2]; in npcm8xx_gpio_fw()
2358 pctrl->gpio_bank[id].gc.owner = THIS_MODULE; in npcm8xx_gpio_fw()
2359 pctrl->gpio_bank[id].gc.parent = dev; in npcm8xx_gpio_fw()
2360 pctrl->gpio_bank[id].gc.fwnode = child; in npcm8xx_gpio_fw()
2361 pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); in npcm8xx_gpio_fw()
2362 if (pctrl->gpio_bank[id].gc.label == NULL) in npcm8xx_gpio_fw()
2363 return -ENOMEM; in npcm8xx_gpio_fw()
2365 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; in npcm8xx_gpio_fw()
2366 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; in npcm8xx_gpio_fw()
2367 pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; in npcm8xx_gpio_fw()
2368 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; in npcm8xx_gpio_fw()
2369 pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; in npcm8xx_gpio_fw()
2370 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; in npcm8xx_gpio_fw()
2371 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; in npcm8xx_gpio_fw()
2372 pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free; in npcm8xx_gpio_fw()
2374 pctrl->gpio_bank[id].debounce.set_val[i] = false; in npcm8xx_gpio_fw()
2375 pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges; in npcm8xx_gpio_fw()
2379 pctrl->bank_num = id; in npcm8xx_gpio_fw()
2387 for (id = 0 ; id < pctrl->bank_num ; id++) { in npcm8xx_gpio_register()
2390 girq = &pctrl->gpio_bank[id].gc.irq; in npcm8xx_gpio_register()
2391 girq->chip = &pctrl->gpio_bank[id].irq_chip; in npcm8xx_gpio_register()
2392 girq->parent_handler = npcmgpio_irq_handler; in npcm8xx_gpio_register()
2393 girq->num_parents = 1; in npcm8xx_gpio_register()
2394 girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents, in npcm8xx_gpio_register()
2395 sizeof(*girq->parents), in npcm8xx_gpio_register()
2397 if (!girq->parents) in npcm8xx_gpio_register()
2398 return -ENOMEM; in npcm8xx_gpio_register()
2400 girq->parents[0] = pctrl->gpio_bank[id].irq; in npcm8xx_gpio_register()
2401 girq->default_type = IRQ_TYPE_NONE; in npcm8xx_gpio_register()
2402 girq->handler = handle_level_irq; in npcm8xx_gpio_register()
2403 ret = devm_gpiochip_add_data(pctrl->dev, in npcm8xx_gpio_register()
2404 &pctrl->gpio_bank[id].gc, in npcm8xx_gpio_register()
2405 &pctrl->gpio_bank[id]); in npcm8xx_gpio_register()
2407 return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id); in npcm8xx_gpio_register()
2415 struct device *dev = &pdev->dev; in npcm8xx_pinctrl_probe()
2421 return -ENOMEM; in npcm8xx_pinctrl_probe()
2423 pctrl->dev = dev; in npcm8xx_pinctrl_probe()
2426 pctrl->gcr_regmap = in npcm8xx_pinctrl_probe()
2428 if (IS_ERR(pctrl->gcr_regmap)) in npcm8xx_pinctrl_probe()
2429 return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), in npcm8xx_pinctrl_probe()
2435 "Failed to gpio dt-binding\n"); in npcm8xx_pinctrl_probe()
2437 pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl); in npcm8xx_pinctrl_probe()
2438 if (IS_ERR(pctrl->pctldev)) in npcm8xx_pinctrl_probe()
2439 return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), in npcm8xx_pinctrl_probe()
2450 { .compatible = "nuvoton,npcm845-pinctrl" },
2458 .name = "npcm8xx-pinctrl",