1 // SPDX-License-Identifier: GPL-2.0
5  * Author: Shan-Chun Hung <schung@nuvoton.com>
24 #include "pinctrl-ma35.h"
59 /* GPIO pull-up and pull-down selection control */
66  * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67  * while bits 16 ~ 31 control high-level or rising edge trigger.
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85 #define field_get(_mask, _reg)	(((_reg) & (_mask)) >> (ffs(_mask) - 1))
86 #define field_prep(_mask, _val)	(((_val) << (ffs(_mask) - 1)) & (_mask))
119 	struct ma35_pin_setting	*settings;  member
162 	return npctl->ngroups;  in ma35_get_groups_count()
169 	return npctl->groups[selector].name;  in ma35_get_group_name()
177 	if (selector >= npctl->ngroups)  in ma35_get_group_pins()
178 		return -EINVAL;  in ma35_get_group_pins()
180 	*pins = npctl->groups[selector].pins;  in ma35_get_group_pins()
181 	*npins = npctl->groups[selector].npins;  in ma35_get_group_pins()
191 	for (i = 0; i < npctl->ngroups; i++) {  in ma35_pinctrl_find_group_by_name()
192 		if (!strcmp(npctl->groups[i].name, name))  in ma35_pinctrl_find_group_by_name()
193 			return &npctl->groups[i];  in ma35_pinctrl_find_group_by_name()
214 	grp = ma35_pinctrl_find_group_by_name(npctl, np->name);  in ma35_pinctrl_dt_node_to_map_func()
216 		dev_err(npctl->dev, "unable to find group for node %s\n", np->name);  in ma35_pinctrl_dt_node_to_map_func()
217 		return -EINVAL;  in ma35_pinctrl_dt_node_to_map_func()
220 	map_num += grp->npins;  in ma35_pinctrl_dt_node_to_map_func()
223 		return -ENOMEM;  in ma35_pinctrl_dt_node_to_map_func()
230 		return -EINVAL;  in ma35_pinctrl_dt_node_to_map_func()
233 	new_map[0].data.mux.function = parent->name;  in ma35_pinctrl_dt_node_to_map_func()
234 	new_map[0].data.mux.group = np->name;  in ma35_pinctrl_dt_node_to_map_func()
238 	for (i = 0; i < grp->npins; i++) {  in ma35_pinctrl_dt_node_to_map_func()
240 		new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]);  in ma35_pinctrl_dt_node_to_map_func()
241 		new_map[i].data.configs.configs = grp->settings[i].configs;  in ma35_pinctrl_dt_node_to_map_func()
242 		new_map[i].data.configs.num_configs = grp->settings[i].nconfigs;  in ma35_pinctrl_dt_node_to_map_func()
244 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",  in ma35_pinctrl_dt_node_to_map_func()
245 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);  in ma35_pinctrl_dt_node_to_map_func()
262 	return npctl->nfunctions;  in ma35_pinmux_get_func_count()
270 	return npctl->functions[selector].name;  in ma35_pinmux_get_func_name()
280 	*groups = npctl->functions[function].groups;  in ma35_pinmux_get_func_groups()
281 	*num_groups = npctl->functions[function].ngroups;  in ma35_pinmux_get_func_groups()
290 	struct ma35_pin_group *grp = &npctl->groups[group];  in ma35_pinmux_set_mux()
291 	struct ma35_pin_setting *setting = grp->settings;  in ma35_pinmux_set_mux()
294 	dev_dbg(npctl->dev, "enable function %s group %s\n",  in ma35_pinmux_set_mux()
295 		npctl->functions[selector].name, npctl->groups[group].name);  in ma35_pinmux_set_mux()
297 	for (i = 0; i < grp->npins; i++) {  in ma35_pinmux_set_mux()
298 		regmap_read(npctl->regmap, setting->offset, &regval);  in ma35_pinmux_set_mux()
299 		regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,  in ma35_pinmux_set_mux()
300 				   setting->shift);  in ma35_pinmux_set_mux()
301 		regval |= setting->muxval << setting->shift;  in ma35_pinmux_set_mux()
302 		regmap_write(npctl->regmap, setting->offset, regval);  in ma35_pinmux_set_mux()
336 	void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;  in ma35_gpio_core_direction_in()
348 	void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;  in ma35_gpio_core_direction_out()
349 	void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;  in ma35_gpio_core_direction_out()
369 	void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;  in ma35_gpio_core_get()
377 	void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;  in ma35_gpio_core_set()
395 		reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;  in ma35_gpio_core_to_request()
399 		reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;  in ma35_gpio_core_to_request()
400 		bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;  in ma35_gpio_core_to_request()
403 	regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, &regval);  in ma35_gpio_core_to_request()
404 	regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);  in ma35_gpio_core_to_request()
405 	regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);  in ma35_gpio_core_to_request()
413 	void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;  in ma35_irq_gpio_ack()
422 	void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;  in ma35_irq_gpio_mask()
436 	void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;  in ma35_irq_gpio_unmask()
437 	void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;  in ma35_irq_gpio_unmask()
441 	bval = bank->irqtype & BIT(hwirq);  in ma35_irq_gpio_unmask()
446 	bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);  in ma35_irq_gpio_unmask()
460 		bank->irqtype &= ~BIT(hwirq);  in ma35_irq_irqtype()
461 		bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);  in ma35_irq_irqtype()
466 		bank->irqtype &= ~BIT(hwirq);  in ma35_irq_irqtype()
467 		bank->irqinten |= MA35_GP_INTEN_H(hwirq);  in ma35_irq_irqtype()
468 		bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);  in ma35_irq_irqtype()
473 		bank->irqtype &= ~BIT(hwirq);  in ma35_irq_irqtype()
474 		bank->irqinten |= MA35_GP_INTEN_L(hwirq);  in ma35_irq_irqtype()
475 		bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);  in ma35_irq_irqtype()
478 		return -EINVAL;  in ma35_irq_irqtype()
481 	writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);  in ma35_irq_irqtype()
482 	writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);  in ma35_irq_irqtype()
488 	.name = "MA35-GPIO-IRQ",
502 	struct irq_domain *irqdomain = bank->chip.irq.domain;  in ma35_irq_demux_intgroup()
509 	isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);  in ma35_irq_demux_intgroup()
511 	for_each_set_bit(offset, &isr, bank->nr_pins)  in ma35_irq_demux_intgroup()
519 	struct ma35_pin_ctrl *ctrl = npctl->ctrl;  in ma35_gpiolib_register()
520 	struct ma35_pin_bank *bank = ctrl->pin_banks;  in ma35_gpiolib_register()
524 	for (i = 0; i < ctrl->nr_banks; i++, bank++) {  in ma35_gpiolib_register()
525 		if (!bank->valid) {  in ma35_gpiolib_register()
526 			dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);  in ma35_gpiolib_register()
529 		bank->irqtype = 0;  in ma35_gpiolib_register()
530 		bank->irqinten = 0;  in ma35_gpiolib_register()
531 		bank->chip.label = bank->name;  in ma35_gpiolib_register()
532 		bank->chip.of_gpio_n_cells = 2;  in ma35_gpiolib_register()
533 		bank->chip.parent = &pdev->dev;  in ma35_gpiolib_register()
534 		bank->chip.request = ma35_gpio_core_to_request;  in ma35_gpiolib_register()
535 		bank->chip.direction_input = ma35_gpio_core_direction_in;  in ma35_gpiolib_register()
536 		bank->chip.direction_output = ma35_gpio_core_direction_out;  in ma35_gpiolib_register()
537 		bank->chip.get = ma35_gpio_core_get;  in ma35_gpiolib_register()
538 		bank->chip.set = ma35_gpio_core_set;  in ma35_gpiolib_register()
539 		bank->chip.base = -1;  in ma35_gpiolib_register()
540 		bank->chip.ngpio = bank->nr_pins;  in ma35_gpiolib_register()
541 		bank->chip.can_sleep = false;  in ma35_gpiolib_register()
543 		if (bank->irq > 0) {  in ma35_gpiolib_register()
546 			girq = &bank->chip.irq;  in ma35_gpiolib_register()
548 			girq->parent_handler = ma35_irq_demux_intgroup;  in ma35_gpiolib_register()
549 			girq->num_parents = 1;  in ma35_gpiolib_register()
551 			girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,  in ma35_gpiolib_register()
552 						     sizeof(*girq->parents), GFP_KERNEL);  in ma35_gpiolib_register()
553 			if (!girq->parents)  in ma35_gpiolib_register()
554 				return -ENOMEM;  in ma35_gpiolib_register()
556 			girq->parents[0] = bank->irq;  in ma35_gpiolib_register()
557 			girq->default_type = IRQ_TYPE_NONE;  in ma35_gpiolib_register()
558 			girq->handler = handle_bad_irq;  in ma35_gpiolib_register()
561 		ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);  in ma35_gpiolib_register()
563 			dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",  in ma35_gpiolib_register()
564 				bank->chip.label, ret);  in ma35_gpiolib_register()
573 	bank->reg_base = fwnode_iomap(bank->fwnode, 0);  in ma35_get_bank_data()
574 	if (!bank->reg_base)  in ma35_get_bank_data()
575 		return -ENOMEM;  in ma35_get_bank_data()
577 	bank->irq = fwnode_irq_get(bank->fwnode, 0);  in ma35_get_bank_data()
579 	bank->nr_pins = MA35_GPIO_PORT_MAX;  in ma35_get_bank_data()
581 	bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);  in ma35_get_bank_data()
582 	if (IS_ERR(bank->clk))  in ma35_get_bank_data()
583 		return PTR_ERR(bank->clk);  in ma35_get_bank_data()
585 	return clk_prepare_enable(bank->clk);  in ma35_get_bank_data()
595 	ctrl = pctl->ctrl;  in ma35_pinctrl_get_soc_data()
596 	ctrl->nr_banks = MA35_GPIO_BANK_MAX;  in ma35_pinctrl_get_soc_data()
598 	ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,  in ma35_pinctrl_get_soc_data()
599 				       sizeof(*ctrl->pin_banks), GFP_KERNEL);  in ma35_pinctrl_get_soc_data()
600 	if (!ctrl->pin_banks)  in ma35_pinctrl_get_soc_data()
601 		return -ENOMEM;  in ma35_pinctrl_get_soc_data()
603 	for (i = 0; i < ctrl->nr_banks; i++) {  in ma35_pinctrl_get_soc_data()
604 		ctrl->pin_banks[i].bank_num = i;  in ma35_pinctrl_get_soc_data()
605 		ctrl->pin_banks[i].name = gpio_group_name[i];  in ma35_pinctrl_get_soc_data()
608 	for_each_gpiochip_node(&pdev->dev, child) {  in ma35_pinctrl_get_soc_data()
609 		bank = &ctrl->pin_banks[id];  in ma35_pinctrl_get_soc_data()
610 		bank->fwnode = child;  in ma35_pinctrl_get_soc_data()
611 		bank->regmap = pctl->regmap;  in ma35_pinctrl_get_soc_data()
612 		bank->dev = &pdev->dev;  in ma35_pinctrl_get_soc_data()
614 			bank->valid = true;  in ma35_pinctrl_get_soc_data()
627 static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin,  in ma35_pinconf_set_pull()  argument
634 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_set_pull()
635 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_set_pull()
660 static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin)  in ma35_pinconf_get_output()  argument
666 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_get_output()
667 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_get_output()
676 static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin)  in ma35_pinconf_get_pull()  argument
682 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_get_pull()
683 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_get_pull()
703 static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out)  in ma35_pinconf_set_output()  argument
708 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_set_output()
709 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_set_output()
716 static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin)  in ma35_pinconf_get_power_source()  argument
722 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_get_power_source()
723 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_get_power_source()
734 					 unsigned int pin, int arg)  in ma35_pinconf_set_power_source()  argument
741 		return -EINVAL;  in ma35_pinconf_set_power_source()
743 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_set_power_source()
744 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_set_power_source()
758 static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,  in ma35_pinconf_get_drive_strength()  argument
765 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_get_drive_strength()
766 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_get_drive_strength()
771 	if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800)  in ma35_pinconf_get_drive_strength()
779 static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,  in ma35_pinconf_set_drive_strength()  argument
784 	int i, ds_val = -1;  in ma35_pinconf_set_drive_strength()
787 	if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) {  in ma35_pinconf_set_drive_strength()
802 	if (ds_val == -1)  in ma35_pinconf_set_drive_strength()
803 		return -EINVAL;  in ma35_pinconf_set_drive_strength()
805 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_set_drive_strength()
806 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_set_drive_strength()
817 static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin)  in ma35_pinconf_get_schmitt_enable()  argument
823 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_get_schmitt_enable()
824 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_get_schmitt_enable()
831 static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable)  in ma35_pinconf_set_schmitt()  argument
837 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_set_schmitt()
838 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_set_schmitt()
852 static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin)  in ma35_pinconf_get_slew_rate()  argument
858 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_get_slew_rate()
859 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_get_slew_rate()
866 static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate)  in ma35_pinconf_set_slew_rate()  argument
872 	ma35_gpio_cla_port(pin, &group_num, &port);  in ma35_pinconf_set_slew_rate()
873 	base = npctl->ctrl->pin_banks[group_num].reg_base;  in ma35_pinconf_set_slew_rate()
884 static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)  in ma35_pinconf_get()  argument
895 		if (ma35_pinconf_get_pull(npctl, pin) != param)  in ma35_pinconf_get()
896 			return -EINVAL;  in ma35_pinconf_get()
901 		ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg);  in ma35_pinconf_get()
907 		arg = ma35_pinconf_get_schmitt_enable(npctl, pin);  in ma35_pinconf_get()
911 		arg = ma35_pinconf_get_slew_rate(npctl, pin);  in ma35_pinconf_get()
915 		arg = ma35_pinconf_get_output(npctl, pin);  in ma35_pinconf_get()
919 		arg = ma35_pinconf_get_power_source(npctl, pin);  in ma35_pinconf_get()
923 		return -EINVAL;  in ma35_pinconf_get()
930 static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,  in ma35_pinconf_set()  argument
946 			ret = ma35_pinconf_set_pull(npctl, pin, param);  in ma35_pinconf_set()
950 			ret = ma35_pinconf_set_drive_strength(npctl, pin, arg);  in ma35_pinconf_set()
954 			ret = ma35_pinconf_set_schmitt(npctl, pin, 1);  in ma35_pinconf_set()
958 			ret = ma35_pinconf_set_schmitt(npctl, pin, arg);  in ma35_pinconf_set()
962 			ret = ma35_pinconf_set_slew_rate(npctl, pin, arg);  in ma35_pinconf_set()
966 			ret = ma35_pinconf_set_output(npctl, pin, arg);  in ma35_pinconf_set()
970 			ret = ma35_pinconf_set_power_source(npctl, pin, arg);  in ma35_pinconf_set()
974 			return -EINVAL;  in ma35_pinconf_set()
992 	struct ma35_pin_setting *pin;  in ma35_pinctrl_parse_groups()  local
998 	grp->name = np->name;  in ma35_pinctrl_parse_groups()
1006 		return -EINVAL;  in ma35_pinctrl_parse_groups()
1008 	elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL);  in ma35_pinctrl_parse_groups()
1010 		return -ENOMEM;  in ma35_pinctrl_parse_groups()
1014 		return -EINVAL;  in ma35_pinctrl_parse_groups()
1016 	grp->npins = count / 3;  in ma35_pinctrl_parse_groups()
1018 	grp->pins = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);  in ma35_pinctrl_parse_groups()
1019 	if (!grp->pins)  in ma35_pinctrl_parse_groups()
1020 		return -ENOMEM;  in ma35_pinctrl_parse_groups()
1022 	grp->settings = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->settings), GFP_KERNEL);  in ma35_pinctrl_parse_groups()
1023 	if (!grp->settings)  in ma35_pinctrl_parse_groups()
1024 		return -ENOMEM;  in ma35_pinctrl_parse_groups()
1026 	pin = grp->settings;  in ma35_pinctrl_parse_groups()
1029 		pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;  in ma35_pinctrl_parse_groups()
1030 		pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;  in ma35_pinctrl_parse_groups()
1031 		pin->muxval = elems[i + 2];  in ma35_pinctrl_parse_groups()
1032 		pin->configs = configs;  in ma35_pinctrl_parse_groups()
1033 		pin->nconfigs = nconfigs;  in ma35_pinctrl_parse_groups()
1034 		grp->pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);  in ma35_pinctrl_parse_groups()
1035 		pin++;  in ma35_pinctrl_parse_groups()
1049 	dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);  in ma35_pinctrl_parse_functions()
1051 	func = &npctl->functions[index];  in ma35_pinctrl_parse_functions()
1052 	func->name = np->name;  in ma35_pinctrl_parse_functions()
1053 	func->ngroups = of_get_child_count(np);  in ma35_pinctrl_parse_functions()
1055 	if (func->ngroups <= 0)  in ma35_pinctrl_parse_functions()
1058 	func->groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(char *), GFP_KERNEL);  in ma35_pinctrl_parse_functions()
1059 	if (!func->groups)  in ma35_pinctrl_parse_functions()
1060 		return -ENOMEM;  in ma35_pinctrl_parse_functions()
1063 		func->groups[i] = child->name;  in ma35_pinctrl_parse_functions()
1064 		grp = &npctl->groups[grp_index++];  in ma35_pinctrl_parse_functions()
1080 	device_for_each_child_node(&pdev->dev, child) {  in ma35_pinctrl_probe_dt()
1081 		if (fwnode_property_present(child, "gpio-controller"))  in ma35_pinctrl_probe_dt()
1083 		npctl->nfunctions++;  in ma35_pinctrl_probe_dt()
1084 		npctl->ngroups += of_get_child_count(to_of_node(child));  in ma35_pinctrl_probe_dt()
1087 	if (!npctl->nfunctions)  in ma35_pinctrl_probe_dt()
1088 		return -EINVAL;  in ma35_pinctrl_probe_dt()
1090 	npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions,  in ma35_pinctrl_probe_dt()
1091 					sizeof(*npctl->functions), GFP_KERNEL);  in ma35_pinctrl_probe_dt()
1092 	if (!npctl->functions)  in ma35_pinctrl_probe_dt()
1093 		return -ENOMEM;  in ma35_pinctrl_probe_dt()
1095 	npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups,  in ma35_pinctrl_probe_dt()
1096 				     sizeof(*npctl->groups), GFP_KERNEL);  in ma35_pinctrl_probe_dt()
1097 	if (!npctl->groups)  in ma35_pinctrl_probe_dt()
1098 		return -ENOMEM;  in ma35_pinctrl_probe_dt()
1100 	device_for_each_child_node(&pdev->dev, child) {  in ma35_pinctrl_probe_dt()
1101 		if (fwnode_property_present(child, "gpio-controller"))  in ma35_pinctrl_probe_dt()
1107 			dev_err(&pdev->dev, "failed to parse function\n");  in ma35_pinctrl_probe_dt()
1117 	struct device *dev = &pdev->dev;  in ma35_pinctrl_probe()
1121 	if (!info || !info->pins || !info->npins) {  in ma35_pinctrl_probe()
1122 		dev_err(&pdev->dev, "wrong pinctrl info\n");  in ma35_pinctrl_probe()
1123 		return -EINVAL;  in ma35_pinctrl_probe()
1126 	npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);  in ma35_pinctrl_probe()
1128 		return -ENOMEM;  in ma35_pinctrl_probe()
1130 	ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);  in ma35_pinctrl_probe()
1132 		return -ENOMEM;  in ma35_pinctrl_probe()
1134 	npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);  in ma35_pinctrl_probe()
1135 	if (!npctl->ctrl)  in ma35_pinctrl_probe()
1136 		return -ENOMEM;  in ma35_pinctrl_probe()
1138 	ma35_pinctrl_desc->name = dev_name(&pdev->dev);  in ma35_pinctrl_probe()
1139 	ma35_pinctrl_desc->pins = info->pins;  in ma35_pinctrl_probe()
1140 	ma35_pinctrl_desc->npins = info->npins;  in ma35_pinctrl_probe()
1141 	ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;  in ma35_pinctrl_probe()
1142 	ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;  in ma35_pinctrl_probe()
1143 	ma35_pinctrl_desc->confops = &ma35_pinconf_ops;  in ma35_pinctrl_probe()
1144 	ma35_pinctrl_desc->owner = THIS_MODULE;  in ma35_pinctrl_probe()
1146 	npctl->info = info;  in ma35_pinctrl_probe()
1147 	npctl->dev = &pdev->dev;  in ma35_pinctrl_probe()
1149 	npctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "nuvoton,sys");  in ma35_pinctrl_probe()
1150 	if (IS_ERR(npctl->regmap))  in ma35_pinctrl_probe()
1151 		return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),  in ma35_pinctrl_probe()
1156 		return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n");  in ma35_pinctrl_probe()
1162 		return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");  in ma35_pinctrl_probe()
1164 	ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl);  in ma35_pinctrl_probe()
1166 		return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");  in ma35_pinctrl_probe()
1168 	ret = pinctrl_enable(npctl->pctl);  in ma35_pinctrl_probe()
1170 		return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");  in ma35_pinctrl_probe()
1179 	return pinctrl_force_sleep(npctl->pctl);  in ma35_pinctrl_suspend()
1186 	return pinctrl_force_default(npctl->pctl);  in ma35_pinctrl_resume()