Lines Matching +full:gpio +full:- +full:bank
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shan-Chun Hung <schung@nuvoton.com>
13 #include <linux/gpio/driver.h>
24 #include "pinctrl-ma35.h"
33 /* GPIO control registers */
50 /* GPIO mode control */
59 /* GPIO pull-up and pull-down selection control */
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
86 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
149 return npctl->ngroups;
156 return npctl->groups[selector].grp.name;
164 if (selector >= npctl->ngroups)
165 return -EINVAL;
167 *pins = npctl->groups[selector].grp.pins;
168 *npins = npctl->groups[selector].grp.npins;
178 for (i = 0; i < npctl->ngroups; i++) {
179 if (!strcmp(npctl->groups[i].grp.name, name))
180 return &npctl->groups[i];
202 grp = ma35_pinctrl_find_group_by_name(npctl, np->name);
204 dev_err(npctl->dev, "unable to find group for node %s\n", np->name);
205 return -EINVAL;
208 map_num += grp->grp.npins;
211 return -ENOMEM;
218 return -EINVAL;
220 setting = grp->data;
223 new_map[0].data.mux.function = parent->name;
224 new_map[0].data.mux.group = np->name;
228 for (i = 0; i < grp->grp.npins; i++) {
230 new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->grp.pins[i]);
234 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
235 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
252 return npctl->nfunctions;
260 return npctl->functions[selector].name;
270 *groups = npctl->functions[function].groups;
271 *num_groups = npctl->functions[function].ngroups;
280 struct group_desc *grp = &npctl->groups[group];
281 struct ma35_pin_setting *setting = grp->data;
284 dev_dbg(npctl->dev, "enable function %s group %s\n",
285 npctl->functions[selector].name, grp->grp.name);
287 for (i = 0; i < grp->grp.npins; i++) {
288 regmap_read(npctl->regmap, setting->offset, ®val);
289 regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,
290 setting->shift);
291 regval |= setting->muxval << setting->shift;
292 regmap_write(npctl->regmap, setting->offset, regval);
306 static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode)
310 regval &= ~MA35_GP_MODE_MASK(gpio);
311 regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode);
316 static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio)
320 return field_get(MA35_GP_MODE_MASK(gpio), regval);
323 static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio)
325 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
326 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
330 ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT);
335 static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val)
337 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
338 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
339 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
346 regval |= BIT(gpio);
348 regval &= ~BIT(gpio);
351 ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT);
356 static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio)
358 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
359 void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;
361 return !!(readl(reg_pin) & BIT(gpio));
364 static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
366 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
367 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
371 regval = readl(reg_dout) | BIT(gpio);
373 regval = readl(reg_dout) & ~BIT(gpio);
378 static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
380 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
383 if (gpio < 8) {
385 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;
386 bit_offs = gpio * MA35_MFP_BITS_PER_PORT;
389 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;
390 bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;
393 regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, ®val);
394 regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);
395 regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);
402 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
403 void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;
411 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
412 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
425 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
426 void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
427 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
431 bval = bank->irqtype & BIT(hwirq);
436 bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);
444 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
450 bank->irqtype &= ~BIT(hwirq);
451 bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);
456 bank->irqtype &= ~BIT(hwirq);
457 bank->irqinten |= MA35_GP_INTEN_H(hwirq);
458 bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);
463 bank->irqtype &= ~BIT(hwirq);
464 bank->irqinten |= MA35_GP_INTEN_L(hwirq);
465 bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);
468 return -EINVAL;
471 writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);
472 writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);
478 .name = "MA35-GPIO-IRQ",
491 struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));
492 struct irq_domain *irqdomain = bank->chip.irq.domain;
499 isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);
501 for_each_set_bit(offset, &isr, bank->nr_pins)
509 struct ma35_pin_ctrl *ctrl = npctl->ctrl;
510 struct ma35_pin_bank *bank = ctrl->pin_banks;
514 for (i = 0; i < ctrl->nr_banks; i++, bank++) {
515 if (!bank->valid) {
516 dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);
519 bank->irqtype = 0;
520 bank->irqinten = 0;
521 bank->chip.label = bank->name;
522 bank->chip.parent = &pdev->dev;
523 bank->chip.request = ma35_gpio_core_to_request;
524 bank->chip.direction_input = ma35_gpio_core_direction_in;
525 bank->chip.direction_output = ma35_gpio_core_direction_out;
526 bank->chip.get = ma35_gpio_core_get;
527 bank->chip.set = ma35_gpio_core_set;
528 bank->chip.base = -1;
529 bank->chip.ngpio = bank->nr_pins;
530 bank->chip.can_sleep = false;
532 if (bank->irq > 0) {
535 girq = &bank->chip.irq;
537 girq->parent_handler = ma35_irq_demux_intgroup;
538 girq->num_parents = 1;
540 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
541 sizeof(*girq->parents), GFP_KERNEL);
542 if (!girq->parents)
543 return -ENOMEM;
545 girq->parents[0] = bank->irq;
546 girq->default_type = IRQ_TYPE_NONE;
547 girq->handler = handle_bad_irq;
550 ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
552 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
553 bank->chip.label, ret);
560 static int ma35_get_bank_data(struct ma35_pin_bank *bank)
562 bank->reg_base = fwnode_iomap(bank->fwnode, 0);
563 if (!bank->reg_base)
564 return -ENOMEM;
566 bank->irq = fwnode_irq_get(bank->fwnode, 0);
568 bank->nr_pins = MA35_GPIO_PORT_MAX;
570 bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);
571 if (IS_ERR(bank->clk))
572 return PTR_ERR(bank->clk);
574 return clk_prepare_enable(bank->clk);
581 struct ma35_pin_bank *bank;
584 ctrl = pctl->ctrl;
585 ctrl->nr_banks = MA35_GPIO_BANK_MAX;
587 ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,
588 sizeof(*ctrl->pin_banks), GFP_KERNEL);
589 if (!ctrl->pin_banks)
590 return -ENOMEM;
592 for (i = 0; i < ctrl->nr_banks; i++) {
593 ctrl->pin_banks[i].bank_num = i;
594 ctrl->pin_banks[i].name = gpio_group_name[i];
597 for_each_gpiochip_node(&pdev->dev, child) {
598 bank = &ctrl->pin_banks[id];
599 bank->fwnode = child;
600 bank->regmap = pctl->regmap;
601 bank->dev = &pdev->dev;
602 if (!ma35_get_bank_data(bank))
603 bank->valid = true;
624 base = npctl->ctrl->pin_banks[group_num].reg_base;
656 base = npctl->ctrl->pin_banks[group_num].reg_base;
672 base = npctl->ctrl->pin_banks[group_num].reg_base;
698 base = npctl->ctrl->pin_banks[group_num].reg_base;
712 base = npctl->ctrl->pin_banks[group_num].reg_base;
730 return -EINVAL;
733 base = npctl->ctrl->pin_banks[group_num].reg_base;
755 base = npctl->ctrl->pin_banks[group_num].reg_base;
773 int i, ds_val = -1;
791 if (ds_val == -1)
792 return -EINVAL;
795 base = npctl->ctrl->pin_banks[group_num].reg_base;
813 base = npctl->ctrl->pin_banks[group_num].reg_base;
827 base = npctl->ctrl->pin_banks[group_num].reg_base;
848 base = npctl->ctrl->pin_banks[group_num].reg_base;
862 base = npctl->ctrl->pin_banks[group_num].reg_base;
885 return -EINVAL;
912 return -EINVAL;
963 return -EINVAL;
995 return -EINVAL;
997 elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL);
999 return -ENOMEM;
1001 grp->grp.name = np->name;
1005 return -EINVAL;
1006 grp->grp.npins = count / 3;
1008 pins = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL);
1010 return -ENOMEM;
1011 grp->grp.pins = pins;
1013 pin = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL);
1015 return -ENOMEM;
1016 grp->data = pin;
1019 pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;
1020 pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;
1021 pin->muxval = elems[i + 2];
1022 pin->configs = configs;
1023 pin->nconfigs = nconfigs;
1024 pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);
1041 dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);
1043 func = &npctl->functions[index];
1044 func->name = np->name;
1045 func->ngroups = of_get_child_count(np);
1047 if (func->ngroups <= 0)
1050 groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(*groups), GFP_KERNEL);
1052 return -ENOMEM;
1057 groups[i] = node->name;
1058 grp = &npctl->groups[grp_index++];
1066 func->groups = groups;
1072 struct device *dev = &pdev->dev;
1078 npctl->nfunctions++;
1079 npctl->ngroups += of_get_child_count(to_of_node(child));
1082 if (!npctl->nfunctions)
1083 return -EINVAL;
1085 npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions,
1086 sizeof(*npctl->functions), GFP_KERNEL);
1087 if (!npctl->functions)
1088 return -ENOMEM;
1090 npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups,
1091 sizeof(*npctl->groups), GFP_KERNEL);
1092 if (!npctl->groups)
1093 return -ENOMEM;
1099 dev_err(&pdev->dev, "failed to parse function\n");
1109 struct device *dev = &pdev->dev;
1113 if (!info || !info->pins || !info->npins) {
1114 dev_err(&pdev->dev, "wrong pinctrl info\n");
1115 return -EINVAL;
1118 npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);
1120 return -ENOMEM;
1122 ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);
1124 return -ENOMEM;
1126 npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);
1127 if (!npctl->ctrl)
1128 return -ENOMEM;
1130 ma35_pinctrl_desc->name = dev_name(&pdev->dev);
1131 ma35_pinctrl_desc->pins = info->pins;
1132 ma35_pinctrl_desc->npins = info->npins;
1133 ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;
1134 ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;
1135 ma35_pinctrl_desc->confops = &ma35_pinconf_ops;
1136 ma35_pinctrl_desc->owner = THIS_MODULE;
1138 npctl->info = info;
1139 npctl->dev = &pdev->dev;
1141 npctl->regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sys");
1142 if (IS_ERR(npctl->regmap))
1143 return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),
1148 return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n");
1154 return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");
1156 ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl);
1158 return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");
1160 ret = pinctrl_enable(npctl->pctl);
1162 return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");
1171 return pinctrl_force_sleep(npctl->pctl);
1178 return pinctrl_force_default(npctl->pctl);