215 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_mode()  argument
220 	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);  in __nmk_gpio_set_mode()
221 	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);  in __nmk_gpio_set_mode()
226 	writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);  in __nmk_gpio_set_mode()
227 	writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);  in __nmk_gpio_set_mode()
230 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_pull()  argument
235 	pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);  in __nmk_gpio_set_pull()
238 		nmk_chip->pull_up &= ~BIT(offset);  in __nmk_gpio_set_pull()
243 	writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);  in __nmk_gpio_set_pull()
246 		nmk_chip->pull_up |= BIT(offset);  in __nmk_gpio_set_pull()
247 		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);  in __nmk_gpio_set_pull()
249 		nmk_chip->pull_up &= ~BIT(offset);  in __nmk_gpio_set_pull()
250 		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);  in __nmk_gpio_set_pull()
254 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_lowemi()  argument
257 	bool enabled = nmk_chip->lowemi & BIT(offset);  in __nmk_gpio_set_lowemi()
263 		nmk_chip->lowemi |= BIT(offset);  in __nmk_gpio_set_lowemi()
265 		nmk_chip->lowemi &= ~BIT(offset);  in __nmk_gpio_set_lowemi()
267 	writel_relaxed(nmk_chip->lowemi,  in __nmk_gpio_set_lowemi()
268 		       nmk_chip->addr + NMK_GPIO_LOWEMI);  in __nmk_gpio_set_lowemi()
271 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_make_input()  argument
274 	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);  in __nmk_gpio_make_input()
277 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_mode_safe()  argument
281 	u32 rwimsc = nmk_chip->rwimsc;  in __nmk_gpio_set_mode_safe()
282 	u32 fwimsc = nmk_chip->fwimsc;  in __nmk_gpio_set_mode_safe()
284 	if (glitch && nmk_chip->set_ioforce) {  in __nmk_gpio_set_mode_safe()
288 		writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);  in __nmk_gpio_set_mode_safe()
289 		writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);  in __nmk_gpio_set_mode_safe()
291 		nmk_chip->set_ioforce(true);  in __nmk_gpio_set_mode_safe()
294 	__nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);  in __nmk_gpio_set_mode_safe()
296 	if (glitch && nmk_chip->set_ioforce) {  in __nmk_gpio_set_mode_safe()
297 		nmk_chip->set_ioforce(false);  in __nmk_gpio_set_mode_safe()
299 		writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);  in __nmk_gpio_set_mode_safe()
300 		writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);  in __nmk_gpio_set_mode_safe()
305 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned int offset)  in nmk_gpio_disable_lazy_irq()  argument
307 	u32 falling = nmk_chip->fimsc & BIT(offset);  in nmk_gpio_disable_lazy_irq()
308 	u32 rising = nmk_chip->rimsc & BIT(offset);  in nmk_gpio_disable_lazy_irq()
309 	int gpio = nmk_chip->chip.base + offset;  in nmk_gpio_disable_lazy_irq()
310 	int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);  in nmk_gpio_disable_lazy_irq()
320 		nmk_chip->rimsc &= ~BIT(offset);  in nmk_gpio_disable_lazy_irq()
321 		writel_relaxed(nmk_chip->rimsc,  in nmk_gpio_disable_lazy_irq()
322 			       nmk_chip->addr + NMK_GPIO_RIMSC);  in nmk_gpio_disable_lazy_irq()
326 		nmk_chip->fimsc &= ~BIT(offset);  in nmk_gpio_disable_lazy_irq()
327 		writel_relaxed(nmk_chip->fimsc,  in nmk_gpio_disable_lazy_irq()
328 			       nmk_chip->addr + NMK_GPIO_FIMSC);  in nmk_gpio_disable_lazy_irq()
331 	dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);  in nmk_gpio_disable_lazy_irq()
913 			struct nmk_gpio_chip *nmk_chip;  in nmk_pmx_set()  local
916 			nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i], &bit);  in nmk_pmx_set()
917 			if (!nmk_chip) {  in nmk_pmx_set()
924 			slpm[nmk_chip->bank] &= ~BIT(bit);  in nmk_pmx_set()
930 		struct nmk_gpio_chip *nmk_chip;  in nmk_pmx_set()  local
933 		nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i], &bit);  in nmk_pmx_set()
934 		if (!nmk_chip) {  in nmk_pmx_set()
943 		clk_enable(nmk_chip->clk);  in nmk_pmx_set()
951 		nmk_gpio_disable_lazy_irq(nmk_chip, bit);  in nmk_pmx_set()
953 		__nmk_gpio_set_mode_safe(nmk_chip, bit,  in nmk_pmx_set()
955 		clk_disable(nmk_chip->clk);  in nmk_pmx_set()
988 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_request_enable()  local
1001 	nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_request_enable()
1007 	clk_enable(nmk_chip->clk);  in nmk_gpio_request_enable()
1009 	__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);  in nmk_gpio_request_enable()
1010 	clk_disable(nmk_chip->clk);  in nmk_gpio_request_enable()
1056 	struct nmk_gpio_chip *nmk_chip;  in nmk_pin_config_set()  local
1062 	nmk_chip = find_nmk_gpio_from_pin(pin, &bit);  in nmk_pin_config_set()
1063 	if (!nmk_chip) {  in nmk_pin_config_set()
1103 			dev_dbg(nmk_chip->chip.parent,  in nmk_pin_config_set()
1112 		dev_dbg(nmk_chip->chip.parent,  in nmk_pin_config_set()
1119 		clk_enable(nmk_chip->clk);  in nmk_pin_config_set()
1122 			__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);  in nmk_pin_config_set()
1124 			__nmk_gpio_make_output(nmk_chip, bit, val);  in nmk_pin_config_set()
1126 			__nmk_gpio_make_input(nmk_chip, bit);  in nmk_pin_config_set()
1127 			__nmk_gpio_set_pull(nmk_chip, bit, pull);  in nmk_pin_config_set()
1130 		__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);  in nmk_pin_config_set()
1132 		__nmk_gpio_set_slpm(nmk_chip, bit, slpm);  in nmk_pin_config_set()
1133 		clk_disable(nmk_chip->clk);  in nmk_pin_config_set()
1217 		struct nmk_gpio_chip *nmk_chip;  in nmk_pinctrl_probe()  local
1224 		nmk_chip = nmk_gpio_populate_chip(gpio_fwnode, pdev);  in nmk_pinctrl_probe()
1225 		if (IS_ERR(nmk_chip))  in nmk_pinctrl_probe()
1230 			BUG_ON(nmk_chip->is_mobileye_soc);  in nmk_pinctrl_probe()