Lines Matching refs:DRV_BASE
18 #define DRV_BASE 0xb00 macro
179 MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
180 MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
181 MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
182 MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
183 MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
184 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
185 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
186 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
187 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
188 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
189 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
190 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
191 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
192 MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
193 MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
194 MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
195 MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
204 MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
205 MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
206 MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
207 MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
208 MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
209 MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
210 MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
211 MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
212 MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
213 MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
214 MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
215 MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
216 MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
217 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
230 MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
231 MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
232 MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
233 MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
240 MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
241 MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
242 MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
243 MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
244 MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
245 MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
246 MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
247 MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
248 MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
249 MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
250 MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
251 MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
252 MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
253 MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
254 MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
255 MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
256 MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
257 MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
258 MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
259 MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
260 MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
261 MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
268 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
269 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
270 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
271 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
272 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
273 MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
274 MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
275 MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
276 MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
277 MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
278 MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
279 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
280 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
281 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
282 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
283 MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
284 MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
285 MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
286 MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
287 MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
288 MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
289 MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
290 MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
291 MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
292 MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)