1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/pinctrl/mt65xx.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinmux.h>
39 				.name = #id,				\
345 	const char *name;  member
681 		.name = "pon",
694 		.name = "pon_tod_1pps",
703 		.name = "gsw_tod_1pps",
716 		.name = "sipo",
725 		.name = "sipo_rclk",
738 		.name = "mdio",
757 		.name = "uart2",
766 		.name = "uart2_cts_rts",
775 		.name = "hsuart",
785 		.name = "hsuart_cts_rts",
794 		.name = "uart4",
803 		.name = "uart5",
816 		.name = "i2c1",
829 		.name = "jtag_udi",
838 		.name = "jtag_dfd",
851 		.name = "pcm1",
860 		.name = "pcm2",
873 		.name = "spi_quad",
882 		.name = "spi_cs1",
891 		.name = "spi_cs2",
900 		.name = "spi_cs3",
909 		.name = "spi_cs4",
922 		.name = "pcm_spi",
931 		.name = "pcm_spi_int",
940 		.name = "pcm_spi_rst",
949 		.name = "pcm_spi_cs1",
958 		.name = "pcm_spi_cs2_p128",
967 		.name = "pcm_spi_cs2_p156",
976 		.name = "pcm_spi_cs3",
985 		.name = "pcm_spi_cs4",
998 		.name = "i2s",
1011 		.name = "emmc",
1024 		.name = "pnand",
1037 		.name = "pcie_reset0",
1046 		.name = "pcie_reset1",
1055 		.name = "pcie_reset2",
1069 		.name = "gpio0",
1078 		.name = "gpio1",
1087 		.name = "gpio2",
1096 		.name = "gpio3",
1105 		.name = "gpio4",
1114 		.name = "gpio5",
1123 		.name = "gpio6",
1132 		.name = "gpio7",
1141 		.name = "gpio8",
1150 		.name = "gpio9",
1159 		.name = "gpio10",
1168 		.name = "gpio11",
1177 		.name = "gpio12",
1186 		.name = "gpio13",
1195 		.name = "gpio14",
1204 		.name = "gpio15",
1213 		.name = "gpio16",
1222 		.name = "gpio17",
1231 		.name = "gpio18",
1240 		.name = "gpio19",
1249 		.name = "gpio20",
1258 		.name = "gpio21",
1267 		.name = "gpio22",
1276 		.name = "gpio23",
1285 		.name = "gpio24",
1294 		.name = "gpio25",
1303 		.name = "gpio26",
1312 		.name = "gpio27",
1321 		.name = "gpio28",
1330 		.name = "gpio29",
1339 		.name = "gpio30",
1348 		.name = "gpio31",
1357 		.name = "gpio36",
1366 		.name = "gpio37",
1375 		.name = "gpio38",
1384 		.name = "gpio39",
1393 		.name = "gpio40",
1402 		.name = "gpio41",
1411 		.name = "gpio42",
1420 		.name = "gpio43",
1429 		.name = "gpio44",
1438 		.name = "gpio45",
1447 		.name = "gpio46",
1456 		.name = "gpio47",
1469 		.name = "gpio33",
1484 		.name = "gpio34",
1499 		.name = "gpio35",
1514 		.name = "gpio42",
1533 		.name = "gpio33",
1548 		.name = "gpio34",
1563 		.name = "gpio35",
1578 		.name = "gpio42",
1597 		.name = "gpio33",
1612 		.name = "gpio34",
1627 		.name = "gpio35",
1642 		.name = "gpio42",
1661 		.name = "gpio33",
1676 		.name = "gpio34",
1691 		.name = "gpio35",
1706 		.name = "gpio42",
1725 		.name = "gpio43",
1740 		.name = "gpio44",
1755 		.name = "gpio45",
1770 		.name = "gpio46",
1789 		.name = "gpio43",
1804 		.name = "gpio44",
1819 		.name = "gpio45",
1834 		.name = "gpio46",
1853 		.name = "gpio43",
1868 		.name = "gpio44",
1883 		.name = "gpio45",
1898 		.name = "gpio46",
1917 		.name = "gpio43",
1932 		.name = "gpio44",
1947 		.name = "gpio45",
1962 		.name = "gpio46",
2263 		return -EINVAL;  in airoha_convert_pin_to_reg_offset()
2265 	return pin - range->pin_base;  in airoha_convert_pin_to_reg_offset()
2272 	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);  in airoha_gpio_set()  local
2276 	regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.data[index],  in airoha_gpio_set()
2282 	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);  in airoha_gpio_get()  local
2287 	err = regmap_read(pinctrl->regmap,  in airoha_gpio_get()
2288 			  pinctrl->gpiochip.data[index], &val);  in airoha_gpio_get()
2310 	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;  in airoha_irq_unmask()
2311 	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;  in airoha_irq_unmask()
2314 	struct airoha_pinctrl *pinctrl;  in airoha_irq_unmask()  local
2318 	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))  in airoha_irq_unmask()
2321 	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);  in airoha_irq_unmask()
2322 	switch (gpiochip->irq_type[data->hwirq]) {  in airoha_irq_unmask()
2327 		regmap_update_bits(pinctrl->regmap, gpiochip->level[index],  in airoha_irq_unmask()
2334 		regmap_update_bits(pinctrl->regmap, gpiochip->edge[index],  in airoha_irq_unmask()
2338 		regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask);  in airoha_irq_unmask()
2347 	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;  in airoha_irq_mask()
2348 	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;  in airoha_irq_mask()
2351 	struct airoha_pinctrl *pinctrl;  in airoha_irq_mask()  local
2354 	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);  in airoha_irq_mask()
2356 	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);  in airoha_irq_mask()
2357 	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);  in airoha_irq_mask()
2365 	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))  in airoha_irq_type()
2366 		return -EINVAL;  in airoha_irq_type()
2369 		if (gpiochip->irq_type[data->hwirq])  in airoha_irq_type()
2374 	gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;  in airoha_irq_type()
2381 	struct airoha_pinctrl *pinctrl = data;  in airoha_irq_handler()  local
2386 		struct gpio_irq_chip *girq = &pinctrl->gpiochip.chip.irq;  in airoha_irq_handler()
2391 		if (regmap_read(pinctrl->regmap, pinctrl->gpiochip.status[i],  in airoha_irq_handler()
2399 			generic_handle_irq(irq_find_mapping(girq->domain,  in airoha_irq_handler()
2401 			regmap_write(pinctrl->regmap,  in airoha_irq_handler()
2402 				     pinctrl->gpiochip.status[i], BIT(irq));  in airoha_irq_handler()
2411 	.name = "airoha-gpio-irq",
2419 static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,  in airoha_pinctrl_add_gpiochip()  argument
2422 	struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;  in airoha_pinctrl_add_gpiochip()
2423 	struct gpio_chip *gc = &chip->chip;  in airoha_pinctrl_add_gpiochip()
2424 	struct gpio_irq_chip *girq = &gc->irq;  in airoha_pinctrl_add_gpiochip()
2425 	struct device *dev = &pdev->dev;  in airoha_pinctrl_add_gpiochip()
2428 	chip->data = gpio_data_regs;  in airoha_pinctrl_add_gpiochip()
2429 	chip->dir = gpio_dir_regs;  in airoha_pinctrl_add_gpiochip()
2430 	chip->out = gpio_out_regs;  in airoha_pinctrl_add_gpiochip()
2431 	chip->status = irq_status_regs;  in airoha_pinctrl_add_gpiochip()
2432 	chip->level = irq_level_regs;  in airoha_pinctrl_add_gpiochip()
2433 	chip->edge = irq_edge_regs;  in airoha_pinctrl_add_gpiochip()
2435 	gc->parent = dev;  in airoha_pinctrl_add_gpiochip()
2436 	gc->label = dev_name(dev);  in airoha_pinctrl_add_gpiochip()
2437 	gc->request = gpiochip_generic_request;  in airoha_pinctrl_add_gpiochip()
2438 	gc->free = gpiochip_generic_free;  in airoha_pinctrl_add_gpiochip()
2439 	gc->direction_input = pinctrl_gpio_direction_input;  in airoha_pinctrl_add_gpiochip()
2440 	gc->direction_output = airoha_gpio_direction_output;  in airoha_pinctrl_add_gpiochip()
2441 	gc->set = airoha_gpio_set;  in airoha_pinctrl_add_gpiochip()
2442 	gc->get = airoha_gpio_get;  in airoha_pinctrl_add_gpiochip()
2443 	gc->base = -1;  in airoha_pinctrl_add_gpiochip()
2444 	gc->ngpio = AIROHA_NUM_PINS;  in airoha_pinctrl_add_gpiochip()
2446 	girq->default_type = IRQ_TYPE_NONE;  in airoha_pinctrl_add_gpiochip()
2447 	girq->handler = handle_simple_irq;  in airoha_pinctrl_add_gpiochip()
2455 			       dev_name(dev), pinctrl);  in airoha_pinctrl_add_gpiochip()
2461 	return devm_gpiochip_add_data(dev, gc, pinctrl);  in airoha_pinctrl_add_gpiochip()
2469 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in airoha_pinmux_set_mux()  local
2477 		return -EINVAL;  in airoha_pinmux_set_mux()
2481 		return -EINVAL;  in airoha_pinmux_set_mux()
2483 	dev_dbg(pctrl_dev->dev, "enable function %s group %s\n",  in airoha_pinmux_set_mux()
2484 		desc->func.name, grp->grp.name);  in airoha_pinmux_set_mux()
2486 	func = desc->data;  in airoha_pinmux_set_mux()
2487 	for (i = 0; i < func->group_size; i++) {  in airoha_pinmux_set_mux()
2491 		group = &func->groups[i];  in airoha_pinmux_set_mux()
2492 		if (strcmp(group->name, grp->grp.name))  in airoha_pinmux_set_mux()
2495 		for (j = 0; j < group->regmap_size; j++) {  in airoha_pinmux_set_mux()
2496 			switch (group->regmap[j].mux) {  in airoha_pinmux_set_mux()
2499 				regmap_update_bits(pinctrl->regmap,  in airoha_pinmux_set_mux()
2500 						   group->regmap[j].offset,  in airoha_pinmux_set_mux()
2501 						   group->regmap[j].mask,  in airoha_pinmux_set_mux()
2502 						   group->regmap[j].val);  in airoha_pinmux_set_mux()
2505 				regmap_update_bits(pinctrl->chip_scu,  in airoha_pinmux_set_mux()
2506 						   group->regmap[j].offset,  in airoha_pinmux_set_mux()
2507 						   group->regmap[j].mask,  in airoha_pinmux_set_mux()
2508 						   group->regmap[j].val);  in airoha_pinmux_set_mux()
2515 	return -EINVAL;  in airoha_pinmux_set_mux()
2522 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in airoha_pinmux_set_direction()  local
2533 	err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],  in airoha_pinmux_set_direction()
2541 	return regmap_update_bits(pinctrl->regmap,  in airoha_pinmux_set_direction()
2542 				  pinctrl->gpiochip.dir[index], mask,  in airoha_pinmux_set_direction()
2570 static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,  in airoha_pinctrl_get_conf()  argument
2578 		return -EINVAL;  in airoha_pinctrl_get_conf()
2580 	if (regmap_read(pinctrl->chip_scu, reg->offset, val))  in airoha_pinctrl_get_conf()
2581 		return -EINVAL;  in airoha_pinctrl_get_conf()
2583 	*val = (*val & reg->mask) >> __ffs(reg->mask);  in airoha_pinctrl_get_conf()
2588 static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,  in airoha_pinctrl_set_conf()  argument
2596 		return -EINVAL;  in airoha_pinctrl_set_conf()
2599 	if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,  in airoha_pinctrl_set_conf()
2600 			       val << __ffs(reg->mask)))  in airoha_pinctrl_set_conf()
2601 		return -EINVAL;  in airoha_pinctrl_set_conf()
2606 #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\  argument
2607 	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
2610 #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)			\  argument
2611 	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
2614 #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)			\  argument
2615 	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
2618 #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)			\  argument
2619 	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
2622 #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)			\  argument
2623 	airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
2626 #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)			\  argument
2627 	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf,		\
2630 #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)			\  argument
2631 	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf,	\
2634 #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)			\  argument
2635 	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf,	\
2638 #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)			\  argument
2639 	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf,	\
2642 #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)			\  argument
2643 	airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf,	\
2649 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in airoha_pinconf_get_direction()  local
2659 	err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);  in airoha_pinconf_get_direction()
2670 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in airoha_pinconf_get()  local
2680 		if (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) ||  in airoha_pinconf_get()
2681 		    airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down))  in airoha_pinconf_get()
2682 			return -EINVAL;  in airoha_pinconf_get()
2686 			return -EINVAL;  in airoha_pinconf_get()
2689 			return -EINVAL;  in airoha_pinconf_get()
2691 			return -EINVAL;  in airoha_pinconf_get()
2699 		if (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) ||  in airoha_pinconf_get()
2700 		    airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4))  in airoha_pinconf_get()
2701 			return -EINVAL;  in airoha_pinconf_get()
2707 		if (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg))  in airoha_pinconf_get()
2708 			return -EINVAL;  in airoha_pinconf_get()
2714 			return -EINVAL;  in airoha_pinconf_get()
2719 		return -EOPNOTSUPP;  in airoha_pinconf_get()
2730 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in airoha_pinconf_set_pin_value()  local
2737 	airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value);  in airoha_pinconf_set_pin_value()
2746 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in airoha_pinconf_set()  local
2755 			airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);  in airoha_pinconf_set()
2756 			airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);  in airoha_pinconf_set()
2759 			airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);  in airoha_pinconf_set()
2760 			airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1);  in airoha_pinconf_set()
2763 			airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1);  in airoha_pinconf_set()
2764 			airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);  in airoha_pinconf_set()
2783 				return -EINVAL;  in airoha_pinconf_set()
2786 			airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2);  in airoha_pinconf_set()
2787 			airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4);  in airoha_pinconf_set()
2791 			airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg);  in airoha_pinconf_set()
2813 			return -EOPNOTSUPP;  in airoha_pinconf_set()
2830 			return -EOPNOTSUPP;  in airoha_pinconf_group_get()
2833 			return -EOPNOTSUPP;  in airoha_pinconf_group_get()
2878 	.name = KBUILD_MODNAME,
2889 	struct device *dev = &pdev->dev;  in airoha_pinctrl_probe()
2890 	struct airoha_pinctrl *pinctrl;  in airoha_pinctrl_probe()  local
2894 	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);  in airoha_pinctrl_probe()
2895 	if (!pinctrl)  in airoha_pinctrl_probe()
2896 		return -ENOMEM;  in airoha_pinctrl_probe()
2898 	pinctrl->regmap = device_node_to_regmap(dev->parent->of_node);  in airoha_pinctrl_probe()
2899 	if (IS_ERR(pinctrl->regmap))  in airoha_pinctrl_probe()
2900 		return PTR_ERR(pinctrl->regmap);  in airoha_pinctrl_probe()
2902 	map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");  in airoha_pinctrl_probe()
2906 	pinctrl->chip_scu = map;  in airoha_pinctrl_probe()
2909 					     pinctrl, &pinctrl->ctrl);  in airoha_pinctrl_probe()
2917 		err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,  in airoha_pinctrl_probe()
2918 						grp->pins, grp->npins,  in airoha_pinctrl_probe()
2921 			dev_err(&pdev->dev, "Failed to register group %s\n",  in airoha_pinctrl_probe()
2922 				grp->name);  in airoha_pinctrl_probe()
2932 		err = pinmux_generic_add_function(pinctrl->ctrl,  in airoha_pinctrl_probe()
2933 						  func->desc.func.name,  in airoha_pinctrl_probe()
2934 						  func->desc.func.groups,  in airoha_pinctrl_probe()
2935 						  func->desc.func.ngroups,  in airoha_pinctrl_probe()
2939 				func->desc.func.name);  in airoha_pinctrl_probe()
2944 	err = pinctrl_enable(pinctrl->ctrl);  in airoha_pinctrl_probe()
2948 	/* build gpio-chip */  in airoha_pinctrl_probe()
2949 	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);  in airoha_pinctrl_probe()
2953 	{ .compatible = "airoha,en7581-pinctrl" },
2961 		.name = "pinctrl-airoha",
2971 MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");