Lines Matching +full:gpio +full:- +full:pol
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2025 MediaTek Inc.
16 #include <linux/gpio/driver.h>
24 #include "mtk-eint.h"
45 .pol = 0x300,
73 unsigned int idx = eint->pins[eint_num].index; in mtk_eint_get_offset()
74 unsigned int inst = eint->pins[eint_num].instance; in mtk_eint_get_offset()
77 reg = eint->base[inst] + offset + (idx / 32 * 4); in mtk_eint_get_offset()
86 unsigned int bit = BIT(eint->pins[eint_num].index % 32); in mtk_eint_can_en_debounce()
88 eint->regs->sens); in mtk_eint_can_en_debounce()
95 if (eint->pins[eint_num].debounce && sens != MTK_EINT_EDGE_SENSITIVE) in mtk_eint_can_en_debounce()
105 unsigned int mask = BIT(eint->pins[hwirq].index & 0x1f); in mtk_eint_flip_edge()
106 unsigned int port = (eint->pins[hwirq].index >> 5) & eint->hw->port_mask; in mtk_eint_flip_edge()
107 void __iomem *reg = eint->base[eint->pins[hwirq].instance] + (port << 2); in mtk_eint_flip_edge()
109 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); in mtk_eint_flip_edge()
114 reg_offset = eint->regs->pol_clr; in mtk_eint_flip_edge()
116 reg_offset = eint->regs->pol_set; in mtk_eint_flip_edge()
119 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, in mtk_eint_flip_edge()
129 unsigned int idx = eint->pins[d->hwirq].index; in mtk_eint_mask()
130 unsigned int inst = eint->pins[d->hwirq].instance; in mtk_eint_mask()
132 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_mask()
133 eint->regs->mask_set); in mtk_eint_mask()
135 eint->cur_mask[inst][idx >> 5] &= ~mask; in mtk_eint_mask()
143 unsigned int idx = eint->pins[d->hwirq].index; in mtk_eint_unmask()
144 unsigned int inst = eint->pins[d->hwirq].instance; in mtk_eint_unmask()
146 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_unmask()
147 eint->regs->mask_clr); in mtk_eint_unmask()
149 eint->cur_mask[inst][idx >> 5] |= mask; in mtk_eint_unmask()
153 if (eint->pins[d->hwirq].dual_edge) in mtk_eint_unmask()
154 mtk_eint_flip_edge(eint, d->hwirq); in mtk_eint_unmask()
160 unsigned int bit = BIT(eint->pins[eint_num].index % 32); in mtk_eint_get_mask()
162 eint->regs->mask); in mtk_eint_get_mask()
170 unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f); in mtk_eint_ack()
171 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_ack()
172 eint->regs->ack); in mtk_eint_ack()
181 unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f); in mtk_eint_set_type()
186 dev_err(eint->dev, in mtk_eint_set_type()
188 d->irq, d->hwirq, type); in mtk_eint_set_type()
189 return -EINVAL; in mtk_eint_set_type()
193 eint->pins[d->hwirq].dual_edge = 1; in mtk_eint_set_type()
195 eint->pins[d->hwirq].dual_edge = 0; in mtk_eint_set_type()
197 if (!mtk_eint_get_mask(eint, d->hwirq)) { in mtk_eint_set_type()
205 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); in mtk_eint_set_type()
208 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set); in mtk_eint_set_type()
213 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr); in mtk_eint_set_type()
216 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set); in mtk_eint_set_type()
230 unsigned int idx = eint->pins[d->hwirq].index; in mtk_eint_irq_set_wake()
231 unsigned int inst = eint->pins[d->hwirq].instance; in mtk_eint_irq_set_wake()
236 eint->wake_mask[inst][port] |= BIT(shift); in mtk_eint_irq_set_wake()
238 eint->wake_mask[inst][port] &= ~BIT(shift); in mtk_eint_irq_set_wake()
249 for (inst = 0; inst < eint->nbase; inst++) { in mtk_eint_chip_write_mask()
250 port_num = DIV_ROUND_UP(eint->base_pin_num[inst], 32); in mtk_eint_chip_write_mask()
252 reg = eint->base[inst] + (port << 2); in mtk_eint_chip_write_mask()
253 writel_relaxed(~buf[inst][port], reg + eint->regs->mask_set); in mtk_eint_chip_write_mask()
254 writel_relaxed(buf[inst][port], reg + eint->regs->mask_clr); in mtk_eint_chip_write_mask()
266 err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, in mtk_eint_irq_request_resources()
269 dev_err(eint->dev, "Can not find pin\n"); in mtk_eint_irq_request_resources()
275 dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n", in mtk_eint_irq_request_resources()
280 err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq); in mtk_eint_irq_request_resources()
282 dev_err(eint->dev, "Can not eint mode\n"); in mtk_eint_irq_request_resources()
295 eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n, in mtk_eint_irq_release_resources()
302 .name = "mt-eint",
318 for (i = 0; i < eint->nbase; i++) { in mtk_eint_hw_init()
319 dom_reg = eint->base[i] + eint->regs->dom_en; in mtk_eint_hw_init()
320 mask_reg = eint->base[i] + eint->regs->mask_set; in mtk_eint_hw_init()
321 for (j = 0; j < eint->base_pin_num[i]; j += 32) { in mtk_eint_hw_init()
337 unsigned int inst = eint->pins[index].instance; in mtk_eint_debounce_process()
338 unsigned int idx = eint->pins[index].index; in mtk_eint_debounce_process()
340 ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_ctrl; in mtk_eint_debounce_process()
341 dbnc = readl(eint->base[inst] + ctrl_offset); in mtk_eint_debounce_process()
344 ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_set; in mtk_eint_debounce_process()
346 writel(rst, eint->base[inst] + ctrl_offset); in mtk_eint_debounce_process()
359 for (i = 0; i < eint->nbase; i++) { in mtk_eint_irq_handler()
360 for (j = 0; j < eint->base_pin_num[i]; j += 32) { in mtk_eint_irq_handler()
362 status = readl(eint->base[i] + port * 4 + eint->regs->stat); in mtk_eint_irq_handler()
367 eint_num = eint->pin_list[i][shift + j]; in mtk_eint_irq_handler()
375 if (eint->wake_mask[i][port] & mask && in mtk_eint_irq_handler()
376 !(eint->cur_mask[i][port] & mask)) { in mtk_eint_irq_handler()
378 eint->regs->mask_set); in mtk_eint_irq_handler()
382 dual_edge = eint->pins[eint_num].dual_edge; in mtk_eint_irq_handler()
385 * Clear soft-irq in case we raised it last in mtk_eint_irq_handler()
389 eint->regs->soft_clr); in mtk_eint_irq_handler()
393 eint->gpio_xlate->get_gpio_state(eint->pctl, in mtk_eint_irq_handler()
397 generic_handle_domain_irq(eint->domain, eint_num); in mtk_eint_irq_handler()
404 * interrupt, raised it through soft-irq. in mtk_eint_irq_handler()
408 eint->regs->soft_set); in mtk_eint_irq_handler()
413 if (eint->pins[eint_num].debounce) in mtk_eint_irq_handler()
423 mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask); in mtk_eint_do_suspend()
431 mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask); in mtk_eint_do_resume()
443 unsigned int inst = eint->pins[eint_num].instance; in mtk_eint_set_debounce()
444 unsigned int idx = eint->pins[eint_num].index; in mtk_eint_set_debounce()
447 if (!eint->hw->db_time) in mtk_eint_set_debounce()
448 return -EOPNOTSUPP; in mtk_eint_set_debounce()
450 virq = irq_find_mapping(eint->domain, eint_num); in mtk_eint_set_debounce()
454 set_offset = (idx / 4) * 4 + eint->regs->dbnc_set; in mtk_eint_set_debounce()
455 clr_offset = (idx / 4) * 4 + eint->regs->dbnc_clr; in mtk_eint_set_debounce()
458 return -EINVAL; in mtk_eint_set_debounce()
460 dbnc = eint->num_db_time; in mtk_eint_set_debounce()
461 for (i = 0; i < eint->num_db_time; i++) { in mtk_eint_set_debounce()
462 if (debounce <= eint->hw->db_time[i]) { in mtk_eint_set_debounce()
476 writel(clr_bit, eint->base[inst] + clr_offset); in mtk_eint_set_debounce()
481 writel(rst | bit, eint->base[inst] + set_offset); in mtk_eint_set_debounce()
499 irq = irq_find_mapping(eint->domain, eint_n); in mtk_eint_find_irq()
501 return -EINVAL; in mtk_eint_find_irq()
512 if (!eint->regs) in mtk_eint_do_init()
513 eint->regs = &mtk_generic_eint_regs; in mtk_eint_do_init()
515 eint->base_pin_num = devm_kmalloc_array(eint->dev, eint->nbase, sizeof(u16), in mtk_eint_do_init()
517 if (!eint->base_pin_num) in mtk_eint_do_init()
518 return -ENOMEM; in mtk_eint_do_init()
521 eint->pins = eint_pin; in mtk_eint_do_init()
522 for (i = 0; i < eint->hw->ap_num; i++) { in mtk_eint_do_init()
523 inst = eint->pins[i].instance; in mtk_eint_do_init()
524 if (inst >= eint->nbase) in mtk_eint_do_init()
526 eint->base_pin_num[inst]++; in mtk_eint_do_init()
529 size = eint->hw->ap_num * sizeof(struct mtk_eint_pin); in mtk_eint_do_init()
530 eint->pins = devm_kmalloc(eint->dev, size, GFP_KERNEL); in mtk_eint_do_init()
531 if (!eint->pins) in mtk_eint_do_init()
534 eint->base_pin_num[inst] = eint->hw->ap_num; in mtk_eint_do_init()
535 for (i = 0; i < eint->hw->ap_num; i++) { in mtk_eint_do_init()
536 eint->pins[i].instance = inst; in mtk_eint_do_init()
537 eint->pins[i].index = i; in mtk_eint_do_init()
538 eint->pins[i].debounce = (i < eint->hw->db_cnt) ? 1 : 0; in mtk_eint_do_init()
542 eint->pin_list = devm_kmalloc(eint->dev, eint->nbase * sizeof(u16 *), GFP_KERNEL); in mtk_eint_do_init()
543 if (!eint->pin_list) in mtk_eint_do_init()
546 eint->wake_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL); in mtk_eint_do_init()
547 if (!eint->wake_mask) in mtk_eint_do_init()
550 eint->cur_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL); in mtk_eint_do_init()
551 if (!eint->cur_mask) in mtk_eint_do_init()
554 for (i = 0; i < eint->nbase; i++) { in mtk_eint_do_init()
555 eint->pin_list[i] = devm_kzalloc(eint->dev, eint->base_pin_num[i] * sizeof(u16), in mtk_eint_do_init()
557 port = DIV_ROUND_UP(eint->base_pin_num[i], 32); in mtk_eint_do_init()
558 eint->wake_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL); in mtk_eint_do_init()
559 eint->cur_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL); in mtk_eint_do_init()
560 if (!eint->pin_list[i] || !eint->wake_mask[i] || !eint->cur_mask[i]) in mtk_eint_do_init()
564 eint->domain = irq_domain_create_linear(dev_fwnode(eint->dev), eint->hw->ap_num, in mtk_eint_do_init()
566 if (!eint->domain) in mtk_eint_do_init()
569 if (eint->hw->db_time) { in mtk_eint_do_init()
571 if (eint->hw->db_time[i] == 0) in mtk_eint_do_init()
573 eint->num_db_time = i; in mtk_eint_do_init()
577 for (i = 0; i < eint->hw->ap_num; i++) { in mtk_eint_do_init()
578 inst = eint->pins[i].instance; in mtk_eint_do_init()
579 if (inst >= eint->nbase) in mtk_eint_do_init()
581 eint->pin_list[inst][eint->pins[i].index] = i; in mtk_eint_do_init()
582 virq = irq_create_mapping(eint->domain, i); in mtk_eint_do_init()
588 irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler, in mtk_eint_do_init()
594 for (i = 0; i < eint->nbase; i++) { in mtk_eint_do_init()
595 if (eint->cur_mask[i]) in mtk_eint_do_init()
596 devm_kfree(eint->dev, eint->cur_mask[i]); in mtk_eint_do_init()
597 if (eint->wake_mask[i]) in mtk_eint_do_init()
598 devm_kfree(eint->dev, eint->wake_mask[i]); in mtk_eint_do_init()
599 if (eint->pin_list[i]) in mtk_eint_do_init()
600 devm_kfree(eint->dev, eint->pin_list[i]); in mtk_eint_do_init()
602 devm_kfree(eint->dev, eint->cur_mask); in mtk_eint_do_init()
604 devm_kfree(eint->dev, eint->wake_mask); in mtk_eint_do_init()
606 devm_kfree(eint->dev, eint->pin_list); in mtk_eint_do_init()
609 devm_kfree(eint->dev, eint->pins); in mtk_eint_do_init()
611 devm_kfree(eint->dev, eint->base_pin_num); in mtk_eint_do_init()
612 return -ENOMEM; in mtk_eint_do_init()