Lines Matching +full:ena +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-intel.h"
180 * Lynxpoint gpios are controlled through both bitmapped registers and
182 * 3 x 32bit registers to cover all 95 GPIOs
185 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
190 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
191 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
192 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
207 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
221 offset -= comm->pin_base; in lp_gpio_reg()
230 return comm->regs + reg_offset + reg; in lp_gpio_reg()
237 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); in lp_gpio_acpi_use()
252 return !!(value & BIT(offset - 8 + 0)); in lp_gpio_ioxapic_use()
254 return !!(value & BIT(offset - 13 + 3)); in lp_gpio_ioxapic_use()
256 return !!(value & BIT(offset - 45 + 5)); in lp_gpio_ioxapic_use()
265 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_pin_dbg_show()
266 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_dbg_show()
294 const struct intel_pingroup *grp = &lg->soc->groups[group]; in lp_pinmux_set_mux()
297 guard(raw_spinlock_irqsave)(&lg->lock); in lp_pinmux_set_mux()
300 for (i = 0; i < grp->grp.npins; i++) { in lp_pinmux_set_mux()
301 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1); in lp_pinmux_set_mux()
307 if (grp->modes) in lp_pinmux_set_mux()
308 value |= grp->modes[i]; in lp_pinmux_set_mux()
310 value |= grp->mode; in lp_pinmux_set_mux()
333 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_gpio_request_enable()
334 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_gpio_request_enable()
337 guard(raw_spinlock_irqsave)(&lg->lock); in lp_gpio_request_enable()
346 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); in lp_gpio_request_enable()
360 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_gpio_disable_free()
362 guard(raw_spinlock_irqsave)(&lg->lock); in lp_gpio_disable_free()
373 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_gpio_set_direction()
376 guard(raw_spinlock_irqsave)(&lg->lock); in lp_gpio_set_direction()
389 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), in lp_gpio_set_direction()
411 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_config_get()
416 scoped_guard(raw_spinlock_irqsave, &lg->lock) in lp_pin_config_get()
424 return -EINVAL; in lp_pin_config_get()
429 return -EINVAL; in lp_pin_config_get()
435 return -EINVAL; in lp_pin_config_get()
440 return -ENOTSUPP; in lp_pin_config_get()
452 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_config_set()
457 guard(raw_spinlock_irqsave)(&lg->lock); in lp_pin_config_set()
478 return -ENOTSUPP; in lp_pin_config_set()
511 guard(raw_spinlock_irqsave)(&lg->lock); in lp_gpio_set()
550 void __iomem *reg, *ena; in lp_gpio_irq_handler() local
557 for (base = 0; base < lg->chip.ngpio; base += 32) { in lp_gpio_irq_handler()
558 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); in lp_gpio_irq_handler()
559 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); in lp_gpio_irq_handler()
562 pending = ioread32(reg) & ioread32(ena); in lp_gpio_irq_handler()
565 generic_handle_domain_irq(lg->chip.irq.domain, base + pin); in lp_gpio_irq_handler()
576 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); in lp_irq_ack()
578 guard(raw_spinlock_irqsave)(&lg->lock); in lp_irq_ack()
596 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_enable()
600 scoped_guard(raw_spinlock_irqsave, &lg->lock) in lp_irq_enable()
609 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_disable()
611 scoped_guard(raw_spinlock_irqsave, &lg->lock) in lp_irq_disable()
625 reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); in lp_irq_set_type()
627 return -EINVAL; in lp_irq_set_type()
631 dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq); in lp_irq_set_type()
632 return -EBUSY; in lp_irq_set_type()
635 guard(raw_spinlock_irqsave)(&lg->lock); in lp_irq_set_type()
666 .name = "LP-GPIO",
683 for (base = 0; base < lg->chip.ngpio; base += 32) { in lp_gpio_irq_init_hw()
685 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); in lp_gpio_irq_init_hw()
688 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); in lp_gpio_irq_init_hw()
698 struct device *dev = lg->dev; in lp_gpio_add_pin_ranges()
701 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); in lp_gpio_add_pin_ranges()
713 struct device *dev = &pdev->dev; in lp_gpio_probe()
721 return -ENODEV; in lp_gpio_probe()
725 return -ENOMEM; in lp_gpio_probe()
727 lg->dev = dev; in lp_gpio_probe()
728 lg->soc = soc; in lp_gpio_probe()
730 lg->ncommunities = lg->soc->ncommunities; in lp_gpio_probe()
731 lg->communities = devm_kcalloc(dev, lg->ncommunities, in lp_gpio_probe()
732 sizeof(*lg->communities), GFP_KERNEL); in lp_gpio_probe()
733 if (!lg->communities) in lp_gpio_probe()
734 return -ENOMEM; in lp_gpio_probe()
736 lg->pctldesc = lptlp_pinctrl_desc; in lp_gpio_probe()
737 lg->pctldesc.name = dev_name(dev); in lp_gpio_probe()
738 lg->pctldesc.pins = lg->soc->pins; in lp_gpio_probe()
739 lg->pctldesc.npins = lg->soc->npins; in lp_gpio_probe()
741 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); in lp_gpio_probe()
742 if (IS_ERR(lg->pctldev)) { in lp_gpio_probe()
744 return PTR_ERR(lg->pctldev); in lp_gpio_probe()
752 return -EINVAL; in lp_gpio_probe()
755 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); in lp_gpio_probe()
758 return -EBUSY; in lp_gpio_probe()
761 for (i = 0; i < lg->soc->ncommunities; i++) { in lp_gpio_probe()
762 struct intel_community *comm = &lg->communities[i]; in lp_gpio_probe()
764 *comm = lg->soc->communities[i]; in lp_gpio_probe()
766 comm->regs = regs; in lp_gpio_probe()
767 comm->pad_regs = regs + 0x100; in lp_gpio_probe()
770 raw_spin_lock_init(&lg->lock); in lp_gpio_probe()
772 gc = &lg->chip; in lp_gpio_probe()
773 gc->label = dev_name(dev); in lp_gpio_probe()
774 gc->owner = THIS_MODULE; in lp_gpio_probe()
775 gc->request = gpiochip_generic_request; in lp_gpio_probe()
776 gc->free = gpiochip_generic_free; in lp_gpio_probe()
777 gc->direction_input = lp_gpio_direction_input; in lp_gpio_probe()
778 gc->direction_output = lp_gpio_direction_output; in lp_gpio_probe()
779 gc->get = lp_gpio_get; in lp_gpio_probe()
780 gc->set = lp_gpio_set; in lp_gpio_probe()
781 gc->set_config = gpiochip_generic_config; in lp_gpio_probe()
782 gc->get_direction = lp_gpio_get_direction; in lp_gpio_probe()
783 gc->base = -1; in lp_gpio_probe()
784 gc->ngpio = LP_NUM_GPIO; in lp_gpio_probe()
785 gc->can_sleep = false; in lp_gpio_probe()
786 gc->add_pin_ranges = lp_gpio_add_pin_ranges; in lp_gpio_probe()
787 gc->parent = dev; in lp_gpio_probe()
794 girq = &gc->irq; in lp_gpio_probe()
796 girq->init_hw = lp_gpio_irq_init_hw; in lp_gpio_probe()
797 girq->parent_handler = lp_gpio_irq_handler; in lp_gpio_probe()
798 girq->num_parents = 1; in lp_gpio_probe()
799 girq->parents = devm_kcalloc(dev, girq->num_parents, in lp_gpio_probe()
800 sizeof(*girq->parents), in lp_gpio_probe()
802 if (!girq->parents) in lp_gpio_probe()
803 return -ENOMEM; in lp_gpio_probe()
804 girq->parents[0] = irq; in lp_gpio_probe()
805 girq->default_type = IRQ_TYPE_NONE; in lp_gpio_probe()
806 girq->handler = handle_bad_irq; in lp_gpio_probe()
811 dev_err(dev, "failed adding lp-gpio chip\n"); in lp_gpio_probe()
821 struct gpio_chip *chip = &lg->chip; in lp_gpio_resume()
825 /* on some hardware suspend clears input sensing, re-enable it here */ in lp_gpio_resume()