1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (c) 2012-2013, Intel Corporation
28 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-intel.h"
570 	offset -= comm->pin_base;  in byt_gpio_reg()
579 		reg_offset = comm->pad_map[offset] * 16;  in byt_gpio_reg()
583 	return comm->pad_regs + reg_offset + reg;  in byt_gpio_reg()
606 			dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",  in byt_set_group_simple_mux()
632 			dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",  in byt_set_group_mixed_mux()
648 	const struct intel_function func = vg->soc->functions[func_selector];  in byt_set_mux()
649 	const struct intel_pingroup group = vg->soc->groups[group_selector];  in byt_set_mux()
663 	/* SCORE pin 92-93 */  in byt_get_gpio_mux()
664 	if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&  in byt_get_gpio_mux()
668 	/* SUS pin 11-21 */  in byt_get_gpio_mux()
669 	if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&  in byt_get_gpio_mux()
685 	/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */  in byt_gpio_clear_triggering()
720 	dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);  in byt_gpio_request_enable()
746 		dev_info_once(vg->dev,  in byt_gpio_direct_irq_check()
821 		return -EINVAL;  in byt_set_pull_strength()
838 	 * chip is not in input mode, set it and warn about it.  in byt_gpio_force_input_mode()
842 	dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);  in byt_gpio_force_input_mode()
866 			return -EINVAL;  in byt_pin_config_get()
871 			return -EINVAL;  in byt_pin_config_get()
879 			return -EINVAL;  in byt_pin_config_get()
886 			return -EINVAL;  in byt_pin_config_get()
914 			return -EINVAL;  in byt_pin_config_get()
919 		return -ENOTSUPP;  in byt_pin_config_get()
999 				return -EINVAL;  in byt_pin_config_set()
1014 			return -ENOTSUPP;  in byt_pin_config_set()
1075 		return -EINVAL;  in byt_gpio_get_direction()
1085 	return -EINVAL;  in byt_gpio_get_direction()
1139 	for (i = 0; i < vg->soc->npins; i++) {  in byt_gpio_dbg_show()
1146 		pin = vg->soc->pins[i].number;  in byt_gpio_dbg_show()
1200 			   " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",  in byt_gpio_dbg_show()
1206 			   comm->pad_map[i], comm->pad_map[i] * 16,  in byt_gpio_dbg_show()
1210 			   conf0 & BYT_TRIG_LVL ? " level" : "      ");  in byt_gpio_dbg_show()
1213 			seq_printf(s, " %-4s %-3s", pull, pull_str);  in byt_gpio_dbg_show()
1218 			seq_puts(s, " open-drain");  in byt_gpio_dbg_show()
1311 		return -EINVAL;  in byt_irq_type()
1317 	WARN(value & BYT_DIRECT_IRQ_EN,  in byt_irq_type()
1320 	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits  in byt_irq_type()
1321 	 * are used to indicate high and low level triggering  in byt_irq_type()
1340 	.name		= "BYT-GPIO",
1359 	for (base = 0; base < vg->chip.ngpio; base += 32) {  in byt_gpio_irq_handler()
1363 			dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);  in byt_gpio_irq_handler()
1370 			generic_handle_domain_irq(vg->chip.irq.domain, base + pin);  in byt_gpio_irq_handler()
1372 	chip->irq_eoi(data);  in byt_gpio_irq_handler()
1381 	memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,  in byt_direct_irq_sanity_check()
1385 		dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);  in byt_direct_irq_sanity_check()
1389 	direct_irq = match - direct_irq_mux;  in byt_direct_irq_sanity_check()
1390 	/* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */  in byt_direct_irq_sanity_check()
1391 	ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;  in byt_direct_irq_sanity_check()
1392 	dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,  in byt_direct_irq_sanity_check()
1397 	 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ  in byt_direct_irq_sanity_check()
1399 	 * 0x800, to one of the IO-APIC pins according to the mux registers.  in byt_direct_irq_sanity_check()
1404 	 *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,  in byt_direct_irq_sanity_check()
1405 	 *    selecting edge mode operation then on the first edge the IO-APIC pin goes  in byt_direct_irq_sanity_check()
1406 	 *    high, but since no write-to-clear write will be done to the IRQ status reg  in byt_direct_irq_sanity_check()
1412 		dev_warn(vg->dev,  in byt_direct_irq_sanity_check()
1435 	for (i = 0; i < vg->soc->npins; i++) {  in byt_init_irq_valid_mask()
1436 		unsigned int pin = vg->soc->pins[i].number;  in byt_init_irq_valid_mask()
1440 			dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);  in byt_init_irq_valid_mask()
1455 			dev_dbg(vg->dev, "disabling GPIO %d\n", i);  in byt_init_irq_valid_mask()
1467 	for (base = 0; base < vg->soc->npins; base += 32) {  in byt_gpio_irq_init_hw()
1471 			dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);  in byt_gpio_irq_init_hw()
1480 			dev_err(vg->dev,  in byt_gpio_irq_init_hw()
1491 	struct device *dev = vg->dev;  in byt_gpio_add_pin_ranges()
1494 	ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);  in byt_gpio_add_pin_ranges()
1503 	struct platform_device *pdev = to_platform_device(vg->dev);  in byt_gpio_probe()
1508 	vg->chip	= byt_gpio_chip;  in byt_gpio_probe()
1509 	gc		= &vg->chip;  in byt_gpio_probe()
1510 	gc->label	= dev_name(vg->dev);  in byt_gpio_probe()
1511 	gc->base	= -1;  in byt_gpio_probe()
1512 	gc->can_sleep	= false;  in byt_gpio_probe()
1513 	gc->add_pin_ranges = byt_gpio_add_pin_ranges;  in byt_gpio_probe()
1514 	gc->parent	= vg->dev;  in byt_gpio_probe()
1515 	gc->ngpio	= vg->soc->npins;  in byt_gpio_probe()
1518 	vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),  in byt_gpio_probe()
1520 	if (!vg->context.pads)  in byt_gpio_probe()
1521 		return -ENOMEM;  in byt_gpio_probe()
1529 		girq = &gc->irq;  in byt_gpio_probe()
1531 		girq->init_hw = byt_gpio_irq_init_hw;  in byt_gpio_probe()
1532 		girq->init_valid_mask = byt_init_irq_valid_mask;  in byt_gpio_probe()
1533 		girq->parent_handler = byt_gpio_irq_handler;  in byt_gpio_probe()
1534 		girq->num_parents = 1;  in byt_gpio_probe()
1535 		girq->parents = devm_kcalloc(vg->dev, girq->num_parents,  in byt_gpio_probe()
1536 					     sizeof(*girq->parents), GFP_KERNEL);  in byt_gpio_probe()
1537 		if (!girq->parents)  in byt_gpio_probe()
1538 			return -ENOMEM;  in byt_gpio_probe()
1539 		girq->parents[0] = irq;  in byt_gpio_probe()
1540 		girq->default_type = IRQ_TYPE_NONE;  in byt_gpio_probe()
1541 		girq->handler = handle_bad_irq;  in byt_gpio_probe()
1544 	ret = devm_gpiochip_add_data(vg->dev, gc, vg);  in byt_gpio_probe()
1546 		dev_err(vg->dev, "failed adding byt-gpio chip\n");  in byt_gpio_probe()
1552 			    const struct intel_pinctrl_soc_data *soc)  in byt_set_soc_data()  argument
1554 	struct platform_device *pdev = to_platform_device(vg->dev);  in byt_set_soc_data()
1557 	vg->soc = soc;  in byt_set_soc_data()
1559 	vg->ncommunities = vg->soc->ncommunities;  in byt_set_soc_data()
1560 	vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,  in byt_set_soc_data()
1561 				       sizeof(*vg->communities), GFP_KERNEL);  in byt_set_soc_data()
1562 	if (!vg->communities)  in byt_set_soc_data()
1563 		return -ENOMEM;  in byt_set_soc_data()
1565 	for (i = 0; i < vg->soc->ncommunities; i++) {  in byt_set_soc_data()
1566 		struct intel_community *comm = vg->communities + i;  in byt_set_soc_data()
1568 		*comm = vg->soc->communities[i];  in byt_set_soc_data()
1570 		comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);  in byt_set_soc_data()
1571 		if (IS_ERR(comm->pad_regs))  in byt_set_soc_data()
1572 			return PTR_ERR(comm->pad_regs);  in byt_set_soc_data()
1587 	struct device *dev = &pdev->dev;  in byt_pinctrl_probe()
1597 		return -ENOMEM;  in byt_pinctrl_probe()
1599 	vg->dev = dev;  in byt_pinctrl_probe()
1602 		dev_err(dev, "failed to set soc data\n");  in byt_pinctrl_probe()
1606 	vg->pctldesc		= byt_pinctrl_desc;  in byt_pinctrl_probe()
1607 	vg->pctldesc.name	= dev_name(dev);  in byt_pinctrl_probe()
1608 	vg->pctldesc.pins	= vg->soc->pins;  in byt_pinctrl_probe()
1609 	vg->pctldesc.npins	= vg->soc->npins;  in byt_pinctrl_probe()
1611 	vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);  in byt_pinctrl_probe()
1612 	if (IS_ERR(vg->pctldev)) {  in byt_pinctrl_probe()
1614 		return PTR_ERR(vg->pctldev);  in byt_pinctrl_probe()
1633 	for (i = 0; i < vg->soc->npins; i++) {  in byt_gpio_suspend()
1636 		unsigned int pin = vg->soc->pins[i].number;  in byt_gpio_suspend()
1640 			dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);  in byt_gpio_suspend()
1644 		vg->context.pads[i].conf0 = value;  in byt_gpio_suspend()
1648 			dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);  in byt_gpio_suspend()
1652 		vg->context.pads[i].val = value;  in byt_gpio_suspend()
1665 	for (i = 0; i < vg->soc->npins; i++) {  in byt_gpio_resume()
1668 		unsigned int pin = vg->soc->pins[i].number;  in byt_gpio_resume()
1672 			dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);  in byt_gpio_resume()
1677 		     vg->context.pads[i].conf0) {  in byt_gpio_resume()
1679 			value |= vg->context.pads[i].conf0;  in byt_gpio_resume()
1686 			dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);  in byt_gpio_resume()
1691 		     vg->context.pads[i].val) {  in byt_gpio_resume()
1695 			v |= vg->context.pads[i].val;  in byt_gpio_resume()