Lines Matching +full:dev +full:- +full:active +full:- +full:grp
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013, Intel Corporation
28 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-intel.h"
65 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
66 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
570 offset -= comm->pin_base; in byt_gpio_reg()
579 reg_offset = comm->pad_map[offset] * 16; in byt_gpio_reg()
583 return comm->pad_regs + reg_offset + reg; in byt_gpio_reg()
600 for (i = 0; i < group.grp.npins; i++) { in byt_set_group_simple_mux()
604 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); in byt_set_group_simple_mux()
606 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", in byt_set_group_simple_mux()
607 group.grp.name, i); in byt_set_group_simple_mux()
626 for (i = 0; i < group.grp.npins; i++) { in byt_set_group_mixed_mux()
630 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); in byt_set_group_mixed_mux()
632 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", in byt_set_group_mixed_mux()
633 group.grp.name, i); in byt_set_group_mixed_mux()
648 const struct intel_function func = vg->soc->functions[func_selector]; in byt_set_mux()
649 const struct intel_pingroup group = vg->soc->groups[group_selector]; in byt_set_mux()
663 /* SCORE pin 92-93 */ in byt_get_gpio_mux()
664 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && in byt_get_gpio_mux()
668 /* SUS pin 11-21 */ in byt_get_gpio_mux()
669 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && in byt_get_gpio_mux()
685 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ in byt_gpio_clear_triggering()
720 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); in byt_gpio_request_enable()
746 dev_info_once(vg->dev, in byt_gpio_direct_irq_check()
821 return -EINVAL; in byt_set_pull_strength()
842 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); in byt_gpio_force_input_mode()
866 return -EINVAL; in byt_pin_config_get()
871 return -EINVAL; in byt_pin_config_get()
879 return -EINVAL; in byt_pin_config_get()
886 return -EINVAL; in byt_pin_config_get()
914 return -EINVAL; in byt_pin_config_get()
919 return -ENOTSUPP; in byt_pin_config_get()
999 return -EINVAL; in byt_pin_config_set()
1014 return -ENOTSUPP; in byt_pin_config_set()
1056 return -EINVAL; in byt_gpio_set()
1077 return -EINVAL; in byt_gpio_get_direction()
1087 return -EINVAL; in byt_gpio_get_direction()
1141 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_dbg_show()
1148 pin = vg->soc->pins[i].number; in byt_gpio_dbg_show()
1202 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", in byt_gpio_dbg_show()
1208 comm->pad_map[i], comm->pad_map[i] * 16, in byt_gpio_dbg_show()
1215 seq_printf(s, " %-4s %-3s", pull, pull_str); in byt_gpio_dbg_show()
1220 seq_puts(s, " open-drain"); in byt_gpio_dbg_show()
1313 return -EINVAL; in byt_irq_type()
1342 .name = "BYT-GPIO",
1363 for (base = 0; base < vg->chip.ngpio; base += 32) { in byt_gpio_irq_handler()
1367 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); in byt_gpio_irq_handler()
1374 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); in byt_gpio_irq_handler()
1386 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, in byt_direct_irq_sanity_check()
1390 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); in byt_direct_irq_sanity_check()
1394 direct_irq = match - direct_irq_mux; in byt_direct_irq_sanity_check()
1395 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ in byt_direct_irq_sanity_check()
1396 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; in byt_direct_irq_sanity_check()
1397 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, in byt_direct_irq_sanity_check()
1402 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ in byt_direct_irq_sanity_check()
1404 * 0x800, to one of the IO-APIC pins according to the mux registers. in byt_direct_irq_sanity_check()
1409 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, in byt_direct_irq_sanity_check()
1410 * selecting edge mode operation then on the first edge the IO-APIC pin goes in byt_direct_irq_sanity_check()
1411 * high, but since no write-to-clear write will be done to the IRQ status reg in byt_direct_irq_sanity_check()
1417 dev_warn(vg->dev, in byt_direct_irq_sanity_check()
1440 for (i = 0; i < vg->soc->npins; i++) { in byt_init_irq_valid_mask()
1441 unsigned int pin = vg->soc->pins[i].number; in byt_init_irq_valid_mask()
1445 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); in byt_init_irq_valid_mask()
1460 dev_dbg(vg->dev, "disabling GPIO %d\n", i); in byt_init_irq_valid_mask()
1472 for (base = 0; base < vg->soc->npins; base += 32) { in byt_gpio_irq_init_hw()
1476 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); in byt_gpio_irq_init_hw()
1485 dev_err(vg->dev, in byt_gpio_irq_init_hw()
1496 struct device *dev = vg->dev; in byt_gpio_add_pin_ranges() local
1499 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); in byt_gpio_add_pin_ranges()
1501 dev_err(dev, "failed to add GPIO pin range\n"); in byt_gpio_add_pin_ranges()
1508 struct platform_device *pdev = to_platform_device(vg->dev); in byt_gpio_probe()
1513 vg->chip = byt_gpio_chip; in byt_gpio_probe()
1514 gc = &vg->chip; in byt_gpio_probe()
1515 gc->label = dev_name(vg->dev); in byt_gpio_probe()
1516 gc->base = -1; in byt_gpio_probe()
1517 gc->can_sleep = false; in byt_gpio_probe()
1518 gc->add_pin_ranges = byt_gpio_add_pin_ranges; in byt_gpio_probe()
1519 gc->parent = vg->dev; in byt_gpio_probe()
1520 gc->ngpio = vg->soc->npins; in byt_gpio_probe()
1523 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), in byt_gpio_probe()
1525 if (!vg->context.pads) in byt_gpio_probe()
1526 return -ENOMEM; in byt_gpio_probe()
1534 girq = &gc->irq; in byt_gpio_probe()
1536 girq->init_hw = byt_gpio_irq_init_hw; in byt_gpio_probe()
1537 girq->init_valid_mask = byt_init_irq_valid_mask; in byt_gpio_probe()
1538 girq->parent_handler = byt_gpio_irq_handler; in byt_gpio_probe()
1539 girq->num_parents = 1; in byt_gpio_probe()
1540 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, in byt_gpio_probe()
1541 sizeof(*girq->parents), GFP_KERNEL); in byt_gpio_probe()
1542 if (!girq->parents) in byt_gpio_probe()
1543 return -ENOMEM; in byt_gpio_probe()
1544 girq->parents[0] = irq; in byt_gpio_probe()
1545 girq->default_type = IRQ_TYPE_NONE; in byt_gpio_probe()
1546 girq->handler = handle_bad_irq; in byt_gpio_probe()
1549 ret = devm_gpiochip_add_data(vg->dev, gc, vg); in byt_gpio_probe()
1551 dev_err(vg->dev, "failed adding byt-gpio chip\n"); in byt_gpio_probe()
1559 struct platform_device *pdev = to_platform_device(vg->dev); in byt_set_soc_data()
1562 vg->soc = soc; in byt_set_soc_data()
1564 vg->ncommunities = vg->soc->ncommunities; in byt_set_soc_data()
1565 vg->communities = devm_kmemdup_array(vg->dev, vg->soc->communities, vg->ncommunities, in byt_set_soc_data()
1566 sizeof(*vg->soc->communities), GFP_KERNEL); in byt_set_soc_data()
1567 if (!vg->communities) in byt_set_soc_data()
1568 return -ENOMEM; in byt_set_soc_data()
1570 for (i = 0; i < vg->soc->ncommunities; i++) { in byt_set_soc_data()
1571 struct intel_community *comm = vg->communities + i; in byt_set_soc_data()
1573 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); in byt_set_soc_data()
1574 if (IS_ERR(comm->pad_regs)) in byt_set_soc_data()
1575 return PTR_ERR(comm->pad_regs); in byt_set_soc_data()
1590 struct device *dev = &pdev->dev; in byt_pinctrl_probe() local
1598 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); in byt_pinctrl_probe()
1600 return -ENOMEM; in byt_pinctrl_probe()
1602 vg->dev = dev; in byt_pinctrl_probe()
1605 dev_err(dev, "failed to set soc data\n"); in byt_pinctrl_probe()
1609 vg->pctldesc = byt_pinctrl_desc; in byt_pinctrl_probe()
1610 vg->pctldesc.name = dev_name(dev); in byt_pinctrl_probe()
1611 vg->pctldesc.pins = vg->soc->pins; in byt_pinctrl_probe()
1612 vg->pctldesc.npins = vg->soc->npins; in byt_pinctrl_probe()
1614 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); in byt_pinctrl_probe()
1615 if (IS_ERR(vg->pctldev)) { in byt_pinctrl_probe()
1616 dev_err(dev, "failed to register pinctrl driver\n"); in byt_pinctrl_probe()
1617 return PTR_ERR(vg->pctldev); in byt_pinctrl_probe()
1629 static int byt_gpio_suspend(struct device *dev) in byt_gpio_suspend() argument
1631 struct intel_pinctrl *vg = dev_get_drvdata(dev); in byt_gpio_suspend()
1636 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_suspend()
1639 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_suspend()
1643 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); in byt_gpio_suspend()
1647 vg->context.pads[i].conf0 = value; in byt_gpio_suspend()
1651 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); in byt_gpio_suspend()
1655 vg->context.pads[i].val = value; in byt_gpio_suspend()
1661 static int byt_gpio_resume(struct device *dev) in byt_gpio_resume() argument
1663 struct intel_pinctrl *vg = dev_get_drvdata(dev); in byt_gpio_resume()
1668 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_resume()
1671 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_resume()
1675 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); in byt_gpio_resume()
1680 vg->context.pads[i].conf0) { in byt_gpio_resume()
1682 value |= vg->context.pads[i].conf0; in byt_gpio_resume()
1684 dev_info(dev, "restored pin %d CONF0 %#08x", i, value); in byt_gpio_resume()
1689 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); in byt_gpio_resume()
1694 vg->context.pads[i].val) { in byt_gpio_resume()
1698 v |= vg->context.pads[i].val; in byt_gpio_resume()
1701 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v); in byt_gpio_resume()