Lines Matching +full:gf +full:- +full:uart2 +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
20 #include <linux/pinctrl/pinconf-generic.h>
29 #include <dt-bindings/pinctrl/lochnagar.h>
31 #include "../pinctrl-utils.h"
35 #define LN_CDC_AIF1_STR "codec-aif1"
36 #define LN_CDC_AIF2_STR "codec-aif2"
37 #define LN_CDC_AIF3_STR "codec-aif3"
38 #define LN_DSP_AIF1_STR "dsp-aif1"
39 #define LN_DSP_AIF2_STR "dsp-aif2"
42 #define LN_GF_AIF1_STR "gf-aif1"
43 #define LN_GF_AIF2_STR "gf-aif2"
44 #define LN_GF_AIF3_STR "gf-aif3"
45 #define LN_GF_AIF4_STR "gf-aif4"
46 #define LN_SPDIF_AIF_STR "spdif-aif"
47 #define LN_USB_AIF1_STR "usb-aif1"
48 #define LN_USB_AIF2_STR "usb-aif2"
49 #define LN_ADAT_AIF_STR "adat-aif"
50 #define LN_SOUNDCARD_AIF_STR "soundcard-aif"
63 LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
64 LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
65 LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
66 LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
87 LN2_PIN_MUX(ID##_BCLK, LN_##ID##_STR"-bclk"); \
88 LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
89 LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
90 LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
202 LN1_PIN_GPIO(CDC_RESET, "codec-reset", RST, CDC_RESET, 1);
203 LN1_PIN_GPIO(DSP_RESET, "dsp-reset", RST, DSP_RESET, 1);
204 LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0);
205 LN1_PIN_MUX(GF_GPIO2, "gf-gpio2");
206 LN1_PIN_MUX(GF_GPIO3, "gf-gpio3");
207 LN1_PIN_MUX(GF_GPIO7, "gf-gpio7");
223 LN2_PIN_GPIO(CDC_RESET, "codec-reset", MINICARD_RESETS, CDC_RESET, 1);
224 LN2_PIN_GPIO(DSP_RESET, "dsp-reset", MINICARD_RESETS, DSP_RESET, 1);
225 LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4, CDC_CIF1MODE, 0);
226 LN2_PIN_GPIO(CDC_LDOENA, "codec-ldoena", POWER_CTRL, PWR_ENA, 0);
227 LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode", SPDIF_CTRL, SPDIF_HWMODE, 0);
228 LN2_PIN_GPIO(SPDIF_RESET, "spdif-reset", SPDIF_CTRL, SPDIF_RESET, 1);
229 LN2_PIN_MUX(FPGA_GPIO1, "fpga-gpio1");
230 LN2_PIN_MUX(FPGA_GPIO2, "fpga-gpio2");
231 LN2_PIN_MUX(FPGA_GPIO3, "fpga-gpio3");
232 LN2_PIN_MUX(FPGA_GPIO4, "fpga-gpio4");
233 LN2_PIN_MUX(FPGA_GPIO5, "fpga-gpio5");
234 LN2_PIN_MUX(FPGA_GPIO6, "fpga-gpio6");
235 LN2_PIN_MUX(CDC_GPIO1, "codec-gpio1");
236 LN2_PIN_MUX(CDC_GPIO2, "codec-gpio2");
237 LN2_PIN_MUX(CDC_GPIO3, "codec-gpio3");
238 LN2_PIN_MUX(CDC_GPIO4, "codec-gpio4");
239 LN2_PIN_MUX(CDC_GPIO5, "codec-gpio5");
240 LN2_PIN_MUX(CDC_GPIO6, "codec-gpio6");
241 LN2_PIN_MUX(CDC_GPIO7, "codec-gpio7");
242 LN2_PIN_MUX(CDC_GPIO8, "codec-gpio8");
243 LN2_PIN_MUX(DSP_GPIO1, "dsp-gpio1");
244 LN2_PIN_MUX(DSP_GPIO2, "dsp-gpio2");
245 LN2_PIN_MUX(DSP_GPIO3, "dsp-gpio3");
246 LN2_PIN_MUX(DSP_GPIO4, "dsp-gpio4");
247 LN2_PIN_MUX(DSP_GPIO5, "dsp-gpio5");
248 LN2_PIN_MUX(DSP_GPIO6, "dsp-gpio6");
249 LN2_PIN_MUX(GF_GPIO2, "gf-gpio2");
250 LN2_PIN_MUX(GF_GPIO3, "gf-gpio3");
251 LN2_PIN_MUX(GF_GPIO7, "gf-gpio7");
252 LN2_PIN_MUX(DSP_UART1_RX, "dsp-uart1-rx");
253 LN2_PIN_MUX(DSP_UART1_TX, "dsp-uart1-tx");
254 LN2_PIN_MUX(DSP_UART2_RX, "dsp-uart2-rx");
255 LN2_PIN_MUX(DSP_UART2_TX, "dsp-uart2-tx");
256 LN2_PIN_MUX(GF_UART2_RX, "gf-uart2-rx");
257 LN2_PIN_MUX(GF_UART2_TX, "gf-uart2-tx");
258 LN2_PIN_MUX(USB_UART_RX, "usb-uart-rx");
259 LN2_PIN_MUX(CDC_PDMCLK1, "codec-pdmclk1");
260 LN2_PIN_MUX(CDC_PDMDAT1, "codec-pdmdat1");
261 LN2_PIN_MUX(CDC_PDMCLK2, "codec-pdmclk2");
262 LN2_PIN_MUX(CDC_PDMDAT2, "codec-pdmdat2");
263 LN2_PIN_MUX(CDC_DMICCLK1, "codec-dmicclk1");
264 LN2_PIN_MUX(CDC_DMICDAT1, "codec-dmicdat1");
265 LN2_PIN_MUX(CDC_DMICCLK2, "codec-dmicclk2");
266 LN2_PIN_MUX(CDC_DMICDAT2, "codec-dmicdat2");
267 LN2_PIN_MUX(CDC_DMICCLK3, "codec-dmicclk3");
268 LN2_PIN_MUX(CDC_DMICDAT3, "codec-dmicdat3");
269 LN2_PIN_MUX(CDC_DMICCLK4, "codec-dmicclk4");
270 LN2_PIN_MUX(CDC_DMICDAT4, "codec-dmicdat4");
271 LN2_PIN_MUX(DSP_DMICCLK1, "dsp-dmicclk1");
272 LN2_PIN_MUX(DSP_DMICDAT1, "dsp-dmicdat1");
273 LN2_PIN_MUX(DSP_DMICCLK2, "dsp-dmicclk2");
274 LN2_PIN_MUX(DSP_DMICDAT2, "dsp-dmicdat2");
275 LN2_PIN_MUX(I2C2_SCL, "i2c2-scl");
276 LN2_PIN_MUX(I2C2_SDA, "i2c2-sda");
277 LN2_PIN_MUX(I2C3_SCL, "i2c3-scl");
278 LN2_PIN_MUX(I2C3_SDA, "i2c3-sda");
279 LN2_PIN_MUX(I2C4_SCL, "i2c4-scl");
280 LN2_PIN_MUX(I2C4_SDA, "i2c4-sda");
281 LN2_PIN_MUX(DSP_STANDBY, "dsp-standby");
282 LN2_PIN_MUX(CDC_MCLK1, "codec-mclk1");
283 LN2_PIN_MUX(CDC_MCLK2, "codec-mclk2");
284 LN2_PIN_MUX(DSP_CLKIN, "dsp-clkin");
285 LN2_PIN_MUX(PSIA1_MCLK, "psia1-mclk");
286 LN2_PIN_MUX(PSIA2_MCLK, "psia2-mclk");
287 LN2_PIN_MUX(GF_GPIO1, "gf-gpio1");
288 LN2_PIN_MUX(GF_GPIO5, "gf-gpio5");
289 LN2_PIN_MUX(DSP_GPIO20, "dsp-gpio20");
476 LN_FUNC("dsp-gpio1", PIN, 0x01),
477 LN_FUNC("dsp-gpio2", PIN, 0x02),
478 LN_FUNC("dsp-gpio3", PIN, 0x03),
479 LN_FUNC("codec-gpio1", PIN, 0x04),
480 LN_FUNC("codec-gpio2", PIN, 0x05),
481 LN_FUNC("codec-gpio3", PIN, 0x06),
482 LN_FUNC("codec-gpio4", PIN, 0x07),
483 LN_FUNC("codec-gpio5", PIN, 0x08),
484 LN_FUNC("codec-gpio6", PIN, 0x09),
485 LN_FUNC("codec-gpio7", PIN, 0x0A),
486 LN_FUNC("codec-gpio8", PIN, 0x0B),
533 LN_FUNC("codec-clkout", PIN, 0x20),
534 LN_FUNC("dsp-clkout", PIN, 0x21),
535 LN_FUNC("pmic-32k", PIN, 0x22),
536 LN_FUNC("spdif-clkout", PIN, 0x23),
537 LN_FUNC("clk-12m288", PIN, 0x24),
538 LN_FUNC("clk-11m2986", PIN, 0x25),
539 LN_FUNC("clk-24m576", PIN, 0x26),
540 LN_FUNC("clk-22m5792", PIN, 0x27),
541 LN_FUNC("xmos-mclk", PIN, 0x29),
542 LN_FUNC("gf-clkout1", PIN, 0x2A),
543 LN_FUNC("gf-mclk1", PIN, 0x2B),
544 LN_FUNC("gf-mclk3", PIN, 0x2C),
545 LN_FUNC("gf-mclk2", PIN, 0x2D),
546 LN_FUNC("gf-clkout2", PIN, 0x2E),
552 LN_FUNC("spdif-mclk", PIN, 0x34),
553 LN_FUNC("codec-irq", PIN, 0x42),
556 LN_FUNC("dsp-irq", PIN, 0x45),
581 LN_FUNC("usb-uart-tx", PIN, 0xC7),
731 return priv->ngroups; in lochnagar_get_groups_count()
739 return priv->groups[group_idx].name; in lochnagar_get_group_name()
749 *pins = priv->groups[group_idx].pins; in lochnagar_get_group_pins()
750 *num_pins = priv->groups[group_idx].npins; in lochnagar_get_group_pins()
767 return priv->nfuncs; in lochnagar_get_funcs_count()
775 return priv->funcs[func_idx].name; in lochnagar_get_func_name()
786 func_type = priv->funcs[func_idx].type; in lochnagar_get_func_groups()
788 *groups = priv->func_groups[func_type].groups; in lochnagar_get_func_groups()
789 *num_groups = priv->func_groups[func_type].ngroups; in lochnagar_get_func_groups()
797 struct regmap *regmap = priv->lochnagar->regmap; in lochnagar2_get_gpio_chan()
799 int free = -1; in lochnagar2_get_gpio_chan()
825 dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op); in lochnagar2_get_gpio_chan()
830 return -ENOSPC; in lochnagar2_get_gpio_chan()
839 switch (priv->lochnagar->type) { in lochnagar_pin_set_mux()
845 dev_err(priv->dev, "Failed to get channel for %s: %d\n", in lochnagar_pin_set_mux()
846 pin->name, ret); in lochnagar_pin_set_mux()
854 dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op); in lochnagar_pin_set_mux()
856 ret = regmap_write(priv->lochnagar->regmap, pin->reg, op); in lochnagar_pin_set_mux()
858 dev_err(priv->dev, "Failed to set %s mux: %d\n", in lochnagar_pin_set_mux()
859 pin->name, ret); in lochnagar_pin_set_mux()
868 struct regmap *regmap = priv->lochnagar->regmap; in lochnagar_aif_set_mux()
869 const struct lochnagar_aif *aif = group->priv; in lochnagar_aif_set_mux()
873 ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op); in lochnagar_aif_set_mux()
875 dev_err(priv->dev, "Failed to set %s source: %d\n", in lochnagar_aif_set_mux()
876 group->name, ret); in lochnagar_aif_set_mux()
880 ret = regmap_update_bits(regmap, aif->ctrl_reg, in lochnagar_aif_set_mux()
881 aif->ena_mask, aif->ena_mask); in lochnagar_aif_set_mux()
883 dev_err(priv->dev, "Failed to set %s enable: %d\n", in lochnagar_aif_set_mux()
884 group->name, ret); in lochnagar_aif_set_mux()
888 for (i = 0; i < group->npins; i++) { in lochnagar_aif_set_mux()
889 pin = priv->pins[group->pins[i]].drv_data; in lochnagar_aif_set_mux()
891 if (pin->type != LN_PTYPE_MUX) in lochnagar_aif_set_mux()
894 dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name); in lochnagar_aif_set_mux()
896 ret = regmap_update_bits(regmap, pin->reg, in lochnagar_aif_set_mux()
900 dev_err(priv->dev, "Failed to set %s to AIF: %d\n", in lochnagar_aif_set_mux()
901 pin->name, ret); in lochnagar_aif_set_mux()
913 const struct lochnagar_func *func = &priv->funcs[func_idx]; in lochnagar_set_mux()
914 const struct lochnagar_group *group = &priv->groups[group_idx]; in lochnagar_set_mux()
917 switch (func->type) { in lochnagar_set_mux()
919 dev_dbg(priv->dev, "Set group %s to %s\n", in lochnagar_set_mux()
920 group->name, func->name); in lochnagar_set_mux()
922 return lochnagar_aif_set_mux(priv, group, func->op); in lochnagar_set_mux()
924 pin = priv->pins[*group->pins].drv_data; in lochnagar_set_mux()
926 dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name); in lochnagar_set_mux()
928 return lochnagar_pin_set_mux(priv, pin, func->op); in lochnagar_set_mux()
930 return -EINVAL; in lochnagar_set_mux()
939 struct lochnagar *lochnagar = priv->lochnagar; in lochnagar_gpio_request()
940 const struct lochnagar_pin *pin = priv->pins[offset].drv_data; in lochnagar_gpio_request()
943 dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name); in lochnagar_gpio_request()
945 if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX) in lochnagar_gpio_request()
950 dev_err(priv->dev, "Failed to get low channel: %d\n", ret); in lochnagar_gpio_request()
956 dev_err(priv->dev, "Failed to get high channel: %d\n", ret); in lochnagar_gpio_request()
970 return -EINVAL; in lochnagar_gpio_set_direction()
990 struct regmap *regmap = priv->lochnagar->regmap; in lochnagar_aif_set_master()
991 const struct lochnagar_group *group = &priv->groups[group_idx]; in lochnagar_aif_set_master()
992 const struct lochnagar_aif *aif = group->priv; in lochnagar_aif_set_master()
996 if (group->type != LN_FTYPE_AIF) in lochnagar_aif_set_master()
997 return -EINVAL; in lochnagar_aif_set_master()
1000 val = aif->master_mask; in lochnagar_aif_set_master()
1002 dev_dbg(priv->dev, "Set AIF %s to %s\n", in lochnagar_aif_set_master()
1003 group->name, master ? "master" : "slave"); in lochnagar_aif_set_master()
1005 ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val); in lochnagar_aif_set_master()
1007 dev_err(priv->dev, "Failed to set %s mode: %d\n", in lochnagar_aif_set_master()
1008 group->name, ret); in lochnagar_aif_set_master()
1038 return -ENOTSUPP; in lochnagar_conf_group_set()
1052 .name = "lochnagar-pinctrl",
1064 struct lochnagar *lochnagar = priv->lochnagar; in lochnagar_gpio_set()
1065 const struct lochnagar_pin *pin = priv->pins[offset].drv_data; in lochnagar_gpio_set()
1070 dev_dbg(priv->dev, "Set GPIO %s to %s\n", in lochnagar_gpio_set()
1071 pin->name, value ? "high" : "low"); in lochnagar_gpio_set()
1073 switch (pin->type) { in lochnagar_gpio_set()
1080 if (pin->invert) in lochnagar_gpio_set()
1083 ret = regmap_update_bits(lochnagar->regmap, pin->reg, in lochnagar_gpio_set()
1084 BIT(pin->shift), value << pin->shift); in lochnagar_gpio_set()
1087 ret = -EINVAL; in lochnagar_gpio_set()
1092 dev_err(chip->parent, "Failed to set %s value: %d\n", in lochnagar_gpio_set()
1093 pin->name, ret); in lochnagar_gpio_set()
1109 for (i = 0; i < priv->ngroups; i++) in lochnagar_fill_func_groups()
1110 priv->func_groups[priv->groups[i].type].ngroups++; in lochnagar_fill_func_groups()
1113 funcs = &priv->func_groups[i]; in lochnagar_fill_func_groups()
1115 if (!funcs->ngroups) in lochnagar_fill_func_groups()
1118 funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups, in lochnagar_fill_func_groups()
1119 sizeof(*funcs->groups), in lochnagar_fill_func_groups()
1121 if (!funcs->groups) in lochnagar_fill_func_groups()
1122 return -ENOMEM; in lochnagar_fill_func_groups()
1124 funcs->ngroups = 0; in lochnagar_fill_func_groups()
1127 for (i = 0; i < priv->ngroups; i++) { in lochnagar_fill_func_groups()
1128 funcs = &priv->func_groups[priv->groups[i].type]; in lochnagar_fill_func_groups()
1130 funcs->groups[funcs->ngroups++] = priv->groups[i].name; in lochnagar_fill_func_groups()
1138 struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent); in lochnagar_pin_probe()
1142 struct device *dev = &pdev->dev; in lochnagar_pin_probe()
1147 return -ENOMEM; in lochnagar_pin_probe()
1149 priv->dev = dev; in lochnagar_pin_probe()
1150 priv->lochnagar = lochnagar; in lochnagar_pin_probe()
1154 return -ENOMEM; in lochnagar_pin_probe()
1158 priv->gpio_chip.label = dev_name(dev); in lochnagar_pin_probe()
1159 priv->gpio_chip.request = gpiochip_generic_request; in lochnagar_pin_probe()
1160 priv->gpio_chip.free = gpiochip_generic_free; in lochnagar_pin_probe()
1161 priv->gpio_chip.direction_output = lochnagar_gpio_direction_out; in lochnagar_pin_probe()
1162 priv->gpio_chip.set = lochnagar_gpio_set; in lochnagar_pin_probe()
1163 priv->gpio_chip.can_sleep = true; in lochnagar_pin_probe()
1164 priv->gpio_chip.parent = dev; in lochnagar_pin_probe()
1165 priv->gpio_chip.base = -1; in lochnagar_pin_probe()
1167 switch (lochnagar->type) { in lochnagar_pin_probe()
1169 priv->funcs = lochnagar1_funcs; in lochnagar_pin_probe()
1170 priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs); in lochnagar_pin_probe()
1171 priv->pins = lochnagar1_pins; in lochnagar_pin_probe()
1172 priv->npins = ARRAY_SIZE(lochnagar1_pins); in lochnagar_pin_probe()
1173 priv->groups = lochnagar1_groups; in lochnagar_pin_probe()
1174 priv->ngroups = ARRAY_SIZE(lochnagar1_groups); in lochnagar_pin_probe()
1176 priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS; in lochnagar_pin_probe()
1179 priv->funcs = lochnagar2_funcs; in lochnagar_pin_probe()
1180 priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs); in lochnagar_pin_probe()
1181 priv->pins = lochnagar2_pins; in lochnagar_pin_probe()
1182 priv->npins = ARRAY_SIZE(lochnagar2_pins); in lochnagar_pin_probe()
1183 priv->groups = lochnagar2_groups; in lochnagar_pin_probe()
1184 priv->ngroups = ARRAY_SIZE(lochnagar2_groups); in lochnagar_pin_probe()
1186 priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS; in lochnagar_pin_probe()
1189 dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type); in lochnagar_pin_probe()
1190 return -EINVAL; in lochnagar_pin_probe()
1197 desc->pins = priv->pins; in lochnagar_pin_probe()
1198 desc->npins = priv->npins; in lochnagar_pin_probe()
1203 dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret); in lochnagar_pin_probe()
1207 ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); in lochnagar_pin_probe()
1209 dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret); in lochnagar_pin_probe()
1217 { .compatible = "cirrus,lochnagar-pinctrl" },
1224 .name = "lochnagar-pinctrl",