Lines Matching +full:gf +full:- +full:gpio3
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
21 #include <linux/pinctrl/pinconf-generic.h>
30 #include <dt-bindings/pinctrl/lochnagar.h>
32 #include "../pinctrl-utils.h"
36 #define LN_CDC_AIF1_STR "codec-aif1"
37 #define LN_CDC_AIF2_STR "codec-aif2"
38 #define LN_CDC_AIF3_STR "codec-aif3"
39 #define LN_DSP_AIF1_STR "dsp-aif1"
40 #define LN_DSP_AIF2_STR "dsp-aif2"
43 #define LN_GF_AIF1_STR "gf-aif1"
44 #define LN_GF_AIF2_STR "gf-aif2"
45 #define LN_GF_AIF3_STR "gf-aif3"
46 #define LN_GF_AIF4_STR "gf-aif4"
47 #define LN_SPDIF_AIF_STR "spdif-aif"
48 #define LN_USB_AIF1_STR "usb-aif1"
49 #define LN_USB_AIF2_STR "usb-aif2"
50 #define LN_ADAT_AIF_STR "adat-aif"
51 #define LN_SOUNDCARD_AIF_STR "soundcard-aif"
64 LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
65 LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
66 LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
67 LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
88 LN2_PIN_MUX(ID##_BCLK, LN_##ID##_STR"-bclk"); \
89 LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
90 LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
91 LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
203 LN1_PIN_GPIO(CDC_RESET, "codec-reset", RST, CDC_RESET, 1);
204 LN1_PIN_GPIO(DSP_RESET, "dsp-reset", RST, DSP_RESET, 1);
205 LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0);
206 LN1_PIN_MUX(GF_GPIO2, "gf-gpio2");
207 LN1_PIN_MUX(GF_GPIO3, "gf-gpio3");
208 LN1_PIN_MUX(GF_GPIO7, "gf-gpio7");
224 LN2_PIN_GPIO(CDC_RESET, "codec-reset", MINICARD_RESETS, CDC_RESET, 1);
225 LN2_PIN_GPIO(DSP_RESET, "dsp-reset", MINICARD_RESETS, DSP_RESET, 1);
226 LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4, CDC_CIF1MODE, 0);
227 LN2_PIN_GPIO(CDC_LDOENA, "codec-ldoena", POWER_CTRL, PWR_ENA, 0);
228 LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode", SPDIF_CTRL, SPDIF_HWMODE, 0);
229 LN2_PIN_GPIO(SPDIF_RESET, "spdif-reset", SPDIF_CTRL, SPDIF_RESET, 1);
230 LN2_PIN_MUX(FPGA_GPIO1, "fpga-gpio1");
231 LN2_PIN_MUX(FPGA_GPIO2, "fpga-gpio2");
232 LN2_PIN_MUX(FPGA_GPIO3, "fpga-gpio3");
233 LN2_PIN_MUX(FPGA_GPIO4, "fpga-gpio4");
234 LN2_PIN_MUX(FPGA_GPIO5, "fpga-gpio5");
235 LN2_PIN_MUX(FPGA_GPIO6, "fpga-gpio6");
236 LN2_PIN_MUX(CDC_GPIO1, "codec-gpio1");
237 LN2_PIN_MUX(CDC_GPIO2, "codec-gpio2");
238 LN2_PIN_MUX(CDC_GPIO3, "codec-gpio3");
239 LN2_PIN_MUX(CDC_GPIO4, "codec-gpio4");
240 LN2_PIN_MUX(CDC_GPIO5, "codec-gpio5");
241 LN2_PIN_MUX(CDC_GPIO6, "codec-gpio6");
242 LN2_PIN_MUX(CDC_GPIO7, "codec-gpio7");
243 LN2_PIN_MUX(CDC_GPIO8, "codec-gpio8");
244 LN2_PIN_MUX(DSP_GPIO1, "dsp-gpio1");
245 LN2_PIN_MUX(DSP_GPIO2, "dsp-gpio2");
246 LN2_PIN_MUX(DSP_GPIO3, "dsp-gpio3");
247 LN2_PIN_MUX(DSP_GPIO4, "dsp-gpio4");
248 LN2_PIN_MUX(DSP_GPIO5, "dsp-gpio5");
249 LN2_PIN_MUX(DSP_GPIO6, "dsp-gpio6");
250 LN2_PIN_MUX(GF_GPIO2, "gf-gpio2");
251 LN2_PIN_MUX(GF_GPIO3, "gf-gpio3");
252 LN2_PIN_MUX(GF_GPIO7, "gf-gpio7");
253 LN2_PIN_MUX(DSP_UART1_RX, "dsp-uart1-rx");
254 LN2_PIN_MUX(DSP_UART1_TX, "dsp-uart1-tx");
255 LN2_PIN_MUX(DSP_UART2_RX, "dsp-uart2-rx");
256 LN2_PIN_MUX(DSP_UART2_TX, "dsp-uart2-tx");
257 LN2_PIN_MUX(GF_UART2_RX, "gf-uart2-rx");
258 LN2_PIN_MUX(GF_UART2_TX, "gf-uart2-tx");
259 LN2_PIN_MUX(USB_UART_RX, "usb-uart-rx");
260 LN2_PIN_MUX(CDC_PDMCLK1, "codec-pdmclk1");
261 LN2_PIN_MUX(CDC_PDMDAT1, "codec-pdmdat1");
262 LN2_PIN_MUX(CDC_PDMCLK2, "codec-pdmclk2");
263 LN2_PIN_MUX(CDC_PDMDAT2, "codec-pdmdat2");
264 LN2_PIN_MUX(CDC_DMICCLK1, "codec-dmicclk1");
265 LN2_PIN_MUX(CDC_DMICDAT1, "codec-dmicdat1");
266 LN2_PIN_MUX(CDC_DMICCLK2, "codec-dmicclk2");
267 LN2_PIN_MUX(CDC_DMICDAT2, "codec-dmicdat2");
268 LN2_PIN_MUX(CDC_DMICCLK3, "codec-dmicclk3");
269 LN2_PIN_MUX(CDC_DMICDAT3, "codec-dmicdat3");
270 LN2_PIN_MUX(CDC_DMICCLK4, "codec-dmicclk4");
271 LN2_PIN_MUX(CDC_DMICDAT4, "codec-dmicdat4");
272 LN2_PIN_MUX(DSP_DMICCLK1, "dsp-dmicclk1");
273 LN2_PIN_MUX(DSP_DMICDAT1, "dsp-dmicdat1");
274 LN2_PIN_MUX(DSP_DMICCLK2, "dsp-dmicclk2");
275 LN2_PIN_MUX(DSP_DMICDAT2, "dsp-dmicdat2");
276 LN2_PIN_MUX(I2C2_SCL, "i2c2-scl");
277 LN2_PIN_MUX(I2C2_SDA, "i2c2-sda");
278 LN2_PIN_MUX(I2C3_SCL, "i2c3-scl");
279 LN2_PIN_MUX(I2C3_SDA, "i2c3-sda");
280 LN2_PIN_MUX(I2C4_SCL, "i2c4-scl");
281 LN2_PIN_MUX(I2C4_SDA, "i2c4-sda");
282 LN2_PIN_MUX(DSP_STANDBY, "dsp-standby");
283 LN2_PIN_MUX(CDC_MCLK1, "codec-mclk1");
284 LN2_PIN_MUX(CDC_MCLK2, "codec-mclk2");
285 LN2_PIN_MUX(DSP_CLKIN, "dsp-clkin");
286 LN2_PIN_MUX(PSIA1_MCLK, "psia1-mclk");
287 LN2_PIN_MUX(PSIA2_MCLK, "psia2-mclk");
288 LN2_PIN_MUX(GF_GPIO1, "gf-gpio1");
289 LN2_PIN_MUX(GF_GPIO5, "gf-gpio5");
290 LN2_PIN_MUX(DSP_GPIO20, "dsp-gpio20");
477 LN_FUNC("dsp-gpio1", PIN, 0x01),
478 LN_FUNC("dsp-gpio2", PIN, 0x02),
479 LN_FUNC("dsp-gpio3", PIN, 0x03),
480 LN_FUNC("codec-gpio1", PIN, 0x04),
481 LN_FUNC("codec-gpio2", PIN, 0x05),
482 LN_FUNC("codec-gpio3", PIN, 0x06),
483 LN_FUNC("codec-gpio4", PIN, 0x07),
484 LN_FUNC("codec-gpio5", PIN, 0x08),
485 LN_FUNC("codec-gpio6", PIN, 0x09),
486 LN_FUNC("codec-gpio7", PIN, 0x0A),
487 LN_FUNC("codec-gpio8", PIN, 0x0B),
534 LN_FUNC("codec-clkout", PIN, 0x20),
535 LN_FUNC("dsp-clkout", PIN, 0x21),
536 LN_FUNC("pmic-32k", PIN, 0x22),
537 LN_FUNC("spdif-clkout", PIN, 0x23),
538 LN_FUNC("clk-12m288", PIN, 0x24),
539 LN_FUNC("clk-11m2986", PIN, 0x25),
540 LN_FUNC("clk-24m576", PIN, 0x26),
541 LN_FUNC("clk-22m5792", PIN, 0x27),
542 LN_FUNC("xmos-mclk", PIN, 0x29),
543 LN_FUNC("gf-clkout1", PIN, 0x2A),
544 LN_FUNC("gf-mclk1", PIN, 0x2B),
545 LN_FUNC("gf-mclk3", PIN, 0x2C),
546 LN_FUNC("gf-mclk2", PIN, 0x2D),
547 LN_FUNC("gf-clkout2", PIN, 0x2E),
553 LN_FUNC("spdif-mclk", PIN, 0x34),
554 LN_FUNC("codec-irq", PIN, 0x42),
557 LN_FUNC("dsp-irq", PIN, 0x45),
582 LN_FUNC("usb-uart-tx", PIN, 0xC7),
732 return priv->ngroups;
740 return priv->groups[group_idx].name;
750 *pins = priv->groups[group_idx].pins;
751 *num_pins = priv->groups[group_idx].npins;
768 return priv->nfuncs;
776 return priv->funcs[func_idx].name;
787 func_type = priv->funcs[func_idx].type;
789 *groups = priv->func_groups[func_type].groups;
790 *num_groups = priv->func_groups[func_type].ngroups;
798 struct regmap *regmap = priv->lochnagar->regmap;
800 int free = -1;
826 dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op);
831 return -ENOSPC;
840 switch (priv->lochnagar->type) {
846 dev_err(priv->dev, "Failed to get channel for %s: %d\n",
847 pin->name, ret);
855 dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op);
857 ret = regmap_write(priv->lochnagar->regmap, pin->reg, op);
859 dev_err(priv->dev, "Failed to set %s mux: %d\n",
860 pin->name, ret);
869 struct regmap *regmap = priv->lochnagar->regmap;
870 const struct lochnagar_aif *aif = group->priv;
874 ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op);
876 dev_err(priv->dev, "Failed to set %s source: %d\n",
877 group->name, ret);
881 ret = regmap_update_bits(regmap, aif->ctrl_reg,
882 aif->ena_mask, aif->ena_mask);
884 dev_err(priv->dev, "Failed to set %s enable: %d\n",
885 group->name, ret);
889 for (i = 0; i < group->npins; i++) {
890 pin = priv->pins[group->pins[i]].drv_data;
892 if (pin->type != LN_PTYPE_MUX)
895 dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name);
897 ret = regmap_update_bits(regmap, pin->reg,
901 dev_err(priv->dev, "Failed to set %s to AIF: %d\n",
902 pin->name, ret);
914 const struct lochnagar_func *func = &priv->funcs[func_idx];
915 const struct lochnagar_group *group = &priv->groups[group_idx];
918 switch (func->type) {
920 dev_dbg(priv->dev, "Set group %s to %s\n",
921 group->name, func->name);
923 return lochnagar_aif_set_mux(priv, group, func->op);
925 pin = priv->pins[*group->pins].drv_data;
927 dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name);
929 return lochnagar_pin_set_mux(priv, pin, func->op);
931 return -EINVAL;
940 struct lochnagar *lochnagar = priv->lochnagar;
941 const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
944 dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name);
946 if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX)
951 dev_err(priv->dev, "Failed to get low channel: %d\n", ret);
957 dev_err(priv->dev, "Failed to get high channel: %d\n", ret);
971 return -EINVAL;
991 struct regmap *regmap = priv->lochnagar->regmap;
992 const struct lochnagar_group *group = &priv->groups[group_idx];
993 const struct lochnagar_aif *aif = group->priv;
997 if (group->type != LN_FTYPE_AIF)
998 return -EINVAL;
1001 val = aif->master_mask;
1003 dev_dbg(priv->dev, "Set AIF %s to %s\n",
1004 group->name, master ? "master" : "slave");
1006 ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
1008 dev_err(priv->dev, "Failed to set %s mode: %d\n",
1009 group->name, ret);
1039 return -ENOTSUPP;
1053 .name = "lochnagar-pinctrl",
1065 struct lochnagar *lochnagar = priv->lochnagar;
1066 const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
1071 dev_dbg(priv->dev, "Set GPIO %s to %s\n",
1072 pin->name, str_high_low(value));
1074 switch (pin->type) {
1081 if (pin->invert)
1084 ret = regmap_update_bits(lochnagar->regmap, pin->reg,
1085 BIT(pin->shift), value << pin->shift);
1088 ret = -EINVAL;
1093 dev_err(chip->parent, "Failed to set %s value: %d\n",
1094 pin->name, ret);
1110 for (i = 0; i < priv->ngroups; i++)
1111 priv->func_groups[priv->groups[i].type].ngroups++;
1114 funcs = &priv->func_groups[i];
1116 if (!funcs->ngroups)
1119 funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups,
1120 sizeof(*funcs->groups),
1122 if (!funcs->groups)
1123 return -ENOMEM;
1125 funcs->ngroups = 0;
1128 for (i = 0; i < priv->ngroups; i++) {
1129 funcs = &priv->func_groups[priv->groups[i].type];
1131 funcs->groups[funcs->ngroups++] = priv->groups[i].name;
1139 struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent);
1143 struct device *dev = &pdev->dev;
1148 return -ENOMEM;
1150 priv->dev = dev;
1151 priv->lochnagar = lochnagar;
1155 return -ENOMEM;
1159 priv->gpio_chip.label = dev_name(dev);
1160 priv->gpio_chip.request = gpiochip_generic_request;
1161 priv->gpio_chip.free = gpiochip_generic_free;
1162 priv->gpio_chip.direction_output = lochnagar_gpio_direction_out;
1163 priv->gpio_chip.set = lochnagar_gpio_set;
1164 priv->gpio_chip.can_sleep = true;
1165 priv->gpio_chip.parent = dev;
1166 priv->gpio_chip.base = -1;
1168 switch (lochnagar->type) {
1170 priv->funcs = lochnagar1_funcs;
1171 priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs);
1172 priv->pins = lochnagar1_pins;
1173 priv->npins = ARRAY_SIZE(lochnagar1_pins);
1174 priv->groups = lochnagar1_groups;
1175 priv->ngroups = ARRAY_SIZE(lochnagar1_groups);
1177 priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS;
1180 priv->funcs = lochnagar2_funcs;
1181 priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs);
1182 priv->pins = lochnagar2_pins;
1183 priv->npins = ARRAY_SIZE(lochnagar2_pins);
1184 priv->groups = lochnagar2_groups;
1185 priv->ngroups = ARRAY_SIZE(lochnagar2_groups);
1187 priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS;
1190 dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type);
1191 return -EINVAL;
1198 desc->pins = priv->pins;
1199 desc->npins = priv->npins;
1204 dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret);
1208 ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
1210 dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret);
1218 { .compatible = "cirrus,lochnagar-pinctrl" },
1225 .name = "lochnagar-pinctrl",