1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/mfd/cs42l43-regs.h>
25 #include <linux/pinctrl/pinconf-generic.h>
28 #include "../pinctrl-utils.h"
139 	"gpio", "spdif", "irq", "mic-shutter", "spk-shutter",
154 	PINCTRL_PINFUNCTION("mic-shutter", cs42l43_pin_shutter_groups,
156 	PINCTRL_PINFUNCTION("spk-shutter", cs42l43_pin_shutter_groups,
191 	dev_dbg(priv->dev, "Setting %s to %s\n",  in cs42l43_pin_set_mux()
213 	if (priv->shutters_locked && reg == CS42L43_SHUTTER_CONTROL) {  in cs42l43_pin_set_mux()
214 		dev_err(priv->dev, "Shutter configuration not available\n");  in cs42l43_pin_set_mux()
215 		return -EPERM;  in cs42l43_pin_set_mux()
218 	return regmap_update_bits(priv->regmap, reg, mask, val);  in cs42l43_pin_set_mux()
223 				      unsigned int offset, bool input)  in cs42l43_gpio_set_direction()  argument
226 	unsigned int shift = offset + CS42L43_GPIO1_DIR_SHIFT;  in cs42l43_gpio_set_direction()
229 	dev_dbg(priv->dev, "Setting gpio%d to %s\n",  in cs42l43_gpio_set_direction()
230 		offset + 1, input ? "input" : "output");  in cs42l43_gpio_set_direction()
232 	ret = pm_runtime_resume_and_get(priv->dev);  in cs42l43_gpio_set_direction()
234 		dev_err(priv->dev, "Failed to resume for direction: %d\n", ret);  in cs42l43_gpio_set_direction()
238 	ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,  in cs42l43_gpio_set_direction()
241 		dev_err(priv->dev, "Failed to set gpio%d direction: %d\n",  in cs42l43_gpio_set_direction()
242 			offset + 1, ret);  in cs42l43_gpio_set_direction()
244 	pm_runtime_put(priv->dev);  in cs42l43_gpio_set_direction()
251 				       unsigned int offset)  in cs42l43_gpio_request_enable()  argument
253 	return cs42l43_pin_set_mux(pctldev, 0, offset);  in cs42l43_gpio_request_enable()
258 				      unsigned int offset)  in cs42l43_gpio_disable_free()  argument
260 	cs42l43_gpio_set_direction(pctldev, range, offset, true);  in cs42l43_gpio_disable_free()
285 	ret = regmap_read(priv->regmap, pdat->reg, &val);  in cs42l43_pin_get_drv_str()
289 	return cs42l43_pin_drv_str_ma[(val & pdat->mask) >> pdat->shift];  in cs42l43_pin_get_drv_str()
300 			if ((i << pdat->shift) > pdat->mask)  in cs42l43_pin_set_drv_str()
303 			dev_dbg(priv->dev, "Set drive strength for %s to %d mA\n",  in cs42l43_pin_set_drv_str()
306 			return regmap_update_bits(priv->regmap, pdat->reg,  in cs42l43_pin_set_drv_str()
307 						  pdat->mask, i << pdat->shift);  in cs42l43_pin_set_drv_str()
312 	dev_err(priv->dev, "Invalid drive strength for %s: %d mA\n",  in cs42l43_pin_set_drv_str()
314 	return -EINVAL;  in cs42l43_pin_set_drv_str()
323 		return -ENOTSUPP;  in cs42l43_pin_get_db()
325 	ret = regmap_read(priv->regmap, CS42L43_GPIO_CTRL2, &val);  in cs42l43_pin_get_db()
339 		return -ENOTSUPP;  in cs42l43_pin_set_db()
341 	dev_dbg(priv->dev, "Set debounce %s for %s\n",  in cs42l43_pin_set_db()
344 	return regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL2,  in cs42l43_pin_set_db()
368 		return -ENOTSUPP;  in cs42l43_pin_config_get()
398 			return -ENOTSUPP;  in cs42l43_pin_config_set()
402 		num_configs--;  in cs42l43_pin_config_set()
452 	.name		= "cs42l43-pinctrl",
463 static int cs42l43_gpio_get(struct gpio_chip *chip, unsigned int offset)  in cs42l43_gpio_get()  argument
469 	ret = pm_runtime_resume_and_get(priv->dev);  in cs42l43_gpio_get()
471 		dev_err(priv->dev, "Failed to resume for get: %d\n", ret);  in cs42l43_gpio_get()
475 	ret = regmap_read(priv->regmap, CS42L43_GPIO_STS, &val);  in cs42l43_gpio_get()
477 		dev_err(priv->dev, "Failed to get gpio%d: %d\n", offset + 1, ret);  in cs42l43_gpio_get()
479 		ret = !!(val & BIT(offset + CS42L43_GPIO1_STS_SHIFT));  in cs42l43_gpio_get()
481 	pm_runtime_put(priv->dev);  in cs42l43_gpio_get()
486 static int cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset,  in cs42l43_gpio_set()  argument
490 	unsigned int shift = offset + CS42L43_GPIO1_LVL_SHIFT;  in cs42l43_gpio_set()
493 	dev_dbg(priv->dev, "Setting gpio%d to %s\n",  in cs42l43_gpio_set()
494 		offset + 1, str_high_low(value));  in cs42l43_gpio_set()
496 	ret = pm_runtime_resume_and_get(priv->dev);  in cs42l43_gpio_set()
500 	ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,  in cs42l43_gpio_set()
505 	pm_runtime_put(priv->dev);  in cs42l43_gpio_set()
511 				      unsigned int offset, int value)  in cs42l43_gpio_direction_out()  argument
515 	ret = cs42l43_gpio_set(chip, offset, value);  in cs42l43_gpio_direction_out()
519 	return pinctrl_gpio_direction_output(chip, offset);  in cs42l43_gpio_direction_out()
527 	ret = gpiochip_add_pin_range(&priv->gpio_chip, priv->gpio_chip.label,  in cs42l43_gpio_add_pin_ranges()
530 		dev_err(priv->dev, "Failed to add GPIO pin range: %d\n", ret);  in cs42l43_gpio_add_pin_ranges()
537 	struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);  in cs42l43_pin_probe()
540 	struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);  in cs42l43_pin_probe()
543 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in cs42l43_pin_probe()
545 		return -ENOMEM;  in cs42l43_pin_probe()
547 	priv->dev = &pdev->dev;  in cs42l43_pin_probe()
548 	priv->regmap = cs42l43->regmap;  in cs42l43_pin_probe()
550 	priv->shutters_locked = cs42l43->hw_lock;  in cs42l43_pin_probe()
552 	priv->gpio_chip.request = gpiochip_generic_request;  in cs42l43_pin_probe()
553 	priv->gpio_chip.free = gpiochip_generic_free;  in cs42l43_pin_probe()
554 	priv->gpio_chip.direction_input = pinctrl_gpio_direction_input;  in cs42l43_pin_probe()
555 	priv->gpio_chip.direction_output = cs42l43_gpio_direction_out;  in cs42l43_pin_probe()
556 	priv->gpio_chip.add_pin_ranges = cs42l43_gpio_add_pin_ranges;  in cs42l43_pin_probe()
557 	priv->gpio_chip.get = cs42l43_gpio_get;  in cs42l43_pin_probe()
558 	priv->gpio_chip.set = cs42l43_gpio_set;  in cs42l43_pin_probe()
559 	priv->gpio_chip.label = dev_name(priv->dev);  in cs42l43_pin_probe()
560 	priv->gpio_chip.parent = priv->dev;  in cs42l43_pin_probe()
561 	priv->gpio_chip.can_sleep = true;  in cs42l43_pin_probe()
562 	priv->gpio_chip.base = -1;  in cs42l43_pin_probe()
563 	priv->gpio_chip.ngpio = CS42L43_NUM_GPIOS;  in cs42l43_pin_probe()
568 		if (fwnode && !fwnode->dev)  in cs42l43_pin_probe()
569 			fwnode->dev = priv->dev;  in cs42l43_pin_probe()
572 	priv->gpio_chip.fwnode = fwnode;  in cs42l43_pin_probe()
574 	device_set_node(priv->dev, fwnode);  in cs42l43_pin_probe()
576 	devm_pm_runtime_enable(priv->dev);  in cs42l43_pin_probe()
577 	pm_runtime_idle(priv->dev);  in cs42l43_pin_probe()
579 	pctldev = devm_pinctrl_register(priv->dev, &cs42l43_pin_desc, priv);  in cs42l43_pin_probe()
581 		return dev_err_probe(priv->dev, PTR_ERR(pctldev),  in cs42l43_pin_probe()
584 	ret = devm_gpiochip_add_data(priv->dev, &priv->gpio_chip, priv);  in cs42l43_pin_probe()
586 		return dev_err_probe(priv->dev, ret,  in cs42l43_pin_probe()
593 	{ "cs42l43-pinctrl", },
600 		.name	= "cs42l43-pinctrl",