Lines Matching refs:SCU94
50 #define SCU94 0x94 /* Multi-function Pin Control #6 */ macro
60 #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
445 #define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
476 SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
481 SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
486 SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
491 SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
496 SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
501 SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
621 SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
627 SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
633 SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
639 SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
1023 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
1024 #define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
1025 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
1026 #define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
1417 SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
1425 SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
1433 SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
1441 SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
1867 #define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
1868 #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
1869 #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
1870 #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }