Lines Matching +full:pull +full:- +full:downs
1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
45 #define SCU80 0x80 /* Multi-function Pin Control #1 */
46 #define SCU84 0x84 /* Multi-function Pin Control #2 */
47 #define SCU88 0x88 /* Multi-function Pin Control #3 */
48 #define SCU8C 0x8C /* Multi-function Pin Control #4 */
49 #define SCU90 0x90 /* Multi-function Pin Control #5 */
50 #define SCU94 0x94 /* Multi-function Pin Control #6 */
51 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
52 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
53 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
54 #define SCUAC 0xAC /* Multi-function Pin Control #10 */
62 /* LHCR0 is offset from the end of the H8S/2168-compatible registers */
1540 /* CRT DVO disabled, configured for single-edge mode */
1543 /* CRT DVO disabled, configured for dual-edge mode */
1546 /* CRT DVO enabled, configured for single-edge mode */
1549 /* CRT DVO enabled, configured for dual-edge mode */
2544 /* GPIOs T[0-5] (RGMII1 Tx pins) */
2550 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2556 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2560 /* GPIOs V[2-7] (RGMII2 Rx pins) */
2564 /* ADC pull-downs (SCUA8[19:4]) */
2601 * banks D and E is handled by the GPIO driver - GPIO passthrough is
2602 * treated like any other non-GPIO mux function. There is a catch
2605 * fully support pass-through debounce.
2621 WARN(!ctx->maps[ip], "Missing SCU syscon!"); in aspeed_g5_acquire_regmap()
2622 return ctx->maps[ip]; in aspeed_g5_acquire_regmap()
2626 return ERR_PTR(-EINVAL); in aspeed_g5_acquire_regmap()
2628 if (likely(ctx->maps[ip])) in aspeed_g5_acquire_regmap()
2629 return ctx->maps[ip]; in aspeed_g5_acquire_regmap()
2635 node = of_parse_phandle(ctx->dev->of_node, in aspeed_g5_acquire_regmap()
2636 "aspeed,external-nodes", 0); in aspeed_g5_acquire_regmap()
2643 return ERR_PTR(-ENODEV); in aspeed_g5_acquire_regmap()
2645 ctx->maps[ASPEED_IP_GFX] = map; in aspeed_g5_acquire_regmap()
2646 dev_dbg(ctx->dev, "Acquired GFX regmap"); in aspeed_g5_acquire_regmap()
2654 np = of_parse_phandle(ctx->dev->of_node, in aspeed_g5_acquire_regmap()
2655 "aspeed,external-nodes", 1); in aspeed_g5_acquire_regmap()
2657 if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") && in aspeed_g5_acquire_regmap()
2658 !of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") && in aspeed_g5_acquire_regmap()
2659 !of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2")) in aspeed_g5_acquire_regmap()
2660 return ERR_PTR(-ENODEV); in aspeed_g5_acquire_regmap()
2662 map = syscon_node_to_regmap(np->parent); in aspeed_g5_acquire_regmap()
2667 return ERR_PTR(-ENODEV); in aspeed_g5_acquire_regmap()
2669 ctx->maps[ASPEED_IP_LPC] = map; in aspeed_g5_acquire_regmap()
2670 dev_dbg(ctx->dev, "Acquired LPC regmap"); in aspeed_g5_acquire_regmap()
2674 return ERR_PTR(-EINVAL); in aspeed_g5_acquire_regmap()
2684 for (i = 0; i < expr->ndescs; i++) { in aspeed_g5_sig_expr_eval()
2685 const struct aspeed_sig_desc *desc = &expr->descs[i]; in aspeed_g5_sig_expr_eval()
2688 map = aspeed_g5_acquire_regmap(ctx, desc->ip); in aspeed_g5_sig_expr_eval()
2690 dev_err(ctx->dev, in aspeed_g5_sig_expr_eval()
2692 desc->ip); in aspeed_g5_sig_expr_eval()
2696 ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]); in aspeed_g5_sig_expr_eval()
2705 * aspeed_g5_sig_expr_set() - Configure a pin's signal by applying an
2724 for (i = 0; i < expr->ndescs; i++) { in aspeed_g5_sig_expr_set()
2725 const struct aspeed_sig_desc *desc = &expr->descs[i]; in aspeed_g5_sig_expr_set()
2726 u32 pattern = enable ? desc->enable : desc->disable; in aspeed_g5_sig_expr_set()
2727 u32 val = (pattern << __ffs(desc->mask)); in aspeed_g5_sig_expr_set()
2730 map = aspeed_g5_acquire_regmap(ctx, desc->ip); in aspeed_g5_sig_expr_set()
2732 dev_err(ctx->dev, in aspeed_g5_sig_expr_set()
2734 desc->ip); in aspeed_g5_sig_expr_set()
2739 * Strap registers are configured in hardware or by early-boot in aspeed_g5_sig_expr_set()
2740 * firmware. Treat them as read-only despite that we can write in aspeed_g5_sig_expr_set()
2742 * deconfigured and is the reason we re-evaluate after writing in aspeed_g5_sig_expr_set()
2745 * We make two exceptions to the read-only rule: in aspeed_g5_sig_expr_set()
2747 * - The passthrough mode of GPIO ports D and E are commonly in aspeed_g5_sig_expr_set()
2748 * used with front-panel buttons to allow normal operation in aspeed_g5_sig_expr_set()
2751 * disabled for the BMC to control host power-on and reset. in aspeed_g5_sig_expr_set()
2753 * - The operating mode of the SPI1 interface is simply in aspeed_g5_sig_expr_set()
2757 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && in aspeed_g5_sig_expr_set()
2758 !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12)))) in aspeed_g5_sig_expr_set()
2761 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) in aspeed_g5_sig_expr_set()
2765 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) { in aspeed_g5_sig_expr_set()
2766 u32 value = ~val & desc->mask; in aspeed_g5_sig_expr_set()
2769 ret = regmap_write(ctx->maps[desc->ip], in aspeed_g5_sig_expr_set()
2776 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, in aspeed_g5_sig_expr_set()
2777 desc->mask, val); in aspeed_g5_sig_expr_set()
2788 return -EPERM; in aspeed_g5_sig_expr_set()
2795 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2796 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2849 .name = "aspeed-g5-pinctrl",
2864 aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev; in aspeed_g5_pinctrl_probe()
2871 { .compatible = "aspeed,ast2500-pinctrl", },
2873 * The aspeed,g5-pinctrl compatible has been removed the from the
2876 { .compatible = "aspeed,g5-pinctrl", },
2883 .name = "aspeed-g5-pinctrl",