Lines Matching +full:tx +full:- +full:termination +full:- +full:fix
1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
219 * struct xpsgtr_dev - representation of a ZynMP GT device
227 * @tx_term_fix: fix for GT issue
273 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
278 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
293 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_read_phy()
294 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
302 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_write_phy()
303 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
311 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_clr_set_phy()
312 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
318 * xpsgtr_save_lane_regs - Saves registers on suspend
326 gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev, in xpsgtr_save_lane_regs()
331 * xpsgtr_restore_lane_regs - Restores registers on resume
340 gtr_dev->saved_regs[i]); in xpsgtr_restore_lane_regs()
351 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_wait_pll_lock()
353 u8 protocol = gtr_phy->protocol; in xpsgtr_wait_pll_lock()
356 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); in xpsgtr_wait_pll_lock()
363 gtr_phy->instance) { in xpsgtr_wait_pll_lock()
367 gtr_phy = >r_dev->phys[i]; in xpsgtr_wait_pll_lock()
369 if (gtr_phy->protocol == protocol && !gtr_phy->instance) in xpsgtr_wait_pll_lock()
373 return -EBUSY; in xpsgtr_wait_pll_lock()
385 if (--timeout == 0) { in xpsgtr_wait_pll_lock()
386 ret = -ETIMEDOUT; in xpsgtr_wait_pll_lock()
393 if (ret == -ETIMEDOUT) in xpsgtr_wait_pll_lock()
394 dev_err(gtr_dev->dev, in xpsgtr_wait_pll_lock()
396 gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance); in xpsgtr_wait_pll_lock()
401 /* Configure PLL and spread-sprectrum clock. */
407 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
408 step_size = ssc->step_size; in xpsgtr_configure_pll()
410 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
411 PLL_FREQ_MASK, ssc->pll_ref_clk); in xpsgtr_configure_pll()
414 if (gtr_phy->refclk == gtr_phy->lane) in xpsgtr_configure_pll()
415 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
418 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
419 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
437 STEPS_0_MASK, ssc->steps & STEPS_0_MASK); in xpsgtr_configure_pll()
442 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); in xpsgtr_configure_pll()
454 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_lane_set_protocol()
455 u8 protocol = gtr_phy->protocol; in xpsgtr_lane_set_protocol()
457 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
485 /* DP-specific initialization. */
498 /* SATA-specific initialization. */
501 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sata()
505 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
508 /* SGMII-specific initialization. */
511 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sgmii()
512 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
513 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
515 /* Set SGMII protocol TX and RX bus width to 10 bits. */ in xpsgtr_phy_init_sgmii()
522 /* Configure TX de-emphasis and margining for DP. */
553 * except when gtr_phy->skip_phy_init is false (this happens when FPD is in xpsgtr_phy_init_required()
556 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init) in xpsgtr_phy_init_required()
563 * There is a functional issue in the GT. The TX termination resistance can be
565 * to fix it, required for XCZU9EG silicon.
569 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_tx_term_fix()
583 * As a part of work around sequence for PMOS calibration fix, in xpsgtr_phy_tx_term_fix()
592 dev_dbg(gtr_dev->dev, "calibrating...\n"); in xpsgtr_phy_tx_term_fix()
600 if (!--timeout) { in xpsgtr_phy_tx_term_fix()
601 dev_err(gtr_dev->dev, "calibration time out\n"); in xpsgtr_phy_tx_term_fix()
602 return -ETIMEDOUT; in xpsgtr_phy_tx_term_fix()
608 dev_dbg(gtr_dev->dev, "calibration done\n"); in xpsgtr_phy_tx_term_fix()
633 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init()
636 mutex_lock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
639 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk])) in xpsgtr_phy_init()
646 if (gtr_dev->tx_term_fix) { in xpsgtr_phy_init()
651 gtr_dev->tx_term_fix = false; in xpsgtr_phy_init()
658 * Configure the PLL, the lane protocol, and perform protocol-specific in xpsgtr_phy_init()
664 switch (gtr_phy->protocol) { in xpsgtr_phy_init()
679 mutex_unlock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
686 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_exit()
688 gtr_phy->skip_phy_init = false; in xpsgtr_phy_exit()
691 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]); in xpsgtr_phy_exit()
711 if (gtr_phy->protocol != ICM_PROTOCOL_DP) in xpsgtr_phy_configure()
714 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]); in xpsgtr_phy_configure()
740 gtr_phy->protocol = ICM_PROTOCOL_SATA; in xpsgtr_set_lane_type()
744 gtr_phy->protocol = ICM_PROTOCOL_USB; in xpsgtr_set_lane_type()
748 gtr_phy->protocol = ICM_PROTOCOL_DP; in xpsgtr_set_lane_type()
752 gtr_phy->protocol = ICM_PROTOCOL_PCIE; in xpsgtr_set_lane_type()
756 gtr_phy->protocol = ICM_PROTOCOL_SGMII; in xpsgtr_set_lane_type()
759 return -EINVAL; in xpsgtr_set_lane_type()
763 return -EINVAL; in xpsgtr_set_lane_type()
765 gtr_phy->instance = phy_instance; in xpsgtr_set_lane_type()
799 if (args->args_count != 4) { in xpsgtr_xlate()
801 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
808 phy_lane = args->args[0]; in xpsgtr_xlate()
809 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) { in xpsgtr_xlate()
811 return ERR_PTR(-ENODEV); in xpsgtr_xlate()
814 gtr_phy = >r_dev->phys[phy_lane]; in xpsgtr_xlate()
815 phy_type = args->args[1]; in xpsgtr_xlate()
816 phy_instance = args->args[2]; in xpsgtr_xlate()
818 guard(mutex)(>r_phy->phy->mutex); in xpsgtr_xlate()
821 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); in xpsgtr_xlate()
825 refclk = args->args[3]; in xpsgtr_xlate()
826 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || in xpsgtr_xlate()
827 !gtr_dev->refclk_sscs[refclk]) { in xpsgtr_xlate()
829 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
832 gtr_phy->refclk = refclk; in xpsgtr_xlate()
839 if (icm_matrix[phy_lane][i] == gtr_phy->instance) in xpsgtr_xlate()
840 return gtr_phy->phy; in xpsgtr_xlate()
843 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
852 struct device *dev = seq->private; in xpsgtr_status_read()
857 mutex_lock(>r_phy->phy->mutex); in xpsgtr_status_read()
859 clk = gtr_phy->dev->clk[gtr_phy->refclk]; in xpsgtr_status_read()
861 seq_printf(seq, "Lane: %u\n", gtr_phy->lane); in xpsgtr_status_read()
863 xpsgtr_icm_str[gtr_phy->protocol]); in xpsgtr_status_read()
864 seq_printf(seq, "Instance: %u\n", gtr_phy->instance); in xpsgtr_status_read()
865 seq_printf(seq, "Reference clock: %u (%pC)\n", gtr_phy->refclk, clk); in xpsgtr_status_read()
870 mutex_unlock(>r_phy->phy->mutex); in xpsgtr_status_read()
883 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); in xpsgtr_runtime_suspend()
884 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); in xpsgtr_runtime_suspend()
904 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1) in xpsgtr_runtime_resume()
908 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 && in xpsgtr_runtime_resume()
909 icm_cfg1 == gtr_dev->saved_icm_cfg1) in xpsgtr_runtime_resume()
915 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++) in xpsgtr_runtime_resume()
916 gtr_dev->phys[i].skip_phy_init = skip_phy_init; in xpsgtr_runtime_resume()
931 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { in xpsgtr_get_ref_clocks()
938 clk = devm_clk_get_optional(gtr_dev->dev, name); in xpsgtr_get_ref_clocks()
940 return dev_err_probe(gtr_dev->dev, PTR_ERR(clk), in xpsgtr_get_ref_clocks()
948 gtr_dev->clk[refclk] = clk; in xpsgtr_get_ref_clocks()
960 if (abs(rate - ssc_lookup[i].refclk_rate) < error) { in xpsgtr_get_ref_clocks()
961 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; in xpsgtr_get_ref_clocks()
967 dev_err(gtr_dev->dev, in xpsgtr_get_ref_clocks()
970 return -EINVAL; in xpsgtr_get_ref_clocks()
979 struct device_node *np = pdev->dev.of_node; in xpsgtr_probe()
985 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); in xpsgtr_probe()
987 return -ENOMEM; in xpsgtr_probe()
989 gtr_dev->dev = &pdev->dev; in xpsgtr_probe()
992 mutex_init(>r_dev->gtr_mutex); in xpsgtr_probe()
994 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr")) in xpsgtr_probe()
995 gtr_dev->tx_term_fix = in xpsgtr_probe()
996 of_property_read_bool(np, "xlnx,tx-termination-fix"); in xpsgtr_probe()
999 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); in xpsgtr_probe()
1000 if (IS_ERR(gtr_dev->serdes)) in xpsgtr_probe()
1001 return PTR_ERR(gtr_dev->serdes); in xpsgtr_probe()
1003 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou"); in xpsgtr_probe()
1004 if (IS_ERR(gtr_dev->siou)) in xpsgtr_probe()
1005 return PTR_ERR(gtr_dev->siou); in xpsgtr_probe()
1012 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) { in xpsgtr_probe()
1013 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port]; in xpsgtr_probe()
1016 gtr_phy->lane = port; in xpsgtr_probe()
1017 gtr_phy->dev = gtr_dev; in xpsgtr_probe()
1019 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); in xpsgtr_probe()
1021 dev_err(&pdev->dev, "failed to create PHY\n"); in xpsgtr_probe()
1025 gtr_phy->phy = phy; in xpsgtr_probe()
1027 debugfs_create_devm_seqfile(&phy->dev, "status", phy->debugfs, in xpsgtr_probe()
1032 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); in xpsgtr_probe()
1034 dev_err(&pdev->dev, "registering provider failed\n"); in xpsgtr_probe()
1038 pm_runtime_set_active(gtr_dev->dev); in xpsgtr_probe()
1039 pm_runtime_enable(gtr_dev->dev); in xpsgtr_probe()
1041 ret = pm_runtime_resume_and_get(gtr_dev->dev); in xpsgtr_probe()
1043 pm_runtime_disable(gtr_dev->dev); in xpsgtr_probe()
1047 gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev, in xpsgtr_probe()
1050 if (!gtr_dev->saved_regs) in xpsgtr_probe()
1051 return -ENOMEM; in xpsgtr_probe()
1060 pm_runtime_disable(gtr_dev->dev); in xpsgtr_remove()
1061 pm_runtime_put_noidle(gtr_dev->dev); in xpsgtr_remove()
1062 pm_runtime_set_suspended(gtr_dev->dev); in xpsgtr_remove()
1066 { .compatible = "xlnx,zynqmp-psgtr", },
1067 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1076 .name = "xilinx-psgtr",