Lines Matching +full:26 +full:mhz
85 #define MEM_OVRD_HS_RATE BIT(26)
86 #define MEM_OVRD_HS_RATE_SHIFT 26
187 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
188 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
189 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
190 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
191 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
192 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
197 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
198 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
199 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
200 {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
201 {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
202 {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */