21 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
22 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
24 #define FUSE_SKU_CALIB_HS_IREF_CAP_MASK 0x3
26 #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK 0x3
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
32 #define XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK 0x3
33 #define XUSB_PADCTL_USB2_PORT_CAP_DISABLED 0x0
34 #define XUSB_PADCTL_USB2_PORT_CAP_HOST 0x1
35 #define XUSB_PADCTL_USB2_PORT_CAP_DEVICE 0x2
36 #define XUSB_PADCTL_USB2_PORT_CAP_OTG 0x3
38 #define XUSB_PADCTL_SS_PORT_MAP 0x014
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
43 #define XUSB_PADCTL_SS_PORT_MAP_PORT_MAP_MASK 0x7
45 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
54 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
56 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
59 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
64 #define XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(x) (0x058 + (x) * 4)
66 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_MASK 0xff
67 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_VAL 0x24
69 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_MASK 0x3f
71 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_MASK 0x3f
73 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_MASK 0xffff
74 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_VAL 0xf070
76 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_MASK 0xf
77 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_VAL 0xf
79 #define XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(x) (0x068 + (x) * 4)
81 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_MASK 0x1f
83 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_MASK 0x7f
84 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_VAL 0x002008ee
86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
87 					       0x0f8 + (x) * 4)
89 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_MASK 0x3
90 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_VAL 0x1
92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
93 					       0x11c + (x) * 4)
96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
97 					       0x128 + (x) * 4)
99 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_G_Z_MASK 0x3f
100 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_TAP_MASK 0x1f
101 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_AMP_MASK 0x7f
103 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK 0xff
104 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_G_Z 0x21
105 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_TAP 0x32
106 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_AMP 0x33
107 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_CTLE_Z 0x48
108 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_LATCH_G_Z 0xa1
110 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x0a0 + (x) * 4)
115 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_MASK 0x3
116 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(x) ((x) ? 0x0 : 0x3)
118 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_MASK 0x3f
119 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL 0x0e
120 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
121 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
123 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x0ac + (x) * 4)
125 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP_MASK 0x3
127 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0x7
130 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP (1 << 0)
132 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0b8
135 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
136 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x5
137 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
138 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x3
140 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x0c0 + (x) * 4)
142 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWN_MASK 0x7
144 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWP_MASK 0x7
146 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEN_MASK 0x7
147 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_SHIFT 0
148 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_MASK 0x7
150 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x0c8 + (x) * 4)
159 #define XUSB_PADCTL_HSIC_PAD_CTL1_AUTO_TERM_EN (1 << 0)
161 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x0d0 + (x) * 4)
163 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0x7
164 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
165 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0x7
167 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x0e0
168 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_STRB_TRIM_MASK 0x1f
170 #define XUSB_PADCTL_USB3_PAD_MUX 0x134
174 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
178 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL0_REFCLK_NDIV_MASK 0x3
181 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
183 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13c
185 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL1_CP_CNTL_MASK 0xf
187 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL0_CP_CNTL_MASK 0xf
190 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_SHIFT 0
191 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_MASK 0x7
193 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140
196 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
198 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
200 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14c
202 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158
204 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15c
231 	if (padctl->enable++ > 0)  in tegra124_xusb_padctl_enable()
252 	return 0;  in tegra124_xusb_padctl_enable()
261 	if (WARN_ON(padctl->enable == 0))  in tegra124_xusb_padctl_disable()
264 	if (--padctl->enable > 0)  in tegra124_xusb_padctl_disable()
285 	return 0;  in tegra124_xusb_padctl_disable()
382 	return 0;  in tegra124_usb3_save_context()
401 	return 0;  in tegra124_hsic_set_idle()
421 	TEGRA124_LANE("usb2-0", 0x004,  0, 0x3, usb2),
422 	TEGRA124_LANE("usb2-1", 0x004,  2, 0x3, usb2),
423 	TEGRA124_LANE("usb2-2", 0x004,  4, 0x3, usb2),
444 	if (err < 0) {  in tegra124_usb2_lane_probe()
555 	if (pad->enable++ > 0)  in tegra124_usb2_phy_power_on()
564 	return 0;  in tegra124_usb2_phy_power_on()
584 	if (WARN_ON(pad->enable == 0))  in tegra124_usb2_phy_power_off()
587 	if (--pad->enable > 0)  in tegra124_usb2_phy_power_off()
597 	return 0;  in tegra124_usb2_phy_power_off()
628 	if (err < 0) {  in tegra124_usb2_pad_probe()
634 	if (err < 0)  in tegra124_usb2_pad_probe()
672 	TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, ulpi),
693 	if (err < 0) {  in tegra124_ulpi_lane_probe()
729 	return 0;  in tegra124_ulpi_phy_power_on()
734 	return 0;  in tegra124_ulpi_phy_power_off()
763 	if (err < 0) {  in tegra124_ulpi_pad_probe()
769 	if (err < 0)  in tegra124_ulpi_pad_probe()
807 	TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, hsic),
808 	TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, hsic),
829 	if (err < 0) {  in tegra124_hsic_lane_probe()
930 	return 0;  in tegra124_hsic_phy_power_on()
950 	return 0;  in tegra124_hsic_phy_power_off()
979 	if (err < 0) {  in tegra124_hsic_pad_probe()
985 	if (err < 0)  in tegra124_hsic_pad_probe()
1024 	TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, pcie),
1025 	TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, pcie),
1026 	TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, pcie),
1027 	TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, pcie),
1028 	TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, pcie),
1049 	if (err < 0) {  in tegra124_pcie_lane_probe()
1110 			err = 0;  in tegra124_pcie_phy_power_on()
1138 	return 0;  in tegra124_pcie_phy_power_off()
1167 	if (err < 0) {  in tegra124_pcie_pad_probe()
1173 	if (err < 0)  in tegra124_pcie_pad_probe()
1206 	TEGRA124_LANE("sata-0", 0x134, 26, 0x3, pcie),
1227 	if (err < 0) {  in tegra124_sata_lane_probe()
1292 			err = 0;  in tegra124_sata_phy_power_on()
1334 	return 0;  in tegra124_sata_phy_power_off()
1363 	if (err < 0) {  in tegra124_sata_pad_probe()
1369 	if (err < 0)  in tegra124_sata_pad_probe()
1411 	return 0;  in tegra124_usb2_port_enable()
1434 	return 0;  in tegra124_ulpi_port_enable()
1456 	return 0;  in tegra124_hsic_port_enable()
1568 		value |= 0x2 <<  in tegra124_usb3_port_enable()
1580 		value |= (0x7 <<  in tegra124_usb3_port_enable()
1582 			 (0x8 <<  in tegra124_usb3_port_enable()
1584 			 (0x8 <<  in tegra124_usb3_port_enable()
1610 	return 0;  in tegra124_usb3_port_enable()
1636 	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->index, 0x7);  in tegra124_usb3_port_disable()
1641 	{ 0, "pcie", 0 },
1643 	{ 1, "sata", 0 },
1644 	{ 0, NULL,   0 },
1668 	if (err < 0)  in tegra124_xusb_read_fuse_calibration()
1671 	for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {  in tegra124_xusb_read_fuse_calibration()
1686 	return 0;  in tegra124_xusb_read_fuse_calibration()
1704 	if (err < 0)  in tegra124_xusb_padctl_probe()