115 static int stm32_impedance_tune(struct stm32_combophy *combophy)  in stm32_impedance_tune()  argument
127 	if (!of_property_read_u32(combophy->dev->of_node, "st,output-micro-ohms", &val)) {  in stm32_impedance_tune()
129 			dev_err(combophy->dev, "Invalid value %u for output ohm\n", val);  in stm32_impedance_tune()
141 		dev_dbg(combophy->dev, "Set %u micro-ohms output impedance\n",  in stm32_impedance_tune()
144 		regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,  in stm32_impedance_tune()
148 		regmap_read(combophy->regmap, SYSCFG_PCIEPRGCR, &val);  in stm32_impedance_tune()
152 	if (!of_property_read_u32(combophy->dev->of_node, "st,output-vswing-microvolt", &val)) {  in stm32_impedance_tune()
154 			dev_err(combophy->dev, "Invalid value %u for output vswing\n", val);  in stm32_impedance_tune()
166 		dev_dbg(combophy->dev, "Set %u microvolt swing\n",  in stm32_impedance_tune()
169 		regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,  in stm32_impedance_tune()
177 static int stm32_combophy_pll_init(struct stm32_combophy *combophy)  in stm32_combophy_pll_init()  argument
185 	if (combophy->have_pad_clk)  in stm32_combophy_pll_init()
186 		clk = combophy->clks[PAD_CLK].clk;  in stm32_combophy_pll_init()
188 		clk = combophy->clks[KER_CLK].clk;  in stm32_combophy_pll_init()
192 	dev_dbg(combophy->dev, "%s pll init rate %d\n",  in stm32_combophy_pll_init()
193 		combophy->have_pad_clk ? "External" : "Ker", clk_rate);  in stm32_combophy_pll_init()
195 	if (combophy->type != PHY_TYPE_PCIE) {  in stm32_combophy_pll_init()
200 	if (of_property_present(combophy->dev->of_node, "st,ssc-on")) {  in stm32_combophy_pll_init()
201 		dev_dbg(combophy->dev, "Enabling clock with SSC\n");  in stm32_combophy_pll_init()
233 		dev_err(combophy->dev, "Invalid rate 0x%x\n", clk_rate);  in stm32_combophy_pll_init()
250 	regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2,  in stm32_combophy_pll_init()
253 	reset_control_assert(combophy->phy_reset);  in stm32_combophy_pll_init()
255 	if (combophy->type == PHY_TYPE_PCIE) {  in stm32_combophy_pll_init()
256 		ret = stm32_impedance_tune(combophy);  in stm32_combophy_pll_init()
261 		cr1_val |= combophy->have_pad_clk ? SYSCFG_COMBOPHY_CR1_REFUSEPAD : 0;  in stm32_combophy_pll_init()
264 	if (!of_property_read_u32(combophy->dev->of_node, "st,rx-equalizer", &val)) {  in stm32_combophy_pll_init()
265 		dev_dbg(combophy->dev, "Set RX equalizer %u\n", val);  in stm32_combophy_pll_init()
267 			dev_err(combophy->dev, "Invalid value %u for rx0 equalizer\n", val);  in stm32_combophy_pll_init()
272 		regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR4,  in stm32_combophy_pll_init()
276 	regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1, cr1_mask, cr1_val);  in stm32_combophy_pll_init()
282 	regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR5,  in stm32_combophy_pll_init()
285 	reset_control_deassert(combophy->phy_reset);  in stm32_combophy_pll_init()
287 	ret = regmap_read_poll_timeout(combophy->regmap, SYSCFG_COMBOPHY_SR, val,  in stm32_combophy_pll_init()
291 		dev_err(combophy->dev, "timeout, cannot lock PLL\n");  in stm32_combophy_pll_init()
292 		if (combophy->type == PHY_TYPE_PCIE && !combophy->have_pad_clk)  in stm32_combophy_pll_init()
293 			regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,  in stm32_combophy_pll_init()
296 		if (combophy->type != PHY_TYPE_PCIE)  in stm32_combophy_pll_init()
297 			regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1,  in stm32_combophy_pll_init()
304 	if (combophy->type == PHY_TYPE_PCIE) {  in stm32_combophy_pll_init()
305 		if (!combophy->have_pad_clk)  in stm32_combophy_pll_init()
306 			regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,  in stm32_combophy_pll_init()
309 		val = readl_relaxed(combophy->base + COMBOPHY_SUP_ANA_MPLL_LOOP_CTL);  in stm32_combophy_pll_init()
312 		writel_relaxed(val, combophy->base + COMBOPHY_SUP_ANA_MPLL_LOOP_CTL);  in stm32_combophy_pll_init()
318 	reset_control_deassert(combophy->phy_reset);  in stm32_combophy_pll_init()
321 	regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2,  in stm32_combophy_pll_init()
330 	struct stm32_combophy *combophy = dev_get_drvdata(dev);  in stm32_combophy_xlate()  local
344 	if (combophy->have_pad_clk && type != PHY_TYPE_PCIE) {  in stm32_combophy_xlate()
349 	combophy->type = type;  in stm32_combophy_xlate()
351 	return combophy->phy;  in stm32_combophy_xlate()
354 static int stm32_combophy_set_mode(struct stm32_combophy *combophy)  in stm32_combophy_set_mode()  argument
356 	int type = combophy->type;  in stm32_combophy_set_mode()
361 		dev_dbg(combophy->dev, "setting PCIe ComboPHY\n");  in stm32_combophy_set_mode()
365 		dev_dbg(combophy->dev, "setting USB3 ComboPHY\n");  in stm32_combophy_set_mode()
369 		dev_err(combophy->dev, "Invalid PHY mode %d\n", type);  in stm32_combophy_set_mode()
373 	return regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2,  in stm32_combophy_set_mode()
379 	struct stm32_combophy *combophy = dev_get_drvdata(dev);  in stm32_combophy_suspend_noirq()  local
386 	if (combophy->is_init) {  in stm32_combophy_suspend_noirq()
387 		clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks);  in stm32_combophy_suspend_noirq()
390 		enable_irq_wake(combophy->irq_wakeup);  in stm32_combophy_suspend_noirq()
398 	struct stm32_combophy *combophy = dev_get_drvdata(dev);  in stm32_combophy_resume_noirq()  local
406 	if (combophy->is_init) {  in stm32_combophy_resume_noirq()
408 		disable_irq_wake(combophy->irq_wakeup);  in stm32_combophy_resume_noirq()
410 		ret = clk_bulk_prepare_enable(combophy->num_clks, combophy->clks);  in stm32_combophy_resume_noirq()
422 	struct stm32_combophy *combophy = phy_get_drvdata(phy);  in stm32_combophy_exit()  local
423 	struct device *dev = combophy->dev;  in stm32_combophy_exit()
425 	combophy->is_init = false;  in stm32_combophy_exit()
427 	if (combophy->type == PHY_TYPE_PCIE && !combophy->have_pad_clk)  in stm32_combophy_exit()
428 		regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,  in stm32_combophy_exit()
431 	if (combophy->type != PHY_TYPE_PCIE)  in stm32_combophy_exit()
432 		regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1,  in stm32_combophy_exit()
435 	regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2,  in stm32_combophy_exit()
438 	clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks);  in stm32_combophy_exit()
447 	struct stm32_combophy *combophy = phy_get_drvdata(phy);  in stm32_combophy_init()  local
448 	struct device *dev = combophy->dev;  in stm32_combophy_init()
453 	ret = clk_bulk_prepare_enable(combophy->num_clks, combophy->clks);  in stm32_combophy_init()
460 	ret = stm32_combophy_set_mode(combophy);  in stm32_combophy_init()
463 		clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks);  in stm32_combophy_init()
468 	ret = stm32_combophy_pll_init(combophy);  in stm32_combophy_init()
470 		clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks);  in stm32_combophy_init()
479 	combophy->is_init = true;  in stm32_combophy_init()
495 static int stm32_combophy_get_clocks(struct stm32_combophy *combophy)  in stm32_combophy_get_clocks()  argument
500 		combophy->clks[i].id = combophy_clks[i];  in stm32_combophy_get_clocks()
502 	combophy->num_clks = ARRAY_SIZE(combophy_clks) - 1;  in stm32_combophy_get_clocks()
504 	ret = devm_clk_bulk_get(combophy->dev, combophy->num_clks, combophy->clks);  in stm32_combophy_get_clocks()
508 	ret = devm_clk_bulk_get_optional(combophy->dev, 1, combophy->clks + combophy->num_clks);  in stm32_combophy_get_clocks()
512 	if (combophy->clks[combophy->num_clks].clk != NULL) {  in stm32_combophy_get_clocks()
513 		combophy->have_pad_clk = true;  in stm32_combophy_get_clocks()
514 		combophy->num_clks++;  in stm32_combophy_get_clocks()
522 	struct stm32_combophy *combophy;  in stm32_combophy_probe()  local
527 	combophy = devm_kzalloc(dev, sizeof(*combophy), GFP_KERNEL);  in stm32_combophy_probe()
528 	if (!combophy)  in stm32_combophy_probe()
531 	combophy->dev = dev;  in stm32_combophy_probe()
533 	dev_set_drvdata(dev, combophy);  in stm32_combophy_probe()
535 	combophy->base = devm_platform_ioremap_resource(pdev, 0);  in stm32_combophy_probe()
536 	if (IS_ERR(combophy->base))  in stm32_combophy_probe()
537 		return PTR_ERR(combophy->base);  in stm32_combophy_probe()
539 	ret = stm32_combophy_get_clocks(combophy);  in stm32_combophy_probe()
543 	combophy->phy_reset = devm_reset_control_get_exclusive(dev, "phy");  in stm32_combophy_probe()
544 	if (IS_ERR(combophy->phy_reset))  in stm32_combophy_probe()
545 		return dev_err_probe(dev, PTR_ERR(combophy->phy_reset),  in stm32_combophy_probe()
548 	combophy->regmap = syscon_regmap_lookup_by_compatible("st,stm32mp25-syscfg");  in stm32_combophy_probe()
549 	if (IS_ERR(combophy->regmap))  in stm32_combophy_probe()
550 		return dev_err_probe(dev, PTR_ERR(combophy->regmap),  in stm32_combophy_probe()
553 	combophy->phy = devm_phy_create(dev, NULL, &stm32_combophy_phy_data);  in stm32_combophy_probe()
554 	if (IS_ERR(combophy->phy))  in stm32_combophy_probe()
555 		return dev_err_probe(dev, PTR_ERR(combophy->phy),  in stm32_combophy_probe()
562 		combophy->irq_wakeup = irq;  in stm32_combophy_probe()
564 		ret = devm_request_threaded_irq(dev, combophy->irq_wakeup, NULL,  in stm32_combophy_probe()
569 						 combophy->irq_wakeup);  in stm32_combophy_probe()
576 	phy_set_drvdata(combophy->phy, combophy);  in stm32_combophy_probe()