Lines Matching +full:0 +full:x31c
23 #define SPEAR1340_PCM_CFG 0x100
25 #define SPEAR1340_PCM_WKUP_CFG 0x104
26 #define SPEAR1340_SWITCH_CTR 0x108
28 #define SPEAR1340_PERIP1_SW_RST 0x318
30 #define SPEAR1340_PERIP2_SW_RST 0x31C
31 #define SPEAR1340_PERIP3_SW_RST 0x320
34 #define SPEAR1340_PCIE_SATA_CFG 0x424
44 #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
46 #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
58 #define SPEAR1340_PCIE_MIPHY_CFG 0x428
63 #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
64 #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
81 /* phy mode: 0 for SATA 1 for PCIe */
106 SPEAR1340_PERIP1_SW_RSATA, 0); in spear1340_miphy_sata_init()
110 return 0; in spear1340_miphy_sata_init()
116 SPEAR1340_PCIE_SATA_CFG_MASK, 0); in spear1340_miphy_sata_exit()
118 SPEAR1340_PCIE_MIPHY_CFG_MASK, 0); in spear1340_miphy_sata_exit()
128 SPEAR1340_PCM_CFG_SATA_POWER_EN, 0); in spear1340_miphy_sata_exit()
132 return 0; in spear1340_miphy_sata_exit()
144 return 0; in spear1340_miphy_pcie_init()
150 SPEAR1340_PCIE_MIPHY_CFG_MASK, 0); in spear1340_miphy_pcie_exit()
152 SPEAR1340_PCIE_SATA_CFG_MASK, 0); in spear1340_miphy_pcie_exit()
154 return 0; in spear1340_miphy_pcie_exit()
160 int ret = 0; in spear1340_miphy_init()
173 int ret = 0; in spear1340_miphy_exit()
199 int ret = 0; in spear1340_miphy_suspend()
210 int ret = 0; in spear1340_miphy_resume()
232 priv->mode = args->args[0]; in spear1340_miphy_xlate()
275 return 0; in spear1340_miphy_probe()