1 // SPDX-License-Identifier: GPL-2.0
3  * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
15 #include <linux/phy/phy.h>
21 /* PHY */
80 	writel(data, priv->base + PCL_PHY_TEST_I);  in uniphier_pciephy_testio_write()
81 	readl(priv->base + PCL_PHY_TEST_O);  in uniphier_pciephy_testio_write()
82 	readl(priv->base + PCL_PHY_TEST_O);  in uniphier_pciephy_testio_write()
87 	u32 val = readl(priv->base + PCL_PHY_TEST_O);  in uniphier_pciephy_testio_read()
126 	val = readl(priv->base + PCL_PHY_RESET);  in uniphier_pciephy_assert()
129 	writel(val, priv->base + PCL_PHY_RESET);  in uniphier_pciephy_assert()
136 	val = readl(priv->base + PCL_PHY_RESET);  in uniphier_pciephy_deassert()
138 	writel(val, priv->base + PCL_PHY_RESET);  in uniphier_pciephy_deassert()
141 static int uniphier_pciephy_init(struct phy *phy)  in uniphier_pciephy_init()  argument
143 	struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);  in uniphier_pciephy_init()
147 	ret = clk_prepare_enable(priv->clk);  in uniphier_pciephy_init()
151 	ret = clk_prepare_enable(priv->clk_gio);  in uniphier_pciephy_init()
155 	ret = reset_control_deassert(priv->rst);  in uniphier_pciephy_init()
159 	ret = reset_control_deassert(priv->rst_gio);  in uniphier_pciephy_init()
164 	val = readl(priv->base + PCL_PHY_CLKCTRL);  in uniphier_pciephy_init()
167 	writel(val, priv->base + PCL_PHY_CLKCTRL);  in uniphier_pciephy_init()
170 	if (priv->data->is_legacy)  in uniphier_pciephy_init()
173 	for (id = 0; id < (priv->data->is_dual_phy ? 2 : 1); id++) {  in uniphier_pciephy_init()
191 	reset_control_assert(priv->rst);  in uniphier_pciephy_init()
193 	clk_disable_unprepare(priv->clk_gio);  in uniphier_pciephy_init()
195 	clk_disable_unprepare(priv->clk);  in uniphier_pciephy_init()
200 static int uniphier_pciephy_exit(struct phy *phy)  in uniphier_pciephy_exit()  argument
202 	struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);  in uniphier_pciephy_exit()
204 	if (!priv->data->is_legacy)  in uniphier_pciephy_exit()
206 	reset_control_assert(priv->rst_gio);  in uniphier_pciephy_exit()
207 	reset_control_assert(priv->rst);  in uniphier_pciephy_exit()
208 	clk_disable_unprepare(priv->clk_gio);  in uniphier_pciephy_exit()
209 	clk_disable_unprepare(priv->clk);  in uniphier_pciephy_exit()
224 	struct device *dev = &pdev->dev;  in uniphier_pciephy_probe()
226 	struct phy *phy;  in uniphier_pciephy_probe()  local
230 		return -ENOMEM;  in uniphier_pciephy_probe()
232 	priv->data = of_device_get_match_data(dev);  in uniphier_pciephy_probe()
233 	if (WARN_ON(!priv->data))  in uniphier_pciephy_probe()
234 		return -EINVAL;  in uniphier_pciephy_probe()
236 	priv->dev = dev;  in uniphier_pciephy_probe()
238 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in uniphier_pciephy_probe()
239 	if (IS_ERR(priv->base))  in uniphier_pciephy_probe()
240 		return PTR_ERR(priv->base);  in uniphier_pciephy_probe()
242 	if (priv->data->is_legacy) {  in uniphier_pciephy_probe()
243 		priv->clk_gio = devm_clk_get(dev, "gio");  in uniphier_pciephy_probe()
244 		if (IS_ERR(priv->clk_gio))  in uniphier_pciephy_probe()
245 			return PTR_ERR(priv->clk_gio);  in uniphier_pciephy_probe()
247 		priv->rst_gio =  in uniphier_pciephy_probe()
249 		if (IS_ERR(priv->rst_gio))  in uniphier_pciephy_probe()
250 			return PTR_ERR(priv->rst_gio);  in uniphier_pciephy_probe()
252 		priv->clk = devm_clk_get(dev, "link");  in uniphier_pciephy_probe()
253 		if (IS_ERR(priv->clk))  in uniphier_pciephy_probe()
254 			return PTR_ERR(priv->clk);  in uniphier_pciephy_probe()
256 		priv->rst = devm_reset_control_get_shared(dev, "link");  in uniphier_pciephy_probe()
257 		if (IS_ERR(priv->rst))  in uniphier_pciephy_probe()
258 			return PTR_ERR(priv->rst);  in uniphier_pciephy_probe()
260 		priv->clk = devm_clk_get(dev, NULL);  in uniphier_pciephy_probe()
261 		if (IS_ERR(priv->clk))  in uniphier_pciephy_probe()
262 			return PTR_ERR(priv->clk);  in uniphier_pciephy_probe()
264 		priv->rst = devm_reset_control_get_shared(dev, NULL);  in uniphier_pciephy_probe()
265 		if (IS_ERR(priv->rst))  in uniphier_pciephy_probe()
266 			return PTR_ERR(priv->rst);  in uniphier_pciephy_probe()
269 	phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);  in uniphier_pciephy_probe()
270 	if (IS_ERR(phy))  in uniphier_pciephy_probe()
271 		return PTR_ERR(phy);  in uniphier_pciephy_probe()
273 	regmap = syscon_regmap_lookup_by_phandle(dev->of_node,  in uniphier_pciephy_probe()
275 	if (!IS_ERR(regmap) && priv->data->set_phymode)  in uniphier_pciephy_probe()
276 		priv->data->set_phymode(regmap);  in uniphier_pciephy_probe()
278 	phy_set_drvdata(phy, priv);  in uniphier_pciephy_probe()
319 		.compatible = "socionext,uniphier-pro5-pcie-phy",
323 		.compatible = "socionext,uniphier-ld20-pcie-phy",
327 		.compatible = "socionext,uniphier-pxs3-pcie-phy",
331 		.compatible = "socionext,uniphier-nx1-pcie-phy",
341 		.name = "uniphier-pcie-phy",
348 MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller");