Lines Matching +full:orientation +full:- +full:switch
1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
253 /* Exynos9 - GS101 */
387 for (; (tune)->region != PTR_INVALID; ++(tune))
441 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
449 * @hs_phy: pointer to non-Samsung IP high-speed phy controller
456 * @sw: TypeC orientation switch handle
457 * @orientation: TypeC connector orientation - normal or flipped
480 enum typec_orientation orientation; member
487 phys[(inst)->index]); in to_usbdrd_phy()
498 switch (rate) { in exynos5_rate_to_clk()
524 return -EINVAL; in exynos5_rate_to_clk()
535 if (!inst->reg_pmu) in exynos5_usbdrd_phy_isol()
540 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, in exynos5_usbdrd_phy_isol()
556 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_pipe3_set_refclk()
566 switch (phy_drd->extrefclk) { in exynos5_usbdrd_pipe3_set_refclk()
588 dev_dbg(phy_drd->dev, "unsupported ref clk\n"); in exynos5_usbdrd_pipe3_set_refclk()
606 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_utmi_set_refclk()
614 reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); in exynos5_usbdrd_utmi_set_refclk()
625 tune = phy_drd->drv_data->phy_tunes[state]; in exynos5_usbdrd_apply_phy_tunes()
633 switch (tune->region) { in exynos5_usbdrd_apply_phy_tunes()
635 reg_base = phy_drd->reg_phy; in exynos5_usbdrd_apply_phy_tunes()
638 reg_base = phy_drd->reg_pcs; in exynos5_usbdrd_apply_phy_tunes()
641 reg_base = phy_drd->reg_pma; in exynos5_usbdrd_apply_phy_tunes()
644 dev_warn_once(phy_drd->dev, in exynos5_usbdrd_apply_phy_tunes()
645 "unknown phy region %d\n", tune->region); in exynos5_usbdrd_apply_phy_tunes()
649 if (~tune->mask) { in exynos5_usbdrd_apply_phy_tunes()
650 reg = readl(reg_base + tune->off); in exynos5_usbdrd_apply_phy_tunes()
651 reg &= ~tune->mask; in exynos5_usbdrd_apply_phy_tunes()
653 reg |= tune->val; in exynos5_usbdrd_apply_phy_tunes()
654 writel(reg, reg_base + tune->off); in exynos5_usbdrd_apply_phy_tunes()
662 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_pipe3_init()
663 /* Set Tx De-Emphasis level */ in exynos5_usbdrd_pipe3_init()
666 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_pipe3_init()
668 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_pipe3_init()
670 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_pipe3_init()
676 void __iomem *regs_base = phy_drd->reg_phy; in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
720 void __iomem *regs_base = phy_drd->reg_pma; in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel()
731 ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel()
740 if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) { in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel()
751 if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) { in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel()
772 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_CMN_REG01C0, in exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock()
775 dev_err(phy_drd->dev, in exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock()
795 /* lane depends on cable orientation */ in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
796 (phy_drd->reg_pma in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
797 + ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
802 dev_err(phy_drd->dev, in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
804 ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
813 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_utmi_init()
814 /* Set Loss-of-Signal Detector sensitivity */ in exynos5_usbdrd_utmi_init()
817 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_utmi_init()
819 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_utmi_init()
820 /* Set Tx De-Emphasis level */ in exynos5_usbdrd_utmi_init()
823 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_utmi_init()
826 writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos5_usbdrd_utmi_init()
828 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_utmi_init()
830 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_utmi_init()
840 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_init()
845 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in exynos5_usbdrd_phy_init()
846 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME); in exynos5_usbdrd_phy_init()
854 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); in exynos5_usbdrd_phy_init()
856 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_phy_init()
859 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_phy_init()
862 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); in exynos5_usbdrd_phy_init()
864 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); in exynos5_usbdrd_phy_init()
867 inst->phy_cfg->phy_init(phy_drd); in exynos5_usbdrd_phy_init()
870 reg = inst->phy_cfg->set_refclk(inst); in exynos5_usbdrd_phy_init()
883 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_init()
888 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_init()
890 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_init()
902 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_exit()
909 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos5_usbdrd_phy_exit()
912 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_exit()
916 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_exit()
919 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_phy_exit()
922 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_phy_exit()
924 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_exit()
935 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); in exynos5_usbdrd_phy_power_on()
937 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_power_on()
938 phy_drd->core_clks); in exynos5_usbdrd_phy_power_on()
943 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_phy_power_on()
944 phy_drd->regulators); in exynos5_usbdrd_phy_power_on()
946 dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); in exynos5_usbdrd_phy_power_on()
950 /* Power-on PHY */ in exynos5_usbdrd_phy_power_on()
951 inst->phy_cfg->phy_isol(inst, false); in exynos5_usbdrd_phy_power_on()
956 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_power_on()
957 phy_drd->core_clks); in exynos5_usbdrd_phy_power_on()
967 dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); in exynos5_usbdrd_phy_power_off()
969 /* Power-off the PHY */ in exynos5_usbdrd_phy_power_off()
970 inst->phy_cfg->phy_isol(inst, true); in exynos5_usbdrd_phy_power_off()
973 regulator_bulk_disable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_phy_power_off()
974 phy_drd->regulators); in exynos5_usbdrd_phy_power_off()
976 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_power_off()
977 phy_drd->core_clks); in exynos5_usbdrd_phy_power_off()
988 writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_handshake()
990 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1, in crport_handshake()
992 if (err == -ETIMEDOUT) { in crport_handshake()
993 dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val); in crport_handshake()
997 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_handshake()
999 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1, in crport_handshake()
1001 if (err == -ETIMEDOUT) { in crport_handshake()
1002 dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val); in crport_handshake()
1017 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_ctrl_write()
1024 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_ctrl_write()
1057 dev_err(phy_drd->dev, in exynos5420_usbdrd_phy_calibrate()
1058 "Failed setting Loss-of-Signal level for SuperSpeed\n"); in exynos5420_usbdrd_phy_calibrate()
1071 dev_err(phy_drd->dev, in exynos5420_usbdrd_phy_calibrate()
1072 "Failed setting Tx-Vboost-Level for SuperSpeed\n"); in exynos5420_usbdrd_phy_calibrate()
1083 * e.g. Samsung SUM-TSB16S 3.0 USB drive. in exynos5420_usbdrd_phy_calibrate()
1085 switch (phy_drd->extrefclk) { in exynos5420_usbdrd_phy_calibrate()
1103 dev_err(phy_drd->dev, in exynos5420_usbdrd_phy_calibrate()
1114 if (WARN_ON(args->args[0] >= EXYNOS5_DRDPHYS_NUM)) in exynos5_usbdrd_phy_xlate()
1115 return ERR_PTR(-ENODEV); in exynos5_usbdrd_phy_xlate()
1117 return phy_drd->phys[args->args[0]].phy; in exynos5_usbdrd_phy_xlate()
1125 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) in exynos5_usbdrd_phy_calibrate()
1144 if (!inst->reg_pmu) in exynos7870_usbdrd_phy_isol()
1149 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, in exynos7870_usbdrd_phy_isol()
1157 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos7870_usbdrd_utmi_init()
1164 reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); in exynos7870_usbdrd_utmi_init()
1169 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos7870_usbdrd_utmi_init()
1174 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos7870_usbdrd_utmi_init()
1177 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); in exynos7870_usbdrd_utmi_init()
1178 if (phy_drd->extrefclk == EXYNOS5_FSEL_24MHZ) in exynos7870_usbdrd_utmi_init()
1184 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); in exynos7870_usbdrd_utmi_init()
1186 /* High-Speed PHY control */ in exynos7870_usbdrd_utmi_init()
1187 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_utmi_init()
1191 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_utmi_init()
1194 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); in exynos7870_usbdrd_utmi_init()
1205 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); in exynos7870_usbdrd_utmi_init()
1207 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos7870_usbdrd_utmi_init()
1215 /* Set DP-pull up as the VBUS pad is not used */ in exynos7870_usbdrd_utmi_init()
1220 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos7870_usbdrd_utmi_init()
1223 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKPORT); in exynos7870_usbdrd_utmi_init()
1225 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKPORT); in exynos7870_usbdrd_utmi_init()
1227 /* High-Speed PHY swrst */ in exynos7870_usbdrd_utmi_init()
1228 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_utmi_init()
1230 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_utmi_init()
1234 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_utmi_init()
1236 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_utmi_init()
1238 if (phy_drd->drv_data->phy_tunes) in exynos7870_usbdrd_utmi_init()
1249 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos7870_usbdrd_phy_init()
1254 inst->phy_cfg->phy_init(phy_drd); in exynos7870_usbdrd_phy_init()
1256 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos7870_usbdrd_phy_init()
1268 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos7870_usbdrd_phy_exit()
1273 * Disable the VBUS signal and the ID pull-up resistor. in exynos7870_usbdrd_phy_exit()
1274 * Enable force-suspend and force-sleep modes. in exynos7870_usbdrd_phy_exit()
1276 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos7870_usbdrd_phy_exit()
1280 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos7870_usbdrd_phy_exit()
1283 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_phy_exit()
1285 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); in exynos7870_usbdrd_phy_exit()
1288 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); in exynos7870_usbdrd_phy_exit()
1290 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); in exynos7870_usbdrd_phy_exit()
1292 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos7870_usbdrd_phy_exit()
1307 /* Configure non-Samsung IP PHY, responsible for UTMI */ in exynos2200_usbdrd_utmi_init()
1308 phy_init(phy_drd->hs_phy); in exynos2200_usbdrd_utmi_init()
1313 void __iomem *regs_base = phy_drd->reg_phy; in exynos2200_usbdrd_link_init()
1318 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure in exynos2200_usbdrd_link_init()
1325 /* De-assert link reset */ in exynos2200_usbdrd_link_init()
1340 void __iomem *regs_base = phy_drd->reg_phy; in exynos2200_usbdrd_link_attach_detach_pipe3_phy()
1344 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { in exynos2200_usbdrd_link_attach_detach_pipe3_phy()
1355 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { in exynos2200_usbdrd_link_attach_detach_pipe3_phy()
1367 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) in exynos2200_usbdrd_link_attach_detach_pipe3_phy()
1381 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { in exynos2200_usbdrd_phy_init()
1382 /* Power-on PHY ... */ in exynos2200_usbdrd_phy_init()
1383 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, in exynos2200_usbdrd_phy_init()
1384 phy_drd->regulators); in exynos2200_usbdrd_phy_init()
1386 dev_err(phy_drd->dev, in exynos2200_usbdrd_phy_init()
1397 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos2200_usbdrd_phy_init()
1408 inst->phy_cfg->phy_init(phy_drd); in exynos2200_usbdrd_phy_init()
1410 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos2200_usbdrd_phy_init()
1419 void __iomem *regs_base = phy_drd->reg_phy; in exynos2200_usbdrd_phy_exit()
1423 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos2200_usbdrd_phy_exit()
1435 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos2200_usbdrd_phy_exit()
1438 return regulator_bulk_disable(phy_drd->drv_data->n_regulators, in exynos2200_usbdrd_phy_exit()
1439 phy_drd->regulators); in exynos2200_usbdrd_phy_exit()
1451 void __iomem *regs_base = phy_drd->reg_phy; in exynos5_usbdrd_usb_v3p1_pipe_override()
1468 void __iomem *regs_base = phy_drd->reg_phy; in exynos850_usbdrd_utmi_init()
1474 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure in exynos850_usbdrd_utmi_init()
1505 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ in exynos850_usbdrd_utmi_init()
1510 if (!phy_drd->sw) { in exynos850_usbdrd_utmi_init()
1522 switch (phy_drd->extrefclk) { in exynos850_usbdrd_utmi_init()
1539 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", in exynos850_usbdrd_utmi_init()
1540 phy_drd->extrefclk); in exynos850_usbdrd_utmi_init()
1545 if (phy_drd->drv_data->phy_tunes) in exynos850_usbdrd_utmi_init()
1580 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_init()
1585 scoped_guard(mutex, &phy_drd->phy_mutex) in exynos850_usbdrd_phy_init()
1586 inst->phy_cfg->phy_init(phy_drd); in exynos850_usbdrd_phy_init()
1588 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_init()
1597 void __iomem *regs_base = phy_drd->reg_phy; in exynos850_usbdrd_phy_exit()
1601 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_exit()
1605 guard(mutex)(&phy_drd->phy_mutex); in exynos850_usbdrd_phy_exit()
1626 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_exit()
1641 void __iomem *regs_pma = phy_drd->reg_pma; in exynos5_usbdrd_gs101_pipe3_init()
1642 void __iomem *regs_phy = phy_drd->reg_phy; in exynos5_usbdrd_gs101_pipe3_init()
1675 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { in exynos5_usbdrd_gs101_phy_init()
1676 /* Power-on PHY ... */ in exynos5_usbdrd_gs101_phy_init()
1677 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_gs101_phy_init()
1678 phy_drd->regulators); in exynos5_usbdrd_gs101_phy_init()
1680 dev_err(phy_drd->dev, in exynos5_usbdrd_gs101_phy_init()
1700 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { in exynos5_usbdrd_gs101_phy_exit()
1708 if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI) in exynos5_usbdrd_gs101_phy_exit()
1711 return regulator_bulk_disable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_gs101_phy_exit()
1712 phy_drd->regulators); in exynos5_usbdrd_gs101_phy_exit()
1727 phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks, in exynos5_usbdrd_phy_clk_handle()
1728 sizeof(*phy_drd->clks), GFP_KERNEL); in exynos5_usbdrd_phy_clk_handle()
1729 if (!phy_drd->clks) in exynos5_usbdrd_phy_clk_handle()
1730 return -ENOMEM; in exynos5_usbdrd_phy_clk_handle()
1732 for (int i = 0; i < phy_drd->drv_data->n_clks; ++i) in exynos5_usbdrd_phy_clk_handle()
1733 phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i]; in exynos5_usbdrd_phy_clk_handle()
1735 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks, in exynos5_usbdrd_phy_clk_handle()
1736 phy_drd->clks); in exynos5_usbdrd_phy_clk_handle()
1738 return dev_err_probe(phy_drd->dev, ret, in exynos5_usbdrd_phy_clk_handle()
1741 phy_drd->core_clks = devm_kcalloc(phy_drd->dev, in exynos5_usbdrd_phy_clk_handle()
1742 phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_clk_handle()
1743 sizeof(*phy_drd->core_clks), in exynos5_usbdrd_phy_clk_handle()
1745 if (!phy_drd->core_clks) in exynos5_usbdrd_phy_clk_handle()
1746 return -ENOMEM; in exynos5_usbdrd_phy_clk_handle()
1748 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) in exynos5_usbdrd_phy_clk_handle()
1749 phy_drd->core_clks[i].id = phy_drd->drv_data->core_clk_names[i]; in exynos5_usbdrd_phy_clk_handle()
1751 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_clk_handle()
1752 phy_drd->core_clks); in exynos5_usbdrd_phy_clk_handle()
1754 return dev_err_probe(phy_drd->dev, ret, in exynos5_usbdrd_phy_clk_handle()
1757 if (phy_drd->drv_data->n_core_clks) { in exynos5_usbdrd_phy_clk_handle()
1759 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) { in exynos5_usbdrd_phy_clk_handle()
1760 if (!strcmp(phy_drd->core_clks[i].id, "ref")) { in exynos5_usbdrd_phy_clk_handle()
1761 ref_clk = phy_drd->core_clks[i].clk; in exynos5_usbdrd_phy_clk_handle()
1766 return dev_err_probe(phy_drd->dev, -ENODEV, in exynos5_usbdrd_phy_clk_handle()
1770 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk); in exynos5_usbdrd_phy_clk_handle()
1772 return dev_err_probe(phy_drd->dev, ret, in exynos5_usbdrd_phy_clk_handle()
1789 enum typec_orientation orientation) in exynos5_usbdrd_orien_sw_set() argument
1794 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_orien_sw_set()
1796 dev_err(phy_drd->dev, "Failed to enable PHY clocks(s)\n"); in exynos5_usbdrd_orien_sw_set()
1800 scoped_guard(mutex, &phy_drd->phy_mutex) { in exynos5_usbdrd_orien_sw_set()
1801 void __iomem * const regs_base = phy_drd->reg_phy; in exynos5_usbdrd_orien_sw_set()
1804 if (orientation == TYPEC_ORIENTATION_NONE) { in exynos5_usbdrd_orien_sw_set()
1823 phy_drd->orientation = orientation; in exynos5_usbdrd_orien_sw_set()
1826 clk_bulk_disable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_orien_sw_set()
1835 typec_switch_unregister(phy_drd->sw); in exynos5_usbdrd_orien_switch_unregister()
1845 if (device_property_present(phy_drd->dev, "orientation-switch")) { in exynos5_usbdrd_setup_notifiers()
1849 sw_desc.fwnode = dev_fwnode(phy_drd->dev); in exynos5_usbdrd_setup_notifiers()
1852 phy_drd->sw = typec_switch_register(phy_drd->dev, &sw_desc); in exynos5_usbdrd_setup_notifiers()
1853 if (IS_ERR(phy_drd->sw)) in exynos5_usbdrd_setup_notifiers()
1854 return dev_err_probe(phy_drd->dev, in exynos5_usbdrd_setup_notifiers()
1855 PTR_ERR(phy_drd->sw), in exynos5_usbdrd_setup_notifiers()
1856 "Failed to register TypeC orientation switch\n"); in exynos5_usbdrd_setup_notifiers()
1858 ret = devm_add_action_or_reset(phy_drd->dev, in exynos5_usbdrd_setup_notifiers()
1862 return dev_err_probe(phy_drd->dev, ret, in exynos5_usbdrd_setup_notifiers()
1863 "Failed to register TypeC orientation devm action\n"); in exynos5_usbdrd_setup_notifiers()
1937 "vbus", "vbus-boost",
2057 PHY_TUNING_ENTRY_PMA(0x0c8c, -1, 0xff),
2058 PHY_TUNING_ENTRY_PMA(0x1c8c, -1, 0xff),
2059 PHY_TUNING_ENTRY_PMA(0x0c9c, -1, 0x7d),
2060 PHY_TUNING_ENTRY_PMA(0x1c9c, -1, 0x7d),
2062 PHY_TUNING_ENTRY_PMA(0x0e7c, -1, 0x06),
2063 PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00),
2064 PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36),
2065 PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06),
2066 PHY_TUNING_ENTRY_PMA(0x19e0, -1, 0x00),
2067 PHY_TUNING_ENTRY_PMA(0x19e4, -1, 0x36),
2069 PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x02),
2070 PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x0b),
2072 PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30),
2073 PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30),
2075 PHY_TUNING_ENTRY_PMA(0x0a08, -1, 0x0c),
2076 PHY_TUNING_ENTRY_PMA(0x1a08, -1, 0x0c),
2078 PHY_TUNING_ENTRY_PMA(0x0a0c, -1, 0x05),
2079 PHY_TUNING_ENTRY_PMA(0x1a0c, -1, 0x05),
2081 PHY_TUNING_ENTRY_PMA(0x00f8, -1, 0x1c),
2082 PHY_TUNING_ENTRY_PMA(0x00fc, -1, 0x54),
2084 PHY_TUNING_ENTRY_PMA(0x104c, -1, 0x07),
2085 PHY_TUNING_ENTRY_PMA(0x204c, -1, 0x07),
2088 PHY_TUNING_ENTRY_PMA(0x0ca8, -1, 0x00),
2089 PHY_TUNING_ENTRY_PMA(0x0cac, -1, 0x04),
2090 PHY_TUNING_ENTRY_PMA(0x1ca8, -1, 0x00),
2091 PHY_TUNING_ENTRY_PMA(0x1cac, -1, 0x04),
2093 PHY_TUNING_ENTRY_PMA(0x0cb8, -1, 0x00),
2094 PHY_TUNING_ENTRY_PMA(0x0cbc, -1, 0x04),
2095 PHY_TUNING_ENTRY_PMA(0x1cb8, -1, 0x00),
2096 PHY_TUNING_ENTRY_PMA(0x1cbc, -1, 0x04),
2111 /* de-serializer enabled when U2 */
2117 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS1_N1, -1,
2121 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS2_N0, -1,
2127 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS3_N0, -1,
2133 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_0, -1, 112),
2142 * increase pcs ts1 adding packet-cnt 1 --> 4
2144 * 19.6us(0x200) -> 15.3us(0x4)
2147 /* Gen1 Tx DRIVER pre-shoot, de-emphasis, level ctrl */
2159 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_3, -1, 4096),
2160 /* set skp_remove_th 0x2 -> 0x7 for avoiding retry problem. */
2188 "dvdd-usb20", "vddh-usb20", "vdd33-usb20",
2189 "vdda-usbdp", "vddh-usbdp",
2208 .compatible = "google,gs101-usb31drd-phy",
2211 .compatible = "samsung,exynos2200-usb32drd-phy",
2214 .compatible = "samsung,exynos5250-usbdrd-phy",
2217 .compatible = "samsung,exynos5420-usbdrd-phy",
2220 .compatible = "samsung,exynos5433-usbdrd-phy",
2223 .compatible = "samsung,exynos7-usbdrd-phy",
2226 .compatible = "samsung,exynos7870-usbdrd-phy",
2229 .compatible = "samsung,exynos850-usbdrd-phy",
2238 struct device *dev = &pdev->dev; in exynos5_usbdrd_phy_probe()
2239 struct device_node *node = dev->of_node; in exynos5_usbdrd_phy_probe()
2250 return -ENOMEM; in exynos5_usbdrd_phy_probe()
2253 phy_drd->dev = dev; in exynos5_usbdrd_phy_probe()
2257 return -EINVAL; in exynos5_usbdrd_phy_probe()
2258 phy_drd->drv_data = drv_data; in exynos5_usbdrd_phy_probe()
2260 ret = devm_mutex_init(dev, &phy_drd->phy_mutex); in exynos5_usbdrd_phy_probe()
2264 if (of_property_present(dev->of_node, "reg-names")) { in exynos5_usbdrd_phy_probe()
2270 phy_drd->reg_phy = reg; in exynos5_usbdrd_phy_probe()
2275 phy_drd->reg_pcs = reg; in exynos5_usbdrd_phy_probe()
2280 phy_drd->reg_pma = reg; in exynos5_usbdrd_phy_probe()
2283 phy_drd->reg_phy = devm_platform_ioremap_resource(pdev, 0); in exynos5_usbdrd_phy_probe()
2284 if (IS_ERR(phy_drd->reg_phy)) in exynos5_usbdrd_phy_probe()
2285 return PTR_ERR(phy_drd->reg_phy); in exynos5_usbdrd_phy_probe()
2292 if (of_property_present(dev->of_node, "phy-names")) { in exynos5_usbdrd_phy_probe()
2293 phy_drd->hs_phy = devm_of_phy_get(dev, dev->of_node, "hs"); in exynos5_usbdrd_phy_probe()
2294 if (IS_ERR(phy_drd->hs_phy)) in exynos5_usbdrd_phy_probe()
2295 return dev_err_probe(dev, PTR_ERR(phy_drd->hs_phy), in exynos5_usbdrd_phy_probe()
2303 reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, in exynos5_usbdrd_phy_probe()
2304 "samsung,pmu-syscon"); in exynos5_usbdrd_phy_probe()
2316 dev_dbg(dev, "Not a multi-controller usbdrd phy\n"); in exynos5_usbdrd_phy_probe()
2319 phy_drd->regulators = devm_kcalloc(dev, in exynos5_usbdrd_phy_probe()
2320 drv_data->n_regulators, in exynos5_usbdrd_phy_probe()
2321 sizeof(*phy_drd->regulators), in exynos5_usbdrd_phy_probe()
2323 if (!phy_drd->regulators) in exynos5_usbdrd_phy_probe()
2324 return -ENOMEM; in exynos5_usbdrd_phy_probe()
2325 regulator_bulk_set_supply_names(phy_drd->regulators, in exynos5_usbdrd_phy_probe()
2326 drv_data->regulator_names, in exynos5_usbdrd_phy_probe()
2327 drv_data->n_regulators); in exynos5_usbdrd_phy_probe()
2328 ret = devm_regulator_bulk_get(dev, drv_data->n_regulators, in exynos5_usbdrd_phy_probe()
2329 phy_drd->regulators); in exynos5_usbdrd_phy_probe()
2340 struct phy *phy = devm_phy_create(dev, NULL, drv_data->phy_ops); in exynos5_usbdrd_phy_probe()
2346 phy_drd->phys[i].phy = phy; in exynos5_usbdrd_phy_probe()
2347 phy_drd->phys[i].index = i; in exynos5_usbdrd_phy_probe()
2348 phy_drd->phys[i].reg_pmu = reg_pmu; in exynos5_usbdrd_phy_probe()
2349 switch (channel) { in exynos5_usbdrd_phy_probe()
2351 pmu_offset = drv_data->pmu_offset_usbdrd1_phy; in exynos5_usbdrd_phy_probe()
2355 pmu_offset = drv_data->pmu_offset_usbdrd0_phy; in exynos5_usbdrd_phy_probe()
2357 ->pmu_offset_usbdrd0_phy_ss) in exynos5_usbdrd_phy_probe()
2358 pmu_offset = drv_data->pmu_offset_usbdrd0_phy_ss; in exynos5_usbdrd_phy_probe()
2361 phy_drd->phys[i].pmu_offset = pmu_offset; in exynos5_usbdrd_phy_probe()
2362 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i]; in exynos5_usbdrd_phy_probe()
2363 phy_set_drvdata(phy, &phy_drd->phys[i]); in exynos5_usbdrd_phy_probe()
2369 return dev_err_probe(phy_drd->dev, PTR_ERR(phy_provider), in exynos5_usbdrd_phy_probe()