Lines Matching +full:exynos5420 +full:- +full:usbdrd +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos5 SoC series USB DRD PHY driver
5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
19 #include <linux/phy/phy.h>
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
27 /* Exynos USB PHY registers */
37 /* Exynos5: USB 3.0 DRD PHY registers */
116 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
135 /* Exynos850: USB DRD PHY registers */
149 * On versions without SS ports (like E850), bit 3 is for the 2.0 phy (HS),
150 * while on versions with (like gs101), bits 2 and 3 are for the 3.0 phy (SS)
151 * and bits 12 & 13 for the 2.0 phy.
194 /* Exynos9 - GS101 */
324 for (; (tune)->region != PTR_INVALID; ++(tune))
378 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
380 * @reg_phy: usb phy controller register memory base
381 * @reg_pcs: usb phy physical coding sublayer register memory base
382 * @reg_pma: usb phy physical media attachment register memory base
384 * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
386 * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
387 * instances each with its 'phy' and 'phy_cfg'.
390 * @regulators: regulators for phy
401 struct phy *phy; member
415 phys[(inst)->index]); in to_usbdrd_phy()
420 * can be written to the phy register.
452 return -EINVAL; in exynos5_rate_to_clk()
463 if (!inst->reg_pmu) in exynos5_usbdrd_phy_isol()
468 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, in exynos5_usbdrd_phy_isol()
473 * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
484 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_pipe3_set_refclk()
494 switch (phy_drd->extrefclk) { in exynos5_usbdrd_pipe3_set_refclk()
512 dev_dbg(phy_drd->dev, "unsupported ref clk\n"); in exynos5_usbdrd_pipe3_set_refclk()
520 * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
530 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_utmi_set_refclk()
538 reg |= PHYCLKRST_FSEL(phy_drd->extrefclk); in exynos5_usbdrd_utmi_set_refclk()
549 tune = phy_drd->drv_data->phy_tunes[state]; in exynos5_usbdrd_apply_phy_tunes()
557 switch (tune->region) { in exynos5_usbdrd_apply_phy_tunes()
559 reg_base = phy_drd->reg_phy; in exynos5_usbdrd_apply_phy_tunes()
562 reg_base = phy_drd->reg_pcs; in exynos5_usbdrd_apply_phy_tunes()
565 reg_base = phy_drd->reg_pma; in exynos5_usbdrd_apply_phy_tunes()
568 dev_warn_once(phy_drd->dev, in exynos5_usbdrd_apply_phy_tunes()
569 "unknown phy region %d\n", tune->region); in exynos5_usbdrd_apply_phy_tunes()
573 if (~tune->mask) { in exynos5_usbdrd_apply_phy_tunes()
574 reg = readl(reg_base + tune->off); in exynos5_usbdrd_apply_phy_tunes()
575 reg &= ~tune->mask; in exynos5_usbdrd_apply_phy_tunes()
577 reg |= tune->val; in exynos5_usbdrd_apply_phy_tunes()
578 writel(reg, reg_base + tune->off); in exynos5_usbdrd_apply_phy_tunes()
586 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_pipe3_init()
587 /* Set Tx De-Emphasis level */ in exynos5_usbdrd_pipe3_init()
590 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_pipe3_init()
592 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_pipe3_init()
594 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_pipe3_init()
600 void __iomem *regs_base = phy_drd->reg_phy; in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
644 void __iomem *regs_base = phy_drd->reg_pma; in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel()
680 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_CMN_REG01C0, in exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock()
683 dev_err(phy_drd->dev, in exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock()
703 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG03C3, in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
708 dev_err(phy_drd->dev, in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
711 /* based on cable orientation, this might be on the other phy port */ in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
713 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG07C3, in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
716 dev_err(phy_drd->dev, in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
724 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_utmi_init()
725 /* Set Loss-of-Signal Detector sensitivity */ in exynos5_usbdrd_utmi_init()
728 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_utmi_init()
730 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_utmi_init()
731 /* Set Tx De-Emphasis level */ in exynos5_usbdrd_utmi_init()
734 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); in exynos5_usbdrd_utmi_init()
737 writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos5_usbdrd_utmi_init()
739 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_utmi_init()
741 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_utmi_init()
744 static int exynos5_usbdrd_phy_init(struct phy *phy) in exynos5_usbdrd_phy_init() argument
748 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos5_usbdrd_phy_init()
751 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_init()
755 /* Reset USB 3.0 PHY */ in exynos5_usbdrd_phy_init()
756 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in exynos5_usbdrd_phy_init()
757 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME); in exynos5_usbdrd_phy_init()
765 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); in exynos5_usbdrd_phy_init()
767 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_phy_init()
768 /* Select PHY CLK source */ in exynos5_usbdrd_phy_init()
770 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); in exynos5_usbdrd_phy_init()
773 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); in exynos5_usbdrd_phy_init()
775 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); in exynos5_usbdrd_phy_init()
778 inst->phy_cfg->phy_init(phy_drd); in exynos5_usbdrd_phy_init()
781 reg = inst->phy_cfg->set_refclk(inst); in exynos5_usbdrd_phy_init()
794 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_init()
799 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_init()
801 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_init()
806 static int exynos5_usbdrd_phy_exit(struct phy *phy) in exynos5_usbdrd_phy_exit() argument
810 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos5_usbdrd_phy_exit()
813 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_exit()
820 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); in exynos5_usbdrd_phy_exit()
823 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_exit()
827 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_phy_exit()
830 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_phy_exit()
833 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); in exynos5_usbdrd_phy_exit()
835 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos5_usbdrd_phy_exit()
840 static int exynos5_usbdrd_phy_power_on(struct phy *phy) in exynos5_usbdrd_phy_power_on() argument
843 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos5_usbdrd_phy_power_on()
846 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); in exynos5_usbdrd_phy_power_on()
848 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_power_on()
849 phy_drd->core_clks); in exynos5_usbdrd_phy_power_on()
854 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_phy_power_on()
855 phy_drd->regulators); in exynos5_usbdrd_phy_power_on()
857 dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); in exynos5_usbdrd_phy_power_on()
861 /* Power-on PHY */ in exynos5_usbdrd_phy_power_on()
862 inst->phy_cfg->phy_isol(inst, false); in exynos5_usbdrd_phy_power_on()
867 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_power_on()
868 phy_drd->core_clks); in exynos5_usbdrd_phy_power_on()
873 static int exynos5_usbdrd_phy_power_off(struct phy *phy) in exynos5_usbdrd_phy_power_off() argument
875 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos5_usbdrd_phy_power_off()
878 dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); in exynos5_usbdrd_phy_power_off()
880 /* Power-off the PHY */ in exynos5_usbdrd_phy_power_off()
881 inst->phy_cfg->phy_isol(inst, true); in exynos5_usbdrd_phy_power_off()
884 regulator_bulk_disable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_phy_power_off()
885 phy_drd->regulators); in exynos5_usbdrd_phy_power_off()
887 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_power_off()
888 phy_drd->core_clks); in exynos5_usbdrd_phy_power_off()
899 writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_handshake()
901 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1, in crport_handshake()
903 if (err == -ETIMEDOUT) { in crport_handshake()
904 dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val); in crport_handshake()
908 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_handshake()
910 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1, in crport_handshake()
912 if (err == -ETIMEDOUT) { in crport_handshake()
913 dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val); in crport_handshake()
927 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_ctrl_write()
935 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); in crport_ctrl_write()
948 * Calibrate few PHY parameters using CR_PORT register to meet
949 * SuperSpeed requirements on Exynos5420 and Exynos5800 systems,
950 * which have 28nm USB 3.0 DRD PHY.
958 * Change los_bias to (0x5) for 28nm PHY from a in exynos5420_usbdrd_phy_calibrate()
970 dev_err(phy_drd->dev, in exynos5420_usbdrd_phy_calibrate()
971 "Failed setting Loss-of-Signal level for SuperSpeed\n"); in exynos5420_usbdrd_phy_calibrate()
976 * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning, in exynos5420_usbdrd_phy_calibrate()
984 dev_err(phy_drd->dev, in exynos5420_usbdrd_phy_calibrate()
985 "Failed setting Tx-Vboost-Level for SuperSpeed\n"); in exynos5420_usbdrd_phy_calibrate()
991 * desired reference clock of PHY, by tuning the CR_PORT in exynos5420_usbdrd_phy_calibrate()
992 * register LANE0.TX_DEBUG which is internal to PHY. in exynos5420_usbdrd_phy_calibrate()
996 * e.g. Samsung SUM-TSB16S 3.0 USB drive. in exynos5420_usbdrd_phy_calibrate()
998 switch (phy_drd->extrefclk) { in exynos5420_usbdrd_phy_calibrate()
1016 dev_err(phy_drd->dev, in exynos5420_usbdrd_phy_calibrate()
1022 static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, in exynos5_usbdrd_phy_xlate()
1027 if (WARN_ON(args->args[0] >= EXYNOS5_DRDPHYS_NUM)) in exynos5_usbdrd_phy_xlate()
1028 return ERR_PTR(-ENODEV); in exynos5_usbdrd_phy_xlate()
1030 return phy_drd->phys[args->args[0]].phy; in exynos5_usbdrd_phy_xlate()
1033 static int exynos5_usbdrd_phy_calibrate(struct phy *phy) in exynos5_usbdrd_phy_calibrate() argument
1035 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos5_usbdrd_phy_calibrate()
1038 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) in exynos5_usbdrd_phy_calibrate()
1055 void __iomem *regs_base = phy_drd->reg_phy; in exynos5_usbdrd_usb_v3p1_pipe_override()
1072 void __iomem *regs_base = phy_drd->reg_phy; in exynos850_usbdrd_utmi_init()
1078 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure in exynos850_usbdrd_utmi_init()
1079 * the PHY clock is not gated by the hardware. in exynos850_usbdrd_utmi_init()
1088 /* Start PHY Reset (POR=high) */ in exynos850_usbdrd_utmi_init()
1104 /* Set PHY clock and control HS PHY */ in exynos850_usbdrd_utmi_init()
1109 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ in exynos850_usbdrd_utmi_init()
1124 switch (phy_drd->extrefclk) { in exynos850_usbdrd_utmi_init()
1141 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", in exynos850_usbdrd_utmi_init()
1142 phy_drd->extrefclk); in exynos850_usbdrd_utmi_init()
1147 if (phy_drd->drv_data->phy_tunes) in exynos850_usbdrd_utmi_init()
1151 /* Power up PHY analog blocks */ in exynos850_usbdrd_utmi_init()
1156 /* Finish PHY reset (POR=low) */ in exynos850_usbdrd_utmi_init()
1165 fsleep(75); /* required after POR=low for guaranteed PHY clock */ in exynos850_usbdrd_utmi_init()
1176 static int exynos850_usbdrd_phy_init(struct phy *phy) in exynos850_usbdrd_phy_init() argument
1178 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos850_usbdrd_phy_init()
1182 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_init()
1187 inst->phy_cfg->phy_init(phy_drd); in exynos850_usbdrd_phy_init()
1189 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_init()
1194 static int exynos850_usbdrd_phy_exit(struct phy *phy) in exynos850_usbdrd_phy_exit() argument
1196 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos850_usbdrd_phy_exit()
1198 void __iomem *regs_base = phy_drd->reg_phy; in exynos850_usbdrd_phy_exit()
1202 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_exit()
1206 /* Set PHY clock and control HS PHY */ in exynos850_usbdrd_phy_exit()
1212 /* Power down PHY analog blocks */ in exynos850_usbdrd_phy_exit()
1225 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); in exynos850_usbdrd_phy_exit()
1240 void __iomem *regs_pma = phy_drd->reg_pma; in exynos5_usbdrd_gs101_pipe3_init()
1241 void __iomem *regs_phy = phy_drd->reg_phy; in exynos5_usbdrd_gs101_pipe3_init()
1268 static int exynos5_usbdrd_gs101_phy_init(struct phy *phy) in exynos5_usbdrd_gs101_phy_init() argument
1270 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos5_usbdrd_gs101_phy_init()
1274 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { in exynos5_usbdrd_gs101_phy_init()
1275 /* Power-on PHY ... */ in exynos5_usbdrd_gs101_phy_init()
1276 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_gs101_phy_init()
1277 phy_drd->regulators); in exynos5_usbdrd_gs101_phy_init()
1279 dev_err(phy_drd->dev, in exynos5_usbdrd_gs101_phy_init()
1280 "Failed to enable PHY regulator(s)\n"); in exynos5_usbdrd_gs101_phy_init()
1290 return exynos850_usbdrd_phy_init(phy); in exynos5_usbdrd_gs101_phy_init()
1293 static int exynos5_usbdrd_gs101_phy_exit(struct phy *phy) in exynos5_usbdrd_gs101_phy_exit() argument
1295 struct phy_usb_instance *inst = phy_get_drvdata(phy); in exynos5_usbdrd_gs101_phy_exit()
1299 if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI) in exynos5_usbdrd_gs101_phy_exit()
1302 ret = exynos850_usbdrd_phy_exit(phy); in exynos5_usbdrd_gs101_phy_exit()
1307 return regulator_bulk_disable(phy_drd->drv_data->n_regulators, in exynos5_usbdrd_gs101_phy_exit()
1308 phy_drd->regulators); in exynos5_usbdrd_gs101_phy_exit()
1323 phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks, in exynos5_usbdrd_phy_clk_handle()
1324 sizeof(*phy_drd->clks), GFP_KERNEL); in exynos5_usbdrd_phy_clk_handle()
1325 if (!phy_drd->clks) in exynos5_usbdrd_phy_clk_handle()
1326 return -ENOMEM; in exynos5_usbdrd_phy_clk_handle()
1328 for (int i = 0; i < phy_drd->drv_data->n_clks; ++i) in exynos5_usbdrd_phy_clk_handle()
1329 phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i]; in exynos5_usbdrd_phy_clk_handle()
1331 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks, in exynos5_usbdrd_phy_clk_handle()
1332 phy_drd->clks); in exynos5_usbdrd_phy_clk_handle()
1334 return dev_err_probe(phy_drd->dev, ret, in exynos5_usbdrd_phy_clk_handle()
1335 "failed to get phy clock(s)\n"); in exynos5_usbdrd_phy_clk_handle()
1337 phy_drd->core_clks = devm_kcalloc(phy_drd->dev, in exynos5_usbdrd_phy_clk_handle()
1338 phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_clk_handle()
1339 sizeof(*phy_drd->core_clks), in exynos5_usbdrd_phy_clk_handle()
1341 if (!phy_drd->core_clks) in exynos5_usbdrd_phy_clk_handle()
1342 return -ENOMEM; in exynos5_usbdrd_phy_clk_handle()
1344 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) in exynos5_usbdrd_phy_clk_handle()
1345 phy_drd->core_clks[i].id = phy_drd->drv_data->core_clk_names[i]; in exynos5_usbdrd_phy_clk_handle()
1347 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_core_clks, in exynos5_usbdrd_phy_clk_handle()
1348 phy_drd->core_clks); in exynos5_usbdrd_phy_clk_handle()
1350 return dev_err_probe(phy_drd->dev, ret, in exynos5_usbdrd_phy_clk_handle()
1351 "failed to get phy core clock(s)\n"); in exynos5_usbdrd_phy_clk_handle()
1354 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) { in exynos5_usbdrd_phy_clk_handle()
1355 if (!strcmp(phy_drd->core_clks[i].id, "ref")) { in exynos5_usbdrd_phy_clk_handle()
1356 ref_clk = phy_drd->core_clks[i].clk; in exynos5_usbdrd_phy_clk_handle()
1361 return dev_err_probe(phy_drd->dev, -ENODEV, in exynos5_usbdrd_phy_clk_handle()
1362 "failed to find phy reference clock\n"); in exynos5_usbdrd_phy_clk_handle()
1365 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk); in exynos5_usbdrd_phy_clk_handle()
1367 return dev_err_probe(phy_drd->dev, ret, in exynos5_usbdrd_phy_clk_handle()
1398 "phy",
1410 "vbus", "vbus-boost",
1504 PHY_TUNING_ENTRY_PMA(0x0c8c, -1, 0xff),
1505 PHY_TUNING_ENTRY_PMA(0x1c8c, -1, 0xff),
1506 PHY_TUNING_ENTRY_PMA(0x0c9c, -1, 0x7d),
1507 PHY_TUNING_ENTRY_PMA(0x1c9c, -1, 0x7d),
1509 PHY_TUNING_ENTRY_PMA(0x0e7c, -1, 0x06),
1510 PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00),
1511 PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36),
1512 PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06),
1513 PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x00),
1514 PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x36),
1516 PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30),
1517 PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30),
1519 PHY_TUNING_ENTRY_PMA(0x0a08, -1, 0x0c),
1520 PHY_TUNING_ENTRY_PMA(0x1a08, -1, 0x0c),
1521 /* remove unrelated option for v4 phy */
1522 PHY_TUNING_ENTRY_PMA(0x0a0c, -1, 0x05),
1523 PHY_TUNING_ENTRY_PMA(0x1a0c, -1, 0x05),
1525 PHY_TUNING_ENTRY_PMA(0x00f8, -1, 0x1c),
1526 PHY_TUNING_ENTRY_PMA(0x00fc, -1, 0x54),
1528 PHY_TUNING_ENTRY_PMA(0x104c, -1, 0x07),
1529 PHY_TUNING_ENTRY_PMA(0x204c, -1, 0x07),
1532 PHY_TUNING_ENTRY_PMA(0x0ca8, -1, 0x00),
1533 PHY_TUNING_ENTRY_PMA(0x0cac, -1, 0x04),
1534 PHY_TUNING_ENTRY_PMA(0x1ca8, -1, 0x00),
1535 PHY_TUNING_ENTRY_PMA(0x1cac, -1, 0x04),
1537 PHY_TUNING_ENTRY_PMA(0x0cb8, -1, 0x00),
1538 PHY_TUNING_ENTRY_PMA(0x0cbc, -1, 0x04),
1539 PHY_TUNING_ENTRY_PMA(0x1cb8, -1, 0x00),
1540 PHY_TUNING_ENTRY_PMA(0x1cbc, -1, 0x04),
1555 /* de-serializer enabled when U2 */
1561 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS1_N1, -1,
1565 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS2_N0, -1,
1571 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS3_N0, -1,
1577 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_0, -1, 112),
1586 * increase pcs ts1 adding packet-cnt 1 --> 4
1588 * 19.6us(0x200) -> 15.3us(0x4)
1591 /* Gen1 Tx DRIVER pre-shoot, de-emphasis, level ctrl */
1603 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_3, -1, 4096),
1604 /* set skp_remove_th 0x2 -> 0x7 for avoiding retry problem. */
1627 "phy", "ctrl_aclk", "ctrl_pclk", "scl_pclk",
1632 "dvdd-usb20", "vddh-usb20", "vdd33-usb20",
1633 "vdda-usbdp", "vddh-usbdp",
1652 .compatible = "google,gs101-usb31drd-phy",
1655 .compatible = "samsung,exynos5250-usbdrd-phy",
1658 .compatible = "samsung,exynos5420-usbdrd-phy",
1661 .compatible = "samsung,exynos5433-usbdrd-phy",
1664 .compatible = "samsung,exynos7-usbdrd-phy",
1667 .compatible = "samsung,exynos850-usbdrd-phy",
1676 struct device *dev = &pdev->dev; in exynos5_usbdrd_phy_probe()
1677 struct device_node *node = dev->of_node; in exynos5_usbdrd_phy_probe()
1688 return -ENOMEM; in exynos5_usbdrd_phy_probe()
1691 phy_drd->dev = dev; in exynos5_usbdrd_phy_probe()
1695 return -EINVAL; in exynos5_usbdrd_phy_probe()
1696 phy_drd->drv_data = drv_data; in exynos5_usbdrd_phy_probe()
1698 if (of_property_present(dev->of_node, "reg-names")) { in exynos5_usbdrd_phy_probe()
1701 reg = devm_platform_ioremap_resource_byname(pdev, "phy"); in exynos5_usbdrd_phy_probe()
1704 phy_drd->reg_phy = reg; in exynos5_usbdrd_phy_probe()
1709 phy_drd->reg_pcs = reg; in exynos5_usbdrd_phy_probe()
1714 phy_drd->reg_pma = reg; in exynos5_usbdrd_phy_probe()
1717 phy_drd->reg_phy = devm_platform_ioremap_resource(pdev, 0); in exynos5_usbdrd_phy_probe()
1718 if (IS_ERR(phy_drd->reg_phy)) in exynos5_usbdrd_phy_probe()
1719 return PTR_ERR(phy_drd->reg_phy); in exynos5_usbdrd_phy_probe()
1726 reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, in exynos5_usbdrd_phy_probe()
1727 "samsung,pmu-syscon"); in exynos5_usbdrd_phy_probe()
1734 * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with in exynos5_usbdrd_phy_probe()
1740 dev_dbg(dev, "Not a multi-controller usbdrd phy\n"); in exynos5_usbdrd_phy_probe()
1743 phy_drd->regulators = devm_kcalloc(dev, in exynos5_usbdrd_phy_probe()
1744 drv_data->n_regulators, in exynos5_usbdrd_phy_probe()
1745 sizeof(*phy_drd->regulators), in exynos5_usbdrd_phy_probe()
1747 if (!phy_drd->regulators) in exynos5_usbdrd_phy_probe()
1748 return -ENOMEM; in exynos5_usbdrd_phy_probe()
1749 regulator_bulk_set_supply_names(phy_drd->regulators, in exynos5_usbdrd_phy_probe()
1750 drv_data->regulator_names, in exynos5_usbdrd_phy_probe()
1751 drv_data->n_regulators); in exynos5_usbdrd_phy_probe()
1752 ret = devm_regulator_bulk_get(dev, drv_data->n_regulators, in exynos5_usbdrd_phy_probe()
1753 phy_drd->regulators); in exynos5_usbdrd_phy_probe()
1757 dev_vdbg(dev, "Creating usbdrd_phy phy\n"); in exynos5_usbdrd_phy_probe()
1760 struct phy *phy = devm_phy_create(dev, NULL, drv_data->phy_ops); in exynos5_usbdrd_phy_probe() local
1762 if (IS_ERR(phy)) { in exynos5_usbdrd_phy_probe()
1763 dev_err(dev, "Failed to create usbdrd_phy phy\n"); in exynos5_usbdrd_phy_probe()
1764 return PTR_ERR(phy); in exynos5_usbdrd_phy_probe()
1767 phy_drd->phys[i].phy = phy; in exynos5_usbdrd_phy_probe()
1768 phy_drd->phys[i].index = i; in exynos5_usbdrd_phy_probe()
1769 phy_drd->phys[i].reg_pmu = reg_pmu; in exynos5_usbdrd_phy_probe()
1772 pmu_offset = drv_data->pmu_offset_usbdrd1_phy; in exynos5_usbdrd_phy_probe()
1776 pmu_offset = drv_data->pmu_offset_usbdrd0_phy; in exynos5_usbdrd_phy_probe()
1778 ->pmu_offset_usbdrd0_phy_ss) in exynos5_usbdrd_phy_probe()
1779 pmu_offset = drv_data->pmu_offset_usbdrd0_phy_ss; in exynos5_usbdrd_phy_probe()
1782 phy_drd->phys[i].pmu_offset = pmu_offset; in exynos5_usbdrd_phy_probe()
1783 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i]; in exynos5_usbdrd_phy_probe()
1784 phy_set_drvdata(phy, &phy_drd->phys[i]); in exynos5_usbdrd_phy_probe()
1790 dev_err(phy_drd->dev, "Failed to register phy provider\n"); in exynos5_usbdrd_phy_probe()
1807 MODULE_DESCRIPTION("Samsung Exynos5 SoCs USB 3.0 DRD controller PHY driver");