30 #define EXYNOS5_FSEL_9MHZ6		0x0
31 #define EXYNOS5_FSEL_10MHZ		0x1
32 #define EXYNOS5_FSEL_12MHZ		0x2
33 #define EXYNOS5_FSEL_19MHZ2		0x3
34 #define EXYNOS5_FSEL_20MHZ		0x4
35 #define EXYNOS5_FSEL_24MHZ		0x5
36 #define EXYNOS5_FSEL_26MHZ		0x6
37 #define EXYNOS5_FSEL_50MHZ		0x7
40 #define EXYNOS2200_DRD_CLKRST			0x0c
43 #define EXYNOS2200_DRD_UTMI			0x10
45 #define EXYNOS2200_UTMI_FORCE_BVALID		BIT(0)
47 #define EXYNOS2200_DRD_HSP_MISC			0x114
49 #define HSP_MISC_RES_TUNE			GENMASK(1, 0)
50 #define RES_TUNE_PHY1_PHY2			0x1
51 #define RES_TUNE_PHY1				0x2
52 #define RES_TUNE_PHY2				0x3
55 #define EXYNOS5_DRD_LINKSYSTEM			0x04
61 #define EXYNOS5_DRD_PHYUTMI			0x08
74 #define PHYUTMI_FORCESLEEP			BIT(0)
76 #define EXYNOS5_DRD_PHYPIPE			0x0c
78 #define EXYNOS5_DRD_PHYCLKRST			0x10
86 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF	0x19
87 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF	0x32
88 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF	0x68
89 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF	0x7d
90 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF	0x02
93 #define PHYCLKRST_FSEL_PAD_100MHZ		0x27
94 #define PHYCLKRST_FSEL_PAD_24MHZ		0x2a
95 #define PHYCLKRST_FSEL_PAD_20MHZ		0x31
96 #define PHYCLKRST_FSEL_PAD_19_2MHZ		0x38
99 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK		0x2
100 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK		0x3
102 #define PHYCLKRST_COMMONONN			BIT(0)
104 #define EXYNOS5_DRD_PHYREG0			0x14
111 #define PHYREG0_CR_CAP_ADDR			BIT(0)
113 #define EXYNOS5_DRD_PHYREG1			0x18
115 #define PHYREG1_CR_ACK				BIT(0)
117 #define EXYNOS5_DRD_PHYPARAM0			0x1c
120 #define PHYPARAM0_REF_LOSLEVEL_VAL		0x9
130 #define PHYPARAM0_COMPDISTUNE			GENMASK(2, 0)
132 #define EXYNOS5_DRD_PHYPARAM1			0x20
133 #define PHYPARAM1_PCS_TXDEEMPH			GENMASK(4, 0)
134 #define PHYPARAM1_PCS_TXDEEMPH_VAL		0x1c
136 #define EXYNOS5_DRD_PHYTERM			0x24
138 #define EXYNOS5_DRD_PHYTEST			0x28
142 #define EXYNOS5_DRD_PHYADP			0x2c
144 #define EXYNOS5_DRD_PHYUTMICLKSEL		0x30
147 #define EXYNOS5_DRD_PHYRESUME			0x34
149 #define EXYNOS5_DRD_LINKPORT			0x44
158 #define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN		(0x15)
159 #define LOSLEVEL_OVRD_IN_LOS_BIAS_5420			(0x5 << 13)
160 #define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT		(0x0 << 13)
161 #define LOSLEVEL_OVRD_IN_EN				(0x1 << 10)
162 #define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT		(0x9 << 0)
164 #define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN	(0x12)
165 #define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420		(0x5 << 13)
166 #define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT		(0x4 << 13)
168 #define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG		(0x1010)
169 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M		(0x4 << 4)
170 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M		(0x8 << 4)
171 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M		(0x8 << 4)
172 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M	(0x20 << 4)
173 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5		(0x20 << 4)
174 #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M		(0x40 << 4)
177 #define EXYNOS7870_DRD_PHYPCSVAL		0x3C
178 #define PHYPCSVAL_PCS_RX_LOS_MASK		GENMASK(9, 0)
180 #define EXYNOS7870_DRD_PHYPARAM2		0x50
182 #define PHYPARAM2_LOS_BIAS			GENMASK(2, 0)
184 #define EXYNOS7870_DRD_HSPHYCTRL		0x54
187 #define HSPHYCTRL_PHYSWRST			BIT(0)
189 #define EXYNOS7870_DRD_HSPHYPLLTUNE		0x70
192 #define HSPHYPLLTUNE_PLL_P_TUNE			GENMASK(3, 0)
195 #define EXYNOS850_DRD_LINKCTRL			0x04
202 #define EXYNOS850_DRD_LINKPORT			0x08
206 #define EXYNOS850_DRD_CLKRST			0x20
218 #define CLKRST_LINK_SW_RST			BIT(0)
220 #define EXYNOS850_DRD_SSPPLLCTL			0x30
221 #define SSPPLLCTL_FSEL				GENMASK(2, 0)
223 #define EXYNOS850_DRD_UTMI			0x50
229 #define UTMI_FORCE_SLEEP			BIT(0)
231 #define EXYNOS850_DRD_HSP			0x54
238 #define EXYNOS850_DRD_HSPPARACON		0x58
248 #define HSPPARACON_COMPDIS			GENMASK(2, 0)
250 #define EXYNOS850_DRD_HSP_TEST			0x5c
254 #define EXYNOS850_DRD_SECPMACTL			0x48
262 #define SECPMACTL_PMA_APB_SW_RST		BIT(0)
265 #define EXYNOS9_PMA_USBDP_CMN_REG0008		0x0020
269 #define EXYNOS9_PMA_USBDP_CMN_REG00B8		0x02e0
270 #define CMN_REG00B8_LANE_MUX_SEL_DP		GENMASK(3, 0)
274 #define CMN_REG00B8_LANE_MUX_SEL_DP_LANE0	BIT(0)
276 #define EXYNOS9_PMA_USBDP_CMN_REG01C0		0x0700
280 /* these have similar register layout, for lanes 0 and 2 */
281 #define EXYNOS9_PMA_USBDP_TRSV_REG03C3			0x0f0c
282 #define EXYNOS9_PMA_USBDP_TRSV_REG07C3			0x1f0c
286 #define TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE		BIT(0)
289 #define EXYNOS9_PMA_USBDP_TRSV_REG0413		0x104c
293 #define EXYNOS9_PMA_USBDP_TRSV_REG0813		0x204c
298 #define EXYNOS9_PCS_NS_VEC_PS1_N1		0x010c
299 #define EXYNOS9_PCS_NS_VEC_PS2_N0		0x0110
300 #define EXYNOS9_PCS_NS_VEC_PS3_N0		0x0118
306 #define NS_VEC_EXP_COND				GENMASK(3, 0)
308 #define EXYNOS9_PCS_OUT_VEC_2			0x014c
309 #define EXYNOS9_PCS_OUT_VEC_3			0x0150
329 #define PCS_OUT_VEC_B0_SEL_OUT			BIT(0)
331 #define EXYNOS9_PCS_TIMEOUT_0			0x0170
333 #define EXYNOS9_PCS_TIMEOUT_3			0x017c
335 #define EXYNOS9_PCS_EBUF_PARAM			0x0304
338 #define EXYNOS9_PCS_BACK_END_MODE_VEC		0x030c
340 #define BACK_END_MODE_VEC_DISABLE_DATA_MASK	BIT(0)
342 #define EXYNOS9_PCS_RX_CONTROL			0x03f0
345 #define EXYNOS9_PCS_RX_CONTROL_DEBUG		0x03f4
347 #define RX_CONTROL_DEBUG_NUM_COM_FOUND		GENMASK(3, 0)
349 #define EXYNOS9_PCS_LOCAL_COEF			0x040c
352 #define LOCAL_COEF_FS				GENMASK(5, 0)
354 #define EXYNOS9_PCS_HS_TX_COEF_MAP_0		0x0410
357 #define HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT		GENMASK(5, 0)
394 #define PTR_INVALID	0
527 	return 0;  in exynos5_rate_to_clk()
538 	val = isolate ? 0 : EXYNOS4_PHY_ENABLE;  in exynos5_usbdrd_phy_isol()
568 		reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) |  in exynos5_usbdrd_pipe3_set_refclk()
573 		reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) |  in exynos5_usbdrd_pipe3_set_refclk()
578 		reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) |  in exynos5_usbdrd_pipe3_set_refclk()
583 		reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) |  in exynos5_usbdrd_pipe3_set_refclk()
631 		u32 reg = 0;  in exynos5_usbdrd_apply_phy_tunes()
727 	 * USB on lanes 0 & 1 in normal mode, or 2 & 3 if reversed, DP on the  in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel()
805 			 ? 0  in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock()
845 	writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);  in exynos5_usbdrd_phy_init()
846 	writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);  in exynos5_usbdrd_phy_init()
849 	 * Setting the Frame length Adj value[6:1] to default 0x20  in exynos5_usbdrd_phy_init()
853 		FIELD_PREP(LINKSYSTEM_FLADJ, 0x20);  in exynos5_usbdrd_phy_init()
892 	return 0;  in exynos5_usbdrd_phy_init()
926 	return 0;  in exynos5_usbdrd_phy_exit()
953 	return 0;  in exynos5_usbdrd_phy_power_on()
979 	return 0;  in exynos5_usbdrd_phy_power_off()
993 		dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val);  in crport_handshake()
1002 		dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val);  in crport_handshake()
1006 	return 0;  in crport_handshake()
1042 	int ret = 0;  in exynos5420_usbdrd_phy_calibrate()
1045 	 * Change los_bias to (0x5) for 28nm PHY from a  in exynos5420_usbdrd_phy_calibrate()
1046 	 * default value (0x0); los_level is set as default  in exynos5420_usbdrd_phy_calibrate()
1047 	 * (0x9) as also reflected in los_level[30:26] bits  in exynos5420_usbdrd_phy_calibrate()
1063 	 * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,  in exynos5420_usbdrd_phy_calibrate()
1064 	 * to raise Tx signal level from its default value of (0x4)  in exynos5420_usbdrd_phy_calibrate()
1114 	if (WARN_ON(args->args[0] >= EXYNOS5_DRDPHYS_NUM))  in exynos5_usbdrd_phy_xlate()
1117 	return phy_drd->phys[args->args[0]].phy;  in exynos5_usbdrd_phy_xlate()
1127 	return 0;  in exynos5_usbdrd_phy_calibrate()
1147 	val = isolate ? 0 : EXYNOS7870_USB2PHY_ENABLE;  in exynos7870_usbdrd_phy_isol()
1196 	 * Setting the Frame length Adj value[6:1] to default 0x20  in exynos7870_usbdrd_utmi_init()
1201 	reg |= FIELD_PREP(LINKSYSTEM_FLADJ, 0x20);  in exynos7870_usbdrd_utmi_init()
1258 	return 0;  in exynos7870_usbdrd_phy_init()
1294 	return 0;  in exynos7870_usbdrd_phy_exit()
1412 	return 0;  in exynos2200_usbdrd_phy_init()
1507 	reg |= FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf);  in exynos850_usbdrd_utmi_init()
1536 		reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0);  in exynos850_usbdrd_utmi_init()
1590 	return 0;  in exynos850_usbdrd_phy_init()
1628 	return 0;  in exynos850_usbdrd_phy_exit()
1709 		return 0;  in exynos5_usbdrd_gs101_phy_exit()
1732 	for (int i = 0; i < phy_drd->drv_data->n_clks; ++i)  in exynos5_usbdrd_phy_clk_handle()
1748 	for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i)  in exynos5_usbdrd_phy_clk_handle()
1759 		for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) {  in exynos5_usbdrd_phy_clk_handle()
1777 	return 0;  in exynos5_usbdrd_phy_clk_handle()
1828 	return 0;  in exynos5_usbdrd_orien_sw_set()
1843 		return 0;  in exynos5_usbdrd_setup_notifiers()
1866 	return 0;  in exynos5_usbdrd_setup_notifiers()
1911 			      FIELD_PREP_CONST(PHYPARAM0_TXPREEMPAMPTUNE, 0) |
1912 			      FIELD_PREP_CONST(PHYPARAM0_TXHSXVTUNE, 0) |
1948 	.n_core_clks		= 0,
1950 	.n_regulators		= 0,
2086 	PHY_TUNING_ENTRY_PMA(0x0c8c, -1, 0xff),
2087 	PHY_TUNING_ENTRY_PMA(0x1c8c, -1, 0xff),
2088 	PHY_TUNING_ENTRY_PMA(0x0c9c, -1, 0x7d),
2089 	PHY_TUNING_ENTRY_PMA(0x1c9c, -1, 0x7d),
2091 	PHY_TUNING_ENTRY_PMA(0x0e7c, -1, 0x06),
2092 	PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00),
2093 	PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36),
2094 	PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06),
2095 	PHY_TUNING_ENTRY_PMA(0x19e0, -1, 0x00),
2096 	PHY_TUNING_ENTRY_PMA(0x19e4, -1, 0x36),
2098 	PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x02),
2099 	PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x0b),
2101 	PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30),
2102 	PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30),
2104 	PHY_TUNING_ENTRY_PMA(0x0a08, -1, 0x0c),
2105 	PHY_TUNING_ENTRY_PMA(0x1a08, -1, 0x0c),
2107 	PHY_TUNING_ENTRY_PMA(0x0a0c, -1, 0x05),
2108 	PHY_TUNING_ENTRY_PMA(0x1a0c, -1, 0x05),
2110 	PHY_TUNING_ENTRY_PMA(0x00f8, -1, 0x1c),
2111 	PHY_TUNING_ENTRY_PMA(0x00fc, -1, 0x54),
2113 	PHY_TUNING_ENTRY_PMA(0x104c, -1, 0x07),
2114 	PHY_TUNING_ENTRY_PMA(0x204c, -1, 0x07),
2117 	PHY_TUNING_ENTRY_PMA(0x0ca8, -1, 0x00),
2118 	PHY_TUNING_ENTRY_PMA(0x0cac, -1, 0x04),
2119 	PHY_TUNING_ENTRY_PMA(0x1ca8, -1, 0x00),
2120 	PHY_TUNING_ENTRY_PMA(0x1cac, -1, 0x04),
2122 	PHY_TUNING_ENTRY_PMA(0x0cb8, -1, 0x00),
2123 	PHY_TUNING_ENTRY_PMA(0x0cbc, -1, 0x04),
2124 	PHY_TUNING_ENTRY_PMA(0x1cb8, -1, 0x00),
2125 	PHY_TUNING_ENTRY_PMA(0x1cbc, -1, 0x04),
2127 	PHY_TUNING_ENTRY_PMA(0x0bb0, 0x03, 0x01),
2128 	PHY_TUNING_ENTRY_PMA(0x0bb4, 0xf0, 0xa0),
2129 	PHY_TUNING_ENTRY_PMA(0x1bb0, 0x03, 0x01),
2130 	PHY_TUNING_ENTRY_PMA(0x1bb4, 0xf0, 0xa0),
2139 			     BACK_END_MODE_VEC_DISABLE_DATA_MASK, 0),
2164 	PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL, 0,
2173 		  * 19.6us(0x200) -> 15.3us(0x4)
2181 		 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_LEVEL, 0xb) |
2182 		 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT, 0))),
2186 		FIELD_PREP_CONST(LOCAL_COEF_PMA_CENTER_COEF, 0xb)),
2189 	/* set skp_remove_th 0x2 -> 0x7 for avoiding retry problem. */
2192 		FIELD_PREP_CONST(EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE, 0x7)),
2199 	PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_3, PCS_OUT_VEC_B2_SEL_OUT, 0),
2315 		phy_drd->reg_phy = devm_platform_ioremap_resource(pdev, 0);  in exynos5_usbdrd_phy_probe()
2321 	 * USB32DRD 4nm controller implements Synopsys eUSB2.0 PHY  in exynos5_usbdrd_phy_probe()
2347 	if (channel < 0)  in exynos5_usbdrd_phy_probe()
2371 	for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {  in exynos5_usbdrd_phy_probe()
2385 		case 0:  in exynos5_usbdrd_phy_probe()
2404 	return 0;  in exynos5_usbdrd_phy_probe()