Lines Matching full:ep
52 struct exynos_pcie_phy *ep = phy_get_drvdata(phy); in exynos5433_pcie_phy_init() local
54 regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, in exynos5433_pcie_phy_init()
56 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
58 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, in exynos5433_pcie_phy_init()
61 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET, in exynos5433_pcie_phy_init()
63 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET, in exynos5433_pcie_phy_init()
67 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
69 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init()
73 exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3)); in exynos5433_pcie_phy_init()
76 exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20)); in exynos5433_pcie_phy_init()
77 exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b)); in exynos5433_pcie_phy_init()
80 exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4)); in exynos5433_pcie_phy_init()
81 exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7)); in exynos5433_pcie_phy_init()
82 exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21)); in exynos5433_pcie_phy_init()
83 exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14)); in exynos5433_pcie_phy_init()
84 exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15)); in exynos5433_pcie_phy_init()
85 exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36)); in exynos5433_pcie_phy_init()
88 exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D)); in exynos5433_pcie_phy_init()
91 exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8)); in exynos5433_pcie_phy_init()
92 exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9)); in exynos5433_pcie_phy_init()
93 exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA)); in exynos5433_pcie_phy_init()
94 exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC)); in exynos5433_pcie_phy_init()
95 exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF)); in exynos5433_pcie_phy_init()
96 exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16)); in exynos5433_pcie_phy_init()
97 exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17)); in exynos5433_pcie_phy_init()
98 exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A)); in exynos5433_pcie_phy_init()
99 exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23)); in exynos5433_pcie_phy_init()
100 exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24)); in exynos5433_pcie_phy_init()
102 exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26)); in exynos5433_pcie_phy_init()
103 exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7)); in exynos5433_pcie_phy_init()
104 exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43)); in exynos5433_pcie_phy_init()
105 exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44)); in exynos5433_pcie_phy_init()
106 exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45)); in exynos5433_pcie_phy_init()
107 exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48)); in exynos5433_pcie_phy_init()
108 exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54)); in exynos5433_pcie_phy_init()
109 exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31)); in exynos5433_pcie_phy_init()
110 exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32)); in exynos5433_pcie_phy_init()
112 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET, in exynos5433_pcie_phy_init()
114 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET, in exynos5433_pcie_phy_init()
121 struct exynos_pcie_phy *ep = phy_get_drvdata(phy); in exynos5433_pcie_phy_exit() local
123 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, in exynos5433_pcie_phy_exit()
125 regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, in exynos5433_pcie_phy_exit()