Lines Matching +full:- +full:30
1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
8 #include <dt-bindings/phy/phy.h>
73 * The selection between the 400-based or 200-based values for REG_400M
337 {6500, 32, 117, 31, 28, 30, 56, 27, 24, 44, 37},
338 {6490, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
339 {6480, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
340 {6470, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
341 {6460, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
342 {6450, 32, 115, 31, 28, 30, 56, 27, 24, 44, 37},
343 {6440, 32, 115, 31, 28, 30, 56, 27, 24, 44, 37},
344 {6430, 31, 116, 31, 28, 30, 55, 27, 24, 44, 37},
345 {6420, 31, 116, 31, 28, 30, 55, 27, 24, 44, 37},
346 {6410, 31, 116, 31, 27, 30, 55, 27, 24, 44, 37},
347 {6400, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36},
348 {6390, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36},
349 {6380, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36},
350 {6370, 31, 115, 30, 27, 30, 55, 26, 23, 43, 36},
351 {6360, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
352 {6350, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
353 {6340, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
354 {6330, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
355 {6320, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36},
356 {6310, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36},
357 {6300, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36},
358 {6290, 31, 113, 30, 27, 29, 54, 26, 23, 43, 36},
359 {6280, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36},
360 {6270, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36},
361 {6260, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36},
362 {6250, 31, 112, 30, 27, 29, 54, 26, 23, 42, 36},
363 {6240, 30, 113, 30, 27, 29, 54, 26, 23, 42, 36},
364 {6230, 30, 112, 30, 27, 29, 54, 26, 23, 42, 35},
365 {6220, 30, 112, 30, 27, 29, 53, 26, 23, 42, 35},
366 {6210, 30, 112, 30, 27, 29, 53, 26, 23, 42, 35},
367 {6200, 30, 112, 29, 27, 29, 53, 26, 23, 42, 35},
368 {6190, 30, 111, 29, 27, 29, 53, 26, 23, 42, 35},
369 {6180, 30, 111, 29, 27, 29, 53, 26, 23, 42, 35},
370 {6170, 30, 111, 29, 26, 29, 53, 26, 23, 42, 35},
371 {6160, 30, 111, 29, 26, 29, 53, 26, 23, 42, 35},
372 {6150, 30, 110, 29, 26, 29, 53, 26, 23, 42, 35},
373 {6140, 30, 110, 29, 26, 29, 52, 26, 23, 42, 35},
374 {6130, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35},
375 {6120, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35},
376 {6110, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35},
377 {6100, 30, 109, 29, 26, 29, 52, 25, 22, 41, 35},
378 {6090, 30, 109, 29, 26, 29, 52, 25, 22, 41, 35},
379 {6080, 30, 109, 29, 26, 28, 53, 25, 22, 41, 35},
380 {6070, 30, 109, 29, 26, 28, 52, 25, 22, 41, 34},
381 {6060, 30, 108, 29, 26, 28, 52, 25, 22, 41, 34},
382 {6050, 30, 108, 29, 26, 28, 52, 25, 22, 41, 34},
447 {5400, 26, 97, 25, 23, 25, 46, 22, 20, 37, 30},
448 {5390, 26, 97, 25, 23, 25, 46, 22, 20, 37, 30},
449 {5380, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
450 {5370, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
451 {5360, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
452 {5350, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
453 {5340, 26, 95, 25, 23, 25, 45, 22, 20, 36, 30},
454 {5330, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
455 {5320, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
456 {5310, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
457 {5300, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
458 {5290, 26, 94, 25, 23, 25, 45, 22, 19, 36, 30},
459 {5280, 26, 94, 25, 23, 25, 45, 22, 19, 36, 30},
460 {5270, 26, 94, 25, 23, 25, 44, 22, 19, 36, 30},
461 {5260, 26, 94, 25, 23, 25, 44, 22, 19, 36, 30},
462 {5250, 25, 94, 25, 23, 24, 45, 22, 19, 36, 30},
537 {4500, 22, 80, 21, 19, 21, 38, 19, 16, 30, 25},
538 {4490, 22, 80, 21, 19, 21, 38, 18, 16, 30, 25},
539 {4480, 22, 79, 21, 19, 21, 38, 18, 16, 30, 25},
540 {4470, 22, 79, 21, 19, 21, 37, 18, 16, 30, 25},
541 {4460, 22, 79, 21, 19, 21, 37, 18, 16, 30, 25},
542 {4450, 21, 80, 21, 19, 21, 37, 18, 16, 30, 25},
543 {4440, 21, 79, 21, 19, 21, 37, 18, 16, 30, 25},
544 {4430, 21, 79, 21, 19, 21, 37, 18, 16, 30, 25},
545 {4420, 21, 79, 21, 19, 21, 37, 18, 16, 30, 25},
546 {4410, 21, 79, 21, 19, 20, 38, 18, 16, 30, 25},
547 {4400, 21, 78, 20, 19, 20, 37, 18, 16, 30, 24},
548 {4390, 21, 78, 20, 19, 20, 37, 18, 16, 30, 24},
549 {4380, 21, 78, 20, 19, 20, 37, 18, 16, 30, 24},
550 {4370, 21, 78, 20, 19, 20, 37, 18, 16, 30, 24},
620 {3670, 18, 64, 17, 16, 17, 30, 15, 13, 25, 20},
621 {3660, 17, 65, 17, 16, 17, 30, 15, 13, 25, 20},
622 {3650, 17, 65, 17, 16, 17, 30, 15, 13, 25, 20},
623 {3640, 17, 65, 17, 16, 17, 30, 15, 13, 25, 20},
624 {3630, 17, 64, 17, 16, 17, 30, 15, 13, 24, 20},
625 {3620, 17, 64, 17, 16, 17, 30, 15, 13, 24, 20},
626 {3610, 17, 64, 17, 16, 17, 30, 15, 13, 24, 20},
629 {3580, 17, 63, 16, 15, 16, 30, 15, 13, 24, 20},
630 {3570, 17, 63, 16, 15, 16, 30, 15, 13, 24, 19},
631 {3560, 17, 63, 16, 15, 16, 30, 14, 13, 24, 19},
632 {3550, 17, 62, 16, 15, 16, 30, 14, 13, 24, 19},
633 {3540, 17, 62, 16, 15, 16, 30, 14, 13, 24, 19},
807 {1800, 8, 30, 7, 8, 8, 14, 7, 6, 12, 9},
808 {1790, 8, 30, 7, 8, 8, 13, 7, 6, 12, 9},
809 {1780, 8, 30, 7, 8, 8, 13, 7, 6, 12, 9},
810 {1770, 8, 30, 7, 8, 8, 13, 7, 6, 12, 9},
884 {1030, 41, 16, 4, 61, 41, 6, 54, 30, 6, 51},
885 {1020, 40, 16, 4, 61, 41, 6, 54, 30, 6, 51},
886 {1010, 40, 16, 4, 60, 40, 6, 53, 30, 6, 50},
909 { 780, 30, 12, 2, 52, 31, 4, 46, 23, 4, 39},
910 { 770, 30, 11, 2, 52, 31, 4, 45, 23, 4, 39},
911 { 760, 30, 11, 2, 52, 31, 3, 45, 22, 4, 38},
912 { 750, 29, 11, 2, 51, 30, 3, 45, 22, 4, 38},
913 { 740, 29, 11, 2, 51, 30, 3, 44, 22, 4, 37},
915 { 720, 28, 10, 2, 50, 30, 3, 44, 22, 4, 36},
916 { 710, 28, 10, 2, 50, 30, 3, 43, 22, 4, 36},
927 { 600, 23, 8, 1, 46, 26, 2, 39, 18, 3, 30},
928 { 590, 23, 8, 1, 46, 24, 2, 39, 17, 3, 30},
954 { 330, 12, 3, 0, 37, 14, 0, 30, 9, 1, 17},
955 { 320, 12, 3, 0, 37, 14, 0, 30, 9, 1, 17},
956 { 310, 12, 3, 0, 36, 13, 0, 30, 9, 1, 16},
974 { 130, 4, 0, 0, 30, 6, 0, 23, 3, 0, 8},
975 { 120, 4, 0, 0, 30, 6, 0, 23, 3, 0, 7},
976 { 110, 3, 0, 0, 30, 6, 0, 23, 3, 0, 7},
984 regmap_write(samsung->regmap, BIAS_CON0, I_DEV_DIV_6 | I_RES_100_2UA); in samsung_mipi_dcphy_bias_block_enable()
985 regmap_write(samsung->regmap, BIAS_CON1, I_VBG_SEL_820MV | I_BGR_VREF_820MV | in samsung_mipi_dcphy_bias_block_enable()
987 regmap_write(samsung->regmap, BIAS_CON2, REG_325M_325MV | REG_LP_400M_400MV | in samsung_mipi_dcphy_bias_block_enable()
994 regmap_update_bits(samsung->regmap, BIAS_CON4, in samsung_mipi_dcphy_bias_block_enable()
1000 regmap_write(samsung->regmap, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000)); in samsung_mipi_dphy_lane_enable()
1001 regmap_update_bits(samsung->regmap, DPHY_MC_GNR_CON0, in samsung_mipi_dphy_lane_enable()
1004 switch (samsung->lanes) { in samsung_mipi_dphy_lane_enable()
1006 regmap_write(samsung->regmap, DPHY_MD3_GNR_CON1, in samsung_mipi_dphy_lane_enable()
1008 regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0, in samsung_mipi_dphy_lane_enable()
1012 regmap_write(samsung->regmap, COMBO_MD2_GNR_CON1, in samsung_mipi_dphy_lane_enable()
1014 regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0, in samsung_mipi_dphy_lane_enable()
1018 regmap_write(samsung->regmap, COMBO_MD1_GNR_CON1, in samsung_mipi_dphy_lane_enable()
1020 regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0, in samsung_mipi_dphy_lane_enable()
1025 regmap_write(samsung->regmap, COMBO_MD0_GNR_CON1, in samsung_mipi_dphy_lane_enable()
1027 regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0, in samsung_mipi_dphy_lane_enable()
1035 switch (samsung->lanes) { in samsung_mipi_dphy_lane_disable()
1037 regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0, in samsung_mipi_dphy_lane_disable()
1041 regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0, in samsung_mipi_dphy_lane_disable()
1045 regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0, in samsung_mipi_dphy_lane_disable()
1050 regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0, in samsung_mipi_dphy_lane_disable()
1055 regmap_update_bits(samsung->regmap, DPHY_MC_GNR_CON0, PHY_ENABLE, 0); in samsung_mipi_dphy_lane_disable()
1060 regmap_update_bits(samsung->regmap, PLL_CON0, S_MASK | P_MASK, in samsung_mipi_dcphy_pll_configure()
1061 S(samsung->pll.scaler) | P(samsung->pll.prediv)); in samsung_mipi_dcphy_pll_configure()
1063 if (samsung->pll.dsm < 0) { in samsung_mipi_dcphy_pll_configure()
1067 dsm_tmp = abs(samsung->pll.dsm); in samsung_mipi_dcphy_pll_configure()
1068 dsm_tmp = dsm_tmp - 1; in samsung_mipi_dcphy_pll_configure()
1070 regmap_write(samsung->regmap, PLL_CON1, dsm_tmp); in samsung_mipi_dcphy_pll_configure()
1072 regmap_write(samsung->regmap, PLL_CON1, samsung->pll.dsm); in samsung_mipi_dcphy_pll_configure()
1075 regmap_update_bits(samsung->regmap, PLL_CON2, in samsung_mipi_dcphy_pll_configure()
1076 M_MASK, M(samsung->pll.fbdiv)); in samsung_mipi_dcphy_pll_configure()
1078 if (samsung->pll.ssc_en) { in samsung_mipi_dcphy_pll_configure()
1079 regmap_write(samsung->regmap, PLL_CON3, in samsung_mipi_dcphy_pll_configure()
1080 MRR(samsung->pll.mrr) | MFR(samsung->pll.mfr)); in samsung_mipi_dcphy_pll_configure()
1081 regmap_update_bits(samsung->regmap, PLL_CON4, SSCG_EN, SSCG_EN); in samsung_mipi_dcphy_pll_configure()
1084 regmap_write(samsung->regmap, PLL_CON5, RESET_N_SEL | PLL_ENABLE_SEL); in samsung_mipi_dcphy_pll_configure()
1085 regmap_write(samsung->regmap, PLL_CON7, PLL_LOCK_CNT(0xf000)); in samsung_mipi_dcphy_pll_configure()
1086 regmap_write(samsung->regmap, PLL_CON8, PLL_STB_CNT(0xf000)); in samsung_mipi_dcphy_pll_configure()
1094 regmap_update_bits(samsung->regmap, PLL_CON0, PLL_EN, PLL_EN); in samsung_mipi_dcphy_pll_enable()
1096 ret = regmap_read_poll_timeout(samsung->regmap, PLL_STAT0, in samsung_mipi_dcphy_pll_enable()
1099 dev_err(samsung->dev, "DC-PHY pll failed to lock\n"); in samsung_mipi_dcphy_pll_enable()
1106 regmap_update_bits(samsung->regmap, PLL_CON0, PLL_EN, 0); in samsung_mipi_dcphy_pll_disable()
1114 unsigned int lane_mbps = div64_ul(samsung->pll.rate, USEC_PER_SEC); in samsung_mipi_dphy_get_timing()
1120 for (i = num_timings; i > 1; i--) in samsung_mipi_dphy_get_timing()
1121 if (lane_mbps <= timings[i - 1].max_lane_mbps) in samsung_mipi_dphy_get_timing()
1124 return &timings[i - 1]; in samsung_mipi_dphy_get_timing()
1132 u32 max_fout = samsung->pdata->dphy_tx_max_lane_kbps; in samsung_mipi_dcphy_pll_round_rate()
1143 dev_err(samsung->dev, "parent rate of PLL can not be zero\n"); in samsung_mipi_dcphy_pll_round_rate()
1169 /* 6MHz ≤ Fref(Fin / p) ≤ 30MHz */ in samsung_mipi_dcphy_pll_round_rate()
1170 min_prediv = DIV_ROUND_UP_ULL(fin, 30 * MSEC_PER_SEC); in samsung_mipi_dcphy_pll_round_rate()
1182 /* -32767 ≤ K[15:0] ≤ 32767 */ in samsung_mipi_dcphy_pll_round_rate()
1183 _dsm = ((_prediv * fvco) - (2 * _fbdiv * fin)); in samsung_mipi_dcphy_pll_round_rate()
1191 delta = abs(fvco * MSEC_PER_SEC - tmp); in samsung_mipi_dcphy_pll_round_rate()
1210 dev_dbg(samsung->dev, "p: %d, m: %d, dsm:%ld, scaler: %d\n", in samsung_mipi_dcphy_pll_round_rate()
1220 unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC); in samsung_mipi_dphy_clk_lane_timing_init()
1224 regmap_write(samsung->regmap, DPHY_MC_GNR_CON0, 0xf000); in samsung_mipi_dphy_clk_lane_timing_init()
1227 * The Drive-Strength / Voltage-Amplitude is adjusted by setting in samsung_mipi_dphy_clk_lane_timing_init()
1228 * the Driver-Up Resistor and Driver-Down Resistor. in samsung_mipi_dphy_clk_lane_timing_init()
1230 res_up = samsung->pdata->dphy_hs_drv_res_cfg->clk_hs_drv_up_ohm; in samsung_mipi_dphy_clk_lane_timing_init()
1231 res_down = samsung->pdata->dphy_hs_drv_res_cfg->clk_hs_drv_down_ohm; in samsung_mipi_dphy_clk_lane_timing_init()
1234 regmap_write(samsung->regmap, DPHY_MC_ANA_CON0, val); in samsung_mipi_dphy_clk_lane_timing_init()
1237 regmap_write(samsung->regmap, DPHY_MC_ANA_CON1, 0x0001); in samsung_mipi_dphy_clk_lane_timing_init()
1241 * Divide-by-2 Clock from Serial Clock. Use this when data rate is under in samsung_mipi_dphy_clk_lane_timing_init()
1242 * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock in samsung_mipi_dphy_clk_lane_timing_init()
1247 val |= T_LPX(timing->lpx); in samsung_mipi_dphy_clk_lane_timing_init()
1249 regmap_write(samsung->regmap, DPHY_MC_TIME_CON0, val); in samsung_mipi_dphy_clk_lane_timing_init()
1251 val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare); in samsung_mipi_dphy_clk_lane_timing_init()
1252 regmap_write(samsung->regmap, DPHY_MC_TIME_CON1, val); in samsung_mipi_dphy_clk_lane_timing_init()
1254 val = T_HS_EXIT(timing->hs_exit) | T_CLK_TRAIL(timing->clk_trail_eot); in samsung_mipi_dphy_clk_lane_timing_init()
1255 regmap_write(samsung->regmap, DPHY_MC_TIME_CON2, val); in samsung_mipi_dphy_clk_lane_timing_init()
1257 val = T_CLK_POST(timing->clk_post); in samsung_mipi_dphy_clk_lane_timing_init()
1258 regmap_write(samsung->regmap, DPHY_MC_TIME_CON3, val); in samsung_mipi_dphy_clk_lane_timing_init()
1261 regmap_write(samsung->regmap, DPHY_MC_TIME_CON4, 0x1f4); in samsung_mipi_dphy_clk_lane_timing_init()
1268 regmap_write(samsung->regmap, DPHY_MC_DESKEW_CON0, 0x9cb1); in samsung_mipi_dphy_clk_lane_timing_init()
1275 unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC); in samsung_mipi_dphy_data_lane_timing_init()
1281 * The Drive-Strength / Voltage-Amplitude is adjusted by adjusting the in samsung_mipi_dphy_data_lane_timing_init()
1282 * Driver-Up Resistor and Driver-Down Resistor. in samsung_mipi_dphy_data_lane_timing_init()
1284 res_up = samsung->pdata->dphy_hs_drv_res_cfg->data_hs_drv_up_ohm; in samsung_mipi_dphy_data_lane_timing_init()
1285 res_down = samsung->pdata->dphy_hs_drv_res_cfg->data_hs_drv_down_ohm; in samsung_mipi_dphy_data_lane_timing_init()
1288 regmap_write(samsung->regmap, COMBO_MD0_ANA_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1289 regmap_write(samsung->regmap, COMBO_MD1_ANA_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1290 regmap_write(samsung->regmap, COMBO_MD2_ANA_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1291 regmap_write(samsung->regmap, DPHY_MD3_ANA_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1294 regmap_write(samsung->regmap, COMBO_MD0_ANA_CON1, 0x0001); in samsung_mipi_dphy_data_lane_timing_init()
1295 regmap_write(samsung->regmap, COMBO_MD1_ANA_CON1, 0x0001); in samsung_mipi_dphy_data_lane_timing_init()
1296 regmap_write(samsung->regmap, COMBO_MD2_ANA_CON1, 0x0001); in samsung_mipi_dphy_data_lane_timing_init()
1297 regmap_write(samsung->regmap, DPHY_MD3_ANA_CON1, 0x0001); in samsung_mipi_dphy_data_lane_timing_init()
1302 * Divide-by-2 Clock from Serial Clock. Use this when data rate is under in samsung_mipi_dphy_data_lane_timing_init()
1303 * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock in samsung_mipi_dphy_data_lane_timing_init()
1308 val |= T_LPX(timing->lpx); in samsung_mipi_dphy_data_lane_timing_init()
1310 regmap_write(samsung->regmap, COMBO_MD0_TIME_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1311 regmap_write(samsung->regmap, COMBO_MD1_TIME_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1312 regmap_write(samsung->regmap, COMBO_MD2_TIME_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1313 regmap_write(samsung->regmap, DPHY_MD3_TIME_CON0, val); in samsung_mipi_dphy_data_lane_timing_init()
1315 val = T_HS_ZERO(timing->hs_zero) | T_HS_PREPARE(timing->hs_prepare); in samsung_mipi_dphy_data_lane_timing_init()
1316 regmap_write(samsung->regmap, COMBO_MD0_TIME_CON1, val); in samsung_mipi_dphy_data_lane_timing_init()
1317 regmap_write(samsung->regmap, COMBO_MD1_TIME_CON1, val); in samsung_mipi_dphy_data_lane_timing_init()
1318 regmap_write(samsung->regmap, COMBO_MD2_TIME_CON1, val); in samsung_mipi_dphy_data_lane_timing_init()
1319 regmap_write(samsung->regmap, DPHY_MD3_TIME_CON1, val); in samsung_mipi_dphy_data_lane_timing_init()
1321 val = T_HS_EXIT(timing->hs_exit) | T_HS_TRAIL(timing->hs_trail_eot); in samsung_mipi_dphy_data_lane_timing_init()
1322 regmap_write(samsung->regmap, COMBO_MD0_TIME_CON2, val); in samsung_mipi_dphy_data_lane_timing_init()
1323 regmap_write(samsung->regmap, COMBO_MD1_TIME_CON2, val); in samsung_mipi_dphy_data_lane_timing_init()
1324 regmap_write(samsung->regmap, COMBO_MD2_TIME_CON2, val); in samsung_mipi_dphy_data_lane_timing_init()
1325 regmap_write(samsung->regmap, DPHY_MD3_TIME_CON2, val); in samsung_mipi_dphy_data_lane_timing_init()
1327 /* TTA-GET/TTA-GO Timing Counter register use default value */ in samsung_mipi_dphy_data_lane_timing_init()
1329 regmap_write(samsung->regmap, COMBO_MD0_TIME_CON3, val); in samsung_mipi_dphy_data_lane_timing_init()
1330 regmap_write(samsung->regmap, COMBO_MD1_TIME_CON3, val); in samsung_mipi_dphy_data_lane_timing_init()
1331 regmap_write(samsung->regmap, COMBO_MD2_TIME_CON3, val); in samsung_mipi_dphy_data_lane_timing_init()
1332 regmap_write(samsung->regmap, DPHY_MD3_TIME_CON3, val); in samsung_mipi_dphy_data_lane_timing_init()
1335 regmap_write(samsung->regmap, COMBO_MD0_TIME_CON4, 0x1f4); in samsung_mipi_dphy_data_lane_timing_init()
1336 regmap_write(samsung->regmap, COMBO_MD1_TIME_CON4, 0x1f4); in samsung_mipi_dphy_data_lane_timing_init()
1337 regmap_write(samsung->regmap, COMBO_MD2_TIME_CON4, 0x1f4); in samsung_mipi_dphy_data_lane_timing_init()
1338 regmap_write(samsung->regmap, DPHY_MD3_TIME_CON4, 0x1f4); in samsung_mipi_dphy_data_lane_timing_init()
1345 reset_control_assert(samsung->m_phy_rst); in samsung_mipi_dphy_power_on()
1357 reset_control_deassert(samsung->m_phy_rst); in samsung_mipi_dphy_power_on()
1371 reset_control_assert(samsung->apb_rst); in samsung_mipi_dcphy_power_on()
1373 reset_control_deassert(samsung->apb_rst); in samsung_mipi_dcphy_power_on()
1375 switch (samsung->type) { in samsung_mipi_dcphy_power_on()
1380 return -EOPNOTSUPP; in samsung_mipi_dcphy_power_on()
1390 switch (samsung->type) { in samsung_mipi_dcphy_power_off()
1396 return -EOPNOTSUPP; in samsung_mipi_dcphy_power_off()
1408 unsigned long fin = div64_ul(clk_get_rate(samsung->ref_clk), MSEC_PER_SEC); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1409 u16 prediv = samsung->pll.prediv; in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1410 u16 fbdiv = samsung->pll.fbdiv; in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1442 dev_err(samsung->dev, "failed to calc ssc parameter mfr and mrr\n"); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1443 return -EINVAL; in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1453 unsigned long prate = clk_get_rate(samsung->ref_clk); in samsung_mipi_dcphy_pll_calc_rate()
1465 dev_dbg(samsung->dev, "%s: fin=%lu, req_rate=%llu\n", in samsung_mipi_dcphy_pll_calc_rate()
1467 dev_dbg(samsung->dev, "%s: fout=%lu, prediv=%u, fbdiv=%u\n", in samsung_mipi_dcphy_pll_calc_rate()
1470 samsung->pll.prediv = prediv; in samsung_mipi_dcphy_pll_calc_rate()
1471 samsung->pll.fbdiv = fbdiv; in samsung_mipi_dcphy_pll_calc_rate()
1472 samsung->pll.dsm = dsm; in samsung_mipi_dcphy_pll_calc_rate()
1473 samsung->pll.scaler = scaler; in samsung_mipi_dcphy_pll_calc_rate()
1474 samsung->pll.rate = fout; in samsung_mipi_dcphy_pll_calc_rate()
1484 samsung->pll.ssc_en = true; in samsung_mipi_dcphy_pll_calc_rate()
1485 samsung->pll.mfr = mfr; in samsung_mipi_dcphy_pll_calc_rate()
1486 samsung->pll.mrr = mrr; in samsung_mipi_dcphy_pll_calc_rate()
1495 unsigned long long target_rate = opts->mipi_dphy.hs_clk_rate; in samsung_mipi_dcphy_configure()
1497 samsung->lanes = opts->mipi_dphy.lanes > 4 ? 4 : opts->mipi_dphy.lanes; in samsung_mipi_dcphy_configure()
1500 opts->mipi_dphy.hs_clk_rate = samsung->pll.rate; in samsung_mipi_dcphy_configure()
1509 return pm_runtime_resume_and_get(samsung->dev); in samsung_mipi_dcphy_init()
1516 return pm_runtime_put(samsung->dev); in samsung_mipi_dcphy_exit()
1541 if (args->args_count != 1) { in samsung_mipi_dcphy_xlate()
1543 return ERR_PTR(-EINVAL); in samsung_mipi_dcphy_xlate()
1546 if (samsung->type != PHY_NONE && samsung->type != args->args[0]) in samsung_mipi_dcphy_xlate()
1548 args->args[0], samsung->type); in samsung_mipi_dcphy_xlate()
1550 samsung->type = args->args[0]; in samsung_mipi_dcphy_xlate()
1552 return samsung->phy; in samsung_mipi_dcphy_xlate()
1557 struct device *dev = &pdev->dev; in samsung_mipi_dcphy_probe()
1558 struct device_node *np = dev->of_node; in samsung_mipi_dcphy_probe()
1567 return -ENOMEM; in samsung_mipi_dcphy_probe()
1569 samsung->dev = dev; in samsung_mipi_dcphy_probe()
1570 samsung->pdata = device_get_match_data(dev); in samsung_mipi_dcphy_probe()
1578 samsung->regmap = devm_regmap_init_mmio(dev, regs, in samsung_mipi_dcphy_probe()
1580 if (IS_ERR(samsung->regmap)) in samsung_mipi_dcphy_probe()
1581 return dev_err_probe(dev, PTR_ERR(samsung->regmap), "Failed to init regmap\n"); in samsung_mipi_dcphy_probe()
1583 samsung->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in samsung_mipi_dcphy_probe()
1584 if (IS_ERR(samsung->grf_regmap)) in samsung_mipi_dcphy_probe()
1585 return dev_err_probe(dev, PTR_ERR(samsung->grf_regmap), in samsung_mipi_dcphy_probe()
1588 samsung->ref_clk = devm_clk_get(dev, "ref"); in samsung_mipi_dcphy_probe()
1589 if (IS_ERR(samsung->ref_clk)) in samsung_mipi_dcphy_probe()
1590 return dev_err_probe(dev, PTR_ERR(samsung->ref_clk), in samsung_mipi_dcphy_probe()
1593 samsung->pclk = devm_clk_get(dev, "pclk"); in samsung_mipi_dcphy_probe()
1594 if (IS_ERR(samsung->pclk)) in samsung_mipi_dcphy_probe()
1595 return dev_err_probe(dev, PTR_ERR(samsung->pclk), "Failed to get pclk\n"); in samsung_mipi_dcphy_probe()
1597 samsung->m_phy_rst = devm_reset_control_get(dev, "m_phy"); in samsung_mipi_dcphy_probe()
1598 if (IS_ERR(samsung->m_phy_rst)) in samsung_mipi_dcphy_probe()
1599 return dev_err_probe(dev, PTR_ERR(samsung->m_phy_rst), in samsung_mipi_dcphy_probe()
1602 samsung->s_phy_rst = devm_reset_control_get(dev, "s_phy"); in samsung_mipi_dcphy_probe()
1603 if (IS_ERR(samsung->s_phy_rst)) in samsung_mipi_dcphy_probe()
1604 return dev_err_probe(dev, PTR_ERR(samsung->s_phy_rst), in samsung_mipi_dcphy_probe()
1607 samsung->apb_rst = devm_reset_control_get(dev, "apb"); in samsung_mipi_dcphy_probe()
1608 if (IS_ERR(samsung->apb_rst)) in samsung_mipi_dcphy_probe()
1609 return dev_err_probe(dev, PTR_ERR(samsung->apb_rst), in samsung_mipi_dcphy_probe()
1612 samsung->grf_apb_rst = devm_reset_control_get(dev, "grf"); in samsung_mipi_dcphy_probe()
1613 if (IS_ERR(samsung->grf_apb_rst)) in samsung_mipi_dcphy_probe()
1614 return dev_err_probe(dev, PTR_ERR(samsung->grf_apb_rst), in samsung_mipi_dcphy_probe()
1617 samsung->phy = devm_phy_create(dev, NULL, &samsung_mipi_dcphy_ops); in samsung_mipi_dcphy_probe()
1618 if (IS_ERR(samsung->phy)) in samsung_mipi_dcphy_probe()
1619 return dev_err_probe(dev, PTR_ERR(samsung->phy), "Failed to create MIPI DC-PHY\n"); in samsung_mipi_dcphy_probe()
1621 phy_set_drvdata(samsung->phy, samsung); in samsung_mipi_dcphy_probe()
1639 clk_disable_unprepare(samsung->ref_clk); in samsung_mipi_dcphy_runtime_suspend()
1640 clk_disable_unprepare(samsung->pclk); in samsung_mipi_dcphy_runtime_suspend()
1650 ret = clk_prepare_enable(samsung->pclk); in samsung_mipi_dcphy_runtime_resume()
1652 dev_err(samsung->dev, "Failed to enable pclk, %d\n", ret); in samsung_mipi_dcphy_runtime_resume()
1656 ret = clk_prepare_enable(samsung->ref_clk); in samsung_mipi_dcphy_runtime_resume()
1658 dev_err(samsung->dev, "Failed to enable reference clock, %d\n", ret); in samsung_mipi_dcphy_runtime_resume()
1659 clk_disable_unprepare(samsung->pclk); in samsung_mipi_dcphy_runtime_resume()
1697 .compatible = "rockchip,rk3576-mipi-dcphy",
1700 .compatible = "rockchip,rk3588-mipi-dcphy",
1709 .name = "samsung-mipi-dcphy",
1717 MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");