1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
22  * The higher 16-bit of this register is used for write protection
80 					phys[inst->index]);  in to_pcie_phy()
88 	if (args->args_count == 0)  in rockchip_pcie_phy_of_xlate()
89 		return rk_phy->phys[0].phy;  in rockchip_pcie_phy_of_xlate()
91 	if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))  in rockchip_pcie_phy_of_xlate()
92 		return ERR_PTR(-ENODEV);  in rockchip_pcie_phy_of_xlate()
94 	return rk_phy->phys[args->args[0]].phy;  in rockchip_pcie_phy_of_xlate()
101 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,  in phy_wr_cfg()
109 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,  in phy_wr_cfg()
114 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,  in phy_wr_cfg()
126 	guard(mutex)(&rk_phy->pcie_mutex);  in rockchip_pcie_phy_power_off()
128 	regmap_write(rk_phy->reg_base,  in rockchip_pcie_phy_power_off()
129 		     rk_phy->phy_data->pcie_laneoff,  in rockchip_pcie_phy_power_off()
132 				   PHY_LANE_IDLE_A_SHIFT + inst->index));  in rockchip_pcie_phy_power_off()
134 	if (--rk_phy->pwr_cnt) {  in rockchip_pcie_phy_power_off()
138 	err = reset_control_assert(rk_phy->phy_rst);  in rockchip_pcie_phy_power_off()
140 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);  in rockchip_pcie_phy_power_off()
141 		rk_phy->pwr_cnt++;  in rockchip_pcie_phy_power_off()
142 		regmap_write(rk_phy->reg_base,  in rockchip_pcie_phy_power_off()
143 			     rk_phy->phy_data->pcie_laneoff,  in rockchip_pcie_phy_power_off()
146 					   PHY_LANE_IDLE_A_SHIFT + inst->index));  in rockchip_pcie_phy_power_off()
160 	guard(mutex)(&rk_phy->pcie_mutex);  in rockchip_pcie_phy_power_on()
162 	regmap_write(rk_phy->reg_base,  in rockchip_pcie_phy_power_on()
163 		     rk_phy->phy_data->pcie_laneoff,  in rockchip_pcie_phy_power_on()
166 				   PHY_LANE_IDLE_A_SHIFT + inst->index));  in rockchip_pcie_phy_power_on()
168 	if (rk_phy->pwr_cnt++) {  in rockchip_pcie_phy_power_on()
172 	err = reset_control_deassert(rk_phy->phy_rst);  in rockchip_pcie_phy_power_on()
174 		dev_err(&phy->dev, "deassert phy_rst err %d\n", err);  in rockchip_pcie_phy_power_on()
175 		rk_phy->pwr_cnt--;  in rockchip_pcie_phy_power_on()
179 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,  in rockchip_pcie_phy_power_on()
186 	 * so we make it large enough here. And we use loop-break  in rockchip_pcie_phy_power_on()
189 	err = regmap_read_poll_timeout(rk_phy->reg_base,  in rockchip_pcie_phy_power_on()
190 				       rk_phy->phy_data->pcie_status,  in rockchip_pcie_phy_power_on()
195 		dev_err(&phy->dev, "pll lock timeout!\n");  in rockchip_pcie_phy_power_on()
202 	err = regmap_read_poll_timeout(rk_phy->reg_base,  in rockchip_pcie_phy_power_on()
203 				       rk_phy->phy_data->pcie_status,  in rockchip_pcie_phy_power_on()
208 		dev_err(&phy->dev, "pll output enable timeout!\n");  in rockchip_pcie_phy_power_on()
212 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,  in rockchip_pcie_phy_power_on()
217 	err = regmap_read_poll_timeout(rk_phy->reg_base,  in rockchip_pcie_phy_power_on()
218 				       rk_phy->phy_data->pcie_status,  in rockchip_pcie_phy_power_on()
223 		dev_err(&phy->dev, "pll relock timeout!\n");  in rockchip_pcie_phy_power_on()
230 	reset_control_assert(rk_phy->phy_rst);  in rockchip_pcie_phy_power_on()
231 	rk_phy->pwr_cnt--;  in rockchip_pcie_phy_power_on()
241 	guard(mutex)(&rk_phy->pcie_mutex);  in rockchip_pcie_phy_init()
243 	if (rk_phy->init_cnt++) {  in rockchip_pcie_phy_init()
247 	err = reset_control_assert(rk_phy->phy_rst);  in rockchip_pcie_phy_init()
249 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);  in rockchip_pcie_phy_init()
250 		rk_phy->init_cnt--;  in rockchip_pcie_phy_init()
262 	guard(mutex)(&rk_phy->pcie_mutex);  in rockchip_pcie_phy_exit()
264 	if (--rk_phy->init_cnt)  in rockchip_pcie_phy_exit()
287 		.compatible = "rockchip,rk3399-pcie-phy",
297 	struct device *dev = &pdev->dev;  in rockchip_pcie_phy_probe()
300 	struct regmap *grf;  in rockchip_pcie_phy_probe()  local
304 	grf = syscon_node_to_regmap(dev->parent->of_node);  in rockchip_pcie_phy_probe()
305 	if (IS_ERR(grf)) {  in rockchip_pcie_phy_probe()
306 		dev_err(dev, "Cannot find GRF syscon\n");  in rockchip_pcie_phy_probe()
307 		return PTR_ERR(grf);  in rockchip_pcie_phy_probe()
312 		return -ENOMEM;  in rockchip_pcie_phy_probe()
314 	rk_phy->phy_data = device_get_match_data(&pdev->dev);  in rockchip_pcie_phy_probe()
315 	if (!rk_phy->phy_data)  in rockchip_pcie_phy_probe()
316 		return -EINVAL;  in rockchip_pcie_phy_probe()
318 	rk_phy->reg_base = grf;  in rockchip_pcie_phy_probe()
320 	mutex_init(&rk_phy->pcie_mutex);  in rockchip_pcie_phy_probe()
322 	rk_phy->phy_rst = devm_reset_control_get(dev, "phy");  in rockchip_pcie_phy_probe()
323 	if (IS_ERR(rk_phy->phy_rst))  in rockchip_pcie_phy_probe()
324 		return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst),  in rockchip_pcie_phy_probe()
327 	rk_phy->clk_pciephy_ref = devm_clk_get_enabled(dev, "refclk");  in rockchip_pcie_phy_probe()
328 	if (IS_ERR(rk_phy->clk_pciephy_ref))  in rockchip_pcie_phy_probe()
329 		return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->clk_pciephy_ref),  in rockchip_pcie_phy_probe()
332 	/* parse #phy-cells to see if it's legacy PHY model */  in rockchip_pcie_phy_probe()
333 	if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))  in rockchip_pcie_phy_probe()
334 		return -ENOENT;  in rockchip_pcie_phy_probe()
340 		rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);  in rockchip_pcie_phy_probe()
341 		if (IS_ERR(rk_phy->phys[i].phy)) {  in rockchip_pcie_phy_probe()
343 			return PTR_ERR(rk_phy->phys[i].phy);  in rockchip_pcie_phy_probe()
345 		rk_phy->phys[i].index = i;  in rockchip_pcie_phy_probe()
346 		phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);  in rockchip_pcie_phy_probe()
359 		.name	= "rockchip-pcie-phy",
366 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");