Lines Matching +full:spread +full:- +full:spectrum
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
221 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
223 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
231 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
232 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
233 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
235 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
240 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
243 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
244 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
246 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
247 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
255 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
259 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
261 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
265 switch (priv->type) { in rockchip_combphy_init()
271 if (priv->cfg->combphy_cfg) in rockchip_combphy_init()
272 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_init()
275 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_init()
276 ret = -EINVAL; in rockchip_combphy_init()
281 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); in rockchip_combphy_init()
285 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
289 if (priv->type == PHY_TYPE_USB3) { in rockchip_combphy_init()
292 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
295 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
301 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
310 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
311 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
326 if (args->args_count != 1) { in rockchip_combphy_xlate()
328 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
331 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
333 args->args[0], priv->type); in rockchip_combphy_xlate()
335 priv->type = args->args[0]; in rockchip_combphy_xlate()
337 return priv->phy; in rockchip_combphy_xlate()
344 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_combphy_parse_dt()
345 if (priv->num_clks < 1) in rockchip_combphy_parse_dt()
346 return -EINVAL; in rockchip_combphy_parse_dt()
348 priv->refclk = NULL; in rockchip_combphy_parse_dt()
349 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
350 if (!strncmp(priv->clks[i].id, "ref", 3)) { in rockchip_combphy_parse_dt()
351 priv->refclk = priv->clks[i].clk; in rockchip_combphy_parse_dt()
356 if (!priv->refclk) { in rockchip_combphy_parse_dt()
358 return -EINVAL; in rockchip_combphy_parse_dt()
361 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
362 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
363 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
364 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
367 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
368 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
369 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
370 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
373 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); in rockchip_combphy_parse_dt()
375 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); in rockchip_combphy_parse_dt()
377 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); in rockchip_combphy_parse_dt()
379 if (PTR_ERR(priv->phy_rst) == -ENOENT) in rockchip_combphy_parse_dt()
380 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); in rockchip_combphy_parse_dt()
381 if (IS_ERR(priv->phy_rst)) in rockchip_combphy_parse_dt()
382 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); in rockchip_combphy_parse_dt()
390 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
399 return -EINVAL; in rockchip_combphy_probe()
404 return -ENOMEM; in rockchip_combphy_probe()
406 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
407 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
408 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
412 /* find the phy-id from the io address */ in rockchip_combphy_probe()
413 priv->id = -ENODEV; in rockchip_combphy_probe()
414 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
415 if (res->start == phy_cfg->phy_ids[id]) { in rockchip_combphy_probe()
416 priv->id = id; in rockchip_combphy_probe()
421 priv->dev = dev; in rockchip_combphy_probe()
422 priv->type = PHY_NONE; in rockchip_combphy_probe()
423 priv->cfg = phy_cfg; in rockchip_combphy_probe()
429 ret = reset_control_assert(priv->phy_rst); in rockchip_combphy_probe()
435 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); in rockchip_combphy_probe()
436 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
438 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
442 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
451 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3528_combphy_cfg()
455 /* Set SSC downward spread spectrum */ in rk3528_combphy_cfg()
459 switch (priv->type) { in rk3528_combphy_cfg()
461 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3528_combphy_cfg()
462 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3528_combphy_cfg()
463 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3528_combphy_cfg()
464 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3528_combphy_cfg()
485 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3528_combphy_cfg()
486 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3528_combphy_cfg()
487 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3528_combphy_cfg()
488 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); in rk3528_combphy_cfg()
491 dev_err(priv->dev, "incompatible PHY type\n"); in rk3528_combphy_cfg()
492 return -EINVAL; in rk3528_combphy_cfg()
495 rate = clk_get_rate(priv->refclk); in rk3528_combphy_cfg()
499 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3528_combphy_cfg()
500 if (priv->type == PHY_TYPE_USB3) { in rk3528_combphy_cfg()
505 } else if (priv->type == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
512 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3528_combphy_cfg()
513 if (priv->type == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
524 writel(0x570804f0, priv->mmio + RK3528_PHYREG42); in rk3528_combphy_cfg()
528 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3528_combphy_cfg()
529 return -EINVAL; in rk3528_combphy_cfg()
532 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { in rk3528_combphy_cfg()
533 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3528_combphy_cfg()
535 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3528_combphy_cfg()
557 if (priv->type == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
558 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) in rk3528_combphy_cfg()
567 /* pipe-phy-grf */
584 /* pipe-grf */
599 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg()
603 switch (priv->type) { in rk3562_combphy_cfg()
605 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
609 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
610 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
611 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
612 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
615 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
629 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3562_combphy_cfg()
636 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3562_combphy_cfg()
639 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3562_combphy_cfg()
641 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
642 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
643 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
644 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
647 dev_err(priv->dev, "incompatible PHY type\n"); in rk3562_combphy_cfg()
648 return -EINVAL; in rk3562_combphy_cfg()
651 rate = clk_get_rate(priv->refclk); in rk3562_combphy_cfg()
655 if (priv->type == PHY_TYPE_USB3) { in rk3562_combphy_cfg()
662 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3562_combphy_cfg()
666 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3562_combphy_cfg()
669 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
670 if (priv->type == PHY_TYPE_PCIE) { in rk3562_combphy_cfg()
682 writel(0x4, priv->mmio + RK3568_PHYREG12); in rk3562_combphy_cfg()
688 writel(0x32, priv->mmio + RK3568_PHYREG18); in rk3562_combphy_cfg()
689 writel(0xf0, priv->mmio + RK3568_PHYREG11); in rk3562_combphy_cfg()
693 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3562_combphy_cfg()
694 return -EINVAL; in rk3562_combphy_cfg()
697 if (priv->ext_refclk) { in rk3562_combphy_cfg()
698 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3562_combphy_cfg()
699 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3562_combphy_cfg()
705 val = readl(priv->mmio + RK3568_PHYREG14); in rk3562_combphy_cfg()
707 writel(val, priv->mmio + RK3568_PHYREG14); in rk3562_combphy_cfg()
711 if (priv->enable_ssc) { in rk3562_combphy_cfg()
712 val = readl(priv->mmio + RK3568_PHYREG8); in rk3562_combphy_cfg()
714 writel(val, priv->mmio + RK3568_PHYREG8); in rk3562_combphy_cfg()
721 /* pipe-phy-grf */
754 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
758 switch (priv->type) { in rk3568_combphy_cfg()
760 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
765 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
766 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
767 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
768 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
772 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
777 val = readl(priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
779 writel(val, priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
786 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3568_combphy_cfg()
793 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3568_combphy_cfg()
794 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3568_combphy_cfg()
796 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
797 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
798 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
799 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
800 switch (priv->id) { in rk3568_combphy_cfg()
802 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); in rk3568_combphy_cfg()
805 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); in rk3568_combphy_cfg()
812 val = readl(priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
814 writel(val, priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
821 writel(val, priv->mmio + RK3568_PHYREG7); in rk3568_combphy_cfg()
823 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
824 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
825 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
826 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
827 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
831 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
832 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
833 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
834 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
838 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
839 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
840 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
841 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
842 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
846 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
847 return -EINVAL; in rk3568_combphy_cfg()
850 rate = clk_get_rate(priv->refclk); in rk3568_combphy_cfg()
854 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
860 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3568_combphy_cfg()
865 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
869 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
870 if (priv->type == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
877 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3568_combphy_cfg()
883 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3568_combphy_cfg()
884 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3568_combphy_cfg()
885 } else if (priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
886 /* downward spread spectrum +500ppm */ in rk3568_combphy_cfg()
896 dev_err(priv->dev, "unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
897 return -EINVAL; in rk3568_combphy_cfg()
900 if (priv->ext_refclk) { in rk3568_combphy_cfg()
901 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
902 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3568_combphy_cfg()
908 val = readl(priv->mmio + RK3568_PHYREG14); in rk3568_combphy_cfg()
910 writel(val, priv->mmio + RK3568_PHYREG14); in rk3568_combphy_cfg()
914 if (priv->enable_ssc) { in rk3568_combphy_cfg()
915 val = readl(priv->mmio + RK3568_PHYREG8); in rk3568_combphy_cfg()
917 writel(val, priv->mmio + RK3568_PHYREG8); in rk3568_combphy_cfg()
924 /* pipe-phy-grf */
951 /* pipe-grf */
971 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3576_combphy_cfg()
975 switch (priv->type) { in rk3576_combphy_cfg()
977 /* Set SSC downward spread spectrum */ in rk3576_combphy_cfg()
981 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3576_combphy_cfg()
982 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3576_combphy_cfg()
983 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3576_combphy_cfg()
984 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3576_combphy_cfg()
988 /* Set SSC downward spread spectrum */ in rk3576_combphy_cfg()
993 val = readl(priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
995 writel(val, priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1002 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1009 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3576_combphy_cfg()
1012 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1015 writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21); in rk3576_combphy_cfg()
1017 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3576_combphy_cfg()
1018 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3576_combphy_cfg()
1019 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3576_combphy_cfg()
1024 val = readl(priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1026 writel(val, priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1031 writel(val, priv->mmio + RK3568_PHYREG7); in rk3576_combphy_cfg()
1033 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3576_combphy_cfg()
1034 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3576_combphy_cfg()
1035 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3576_combphy_cfg()
1036 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3576_combphy_cfg()
1037 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3576_combphy_cfg()
1038 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3576_combphy_cfg()
1042 dev_err(priv->dev, "incompatible PHY type\n"); in rk3576_combphy_cfg()
1043 return -EINVAL; in rk3576_combphy_cfg()
1046 rate = clk_get_rate(priv->refclk); in rk3576_combphy_cfg()
1050 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3576_combphy_cfg()
1051 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
1058 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3576_combphy_cfg()
1059 } else if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
1067 writel(0x00, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1075 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1076 writel(0x02, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1077 writel(0x57, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1079 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3576_combphy_cfg()
1084 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3576_combphy_cfg()
1088 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3576_combphy_cfg()
1089 if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
1091 writel(0xc0, priv->mmio + RK3576_PHYREG30); in rk3576_combphy_cfg()
1100 writel(0x4c, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1110 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1111 writel(0x43, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1112 writel(0x88, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1113 writel(0x56, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1114 } else if (priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
1115 /* downward spread spectrum +500ppm */ in rk3576_combphy_cfg()
1131 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3576_combphy_cfg()
1132 return -EINVAL; in rk3576_combphy_cfg()
1135 if (priv->ext_refclk) { in rk3576_combphy_cfg()
1136 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3576_combphy_cfg()
1137 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3576_combphy_cfg()
1144 writel(0x0c, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1154 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1155 writel(0x43, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1156 writel(0x88, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1157 writel(0x56, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1161 if (priv->enable_ssc) { in rk3576_combphy_cfg()
1162 val = readl(priv->mmio + RK3568_PHYREG8); in rk3576_combphy_cfg()
1164 writel(val, priv->mmio + RK3568_PHYREG8); in rk3576_combphy_cfg()
1166 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { in rk3576_combphy_cfg()
1168 writel(0x00, priv->mmio + RK3576_PHYREG17); in rk3576_combphy_cfg()
1169 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3576_combphy_cfg()
1172 writel(0x00, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1181 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1182 writel(0x02, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1183 writel(0x08, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1184 writel(0x57, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1185 writel(0x40, priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1187 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3576_combphy_cfg()
1191 writel(val, priv->mmio + RK3568_PHYREG33); in rk3576_combphy_cfg()
1199 /* pipe-phy-grf */
1223 /* php-grf */
1240 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
1244 switch (priv->type) { in rk3588_combphy_cfg()
1246 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
1247 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
1248 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
1249 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
1250 switch (priv->id) { in rk3588_combphy_cfg()
1252 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); in rk3588_combphy_cfg()
1255 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); in rk3588_combphy_cfg()
1260 /* Set SSC downward spread spectrum */ in rk3588_combphy_cfg()
1265 val = readl(priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1267 writel(val, priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1274 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3588_combphy_cfg()
1281 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3588_combphy_cfg()
1282 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3588_combphy_cfg()
1284 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
1285 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
1286 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
1290 val = readl(priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1292 writel(val, priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1299 writel(val, priv->mmio + RK3568_PHYREG7); in rk3588_combphy_cfg()
1301 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
1302 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
1303 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
1304 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
1305 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
1306 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
1311 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
1312 return -EINVAL; in rk3588_combphy_cfg()
1315 rate = clk_get_rate(priv->refclk); in rk3588_combphy_cfg()
1319 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1325 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3588_combphy_cfg()
1330 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3588_combphy_cfg()
1333 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
1334 if (priv->type == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
1341 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3588_combphy_cfg()
1344 writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27); in rk3588_combphy_cfg()
1347 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3588_combphy_cfg()
1348 } else if (priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1349 /* downward spread spectrum +500ppm */ in rk3588_combphy_cfg()
1358 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3588_combphy_cfg()
1359 return -EINVAL; in rk3588_combphy_cfg()
1362 if (priv->ext_refclk) { in rk3588_combphy_cfg()
1363 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3588_combphy_cfg()
1364 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3588_combphy_cfg()
1370 val = readl(priv->mmio + RK3568_PHYREG14); in rk3588_combphy_cfg()
1372 writel(val, priv->mmio + RK3568_PHYREG14); in rk3588_combphy_cfg()
1376 if (priv->enable_ssc) { in rk3588_combphy_cfg()
1377 val = readl(priv->mmio + RK3568_PHYREG8); in rk3588_combphy_cfg()
1379 writel(val, priv->mmio + RK3568_PHYREG8); in rk3588_combphy_cfg()
1386 /* pipe-phy-grf */
1407 /* pipe-grf */
1427 .compatible = "rockchip,rk3528-naneng-combphy",
1431 .compatible = "rockchip,rk3562-naneng-combphy",
1435 .compatible = "rockchip,rk3568-naneng-combphy",
1439 .compatible = "rockchip,rk3576-naneng-combphy",
1443 .compatible = "rockchip,rk3588-naneng-combphy",
1453 .name = "rockchip-naneng-combphy",