Lines Matching +full:refclk +full:- +full:ext
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
206 struct clk *refclk; member
214 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
216 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
224 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
225 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
226 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
228 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
233 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
236 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
237 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
239 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
240 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
248 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
252 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
254 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
258 switch (priv->type) { in rockchip_combphy_init()
264 if (priv->cfg->combphy_cfg) in rockchip_combphy_init()
265 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_init()
268 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_init()
269 ret = -EINVAL; in rockchip_combphy_init()
274 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); in rockchip_combphy_init()
278 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
282 if (priv->type == PHY_TYPE_USB3) { in rockchip_combphy_init()
285 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
288 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
294 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
303 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
304 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
319 if (args->args_count != 1) { in rockchip_combphy_xlate()
321 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
324 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
326 args->args[0], priv->type); in rockchip_combphy_xlate()
328 priv->type = args->args[0]; in rockchip_combphy_xlate()
330 return priv->phy; in rockchip_combphy_xlate()
337 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_combphy_parse_dt()
338 if (priv->num_clks < 1) in rockchip_combphy_parse_dt()
339 return -EINVAL; in rockchip_combphy_parse_dt()
341 priv->refclk = NULL; in rockchip_combphy_parse_dt()
342 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
343 if (!strncmp(priv->clks[i].id, "ref", 3)) { in rockchip_combphy_parse_dt()
344 priv->refclk = priv->clks[i].clk; in rockchip_combphy_parse_dt()
349 if (!priv->refclk) { in rockchip_combphy_parse_dt()
350 dev_err(dev, "no refclk found\n"); in rockchip_combphy_parse_dt()
351 return -EINVAL; in rockchip_combphy_parse_dt()
354 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
355 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
356 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
357 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
360 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
361 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
362 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
363 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
366 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); in rockchip_combphy_parse_dt()
368 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); in rockchip_combphy_parse_dt()
370 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); in rockchip_combphy_parse_dt()
372 if (PTR_ERR(priv->phy_rst) == -ENOENT) in rockchip_combphy_parse_dt()
373 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); in rockchip_combphy_parse_dt()
374 if (IS_ERR(priv->phy_rst)) in rockchip_combphy_parse_dt()
375 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); in rockchip_combphy_parse_dt()
383 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
392 return -EINVAL; in rockchip_combphy_probe()
397 return -ENOMEM; in rockchip_combphy_probe()
399 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
400 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
401 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
405 /* find the phy-id from the io address */ in rockchip_combphy_probe()
406 priv->id = -ENODEV; in rockchip_combphy_probe()
407 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
408 if (res->start == phy_cfg->phy_ids[id]) { in rockchip_combphy_probe()
409 priv->id = id; in rockchip_combphy_probe()
414 priv->dev = dev; in rockchip_combphy_probe()
415 priv->type = PHY_NONE; in rockchip_combphy_probe()
416 priv->cfg = phy_cfg; in rockchip_combphy_probe()
422 ret = reset_control_assert(priv->phy_rst); in rockchip_combphy_probe()
428 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); in rockchip_combphy_probe()
429 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
431 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
435 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
444 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3528_combphy_cfg()
452 switch (priv->type) { in rk3528_combphy_cfg()
454 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3528_combphy_cfg()
455 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3528_combphy_cfg()
456 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3528_combphy_cfg()
457 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3528_combphy_cfg()
478 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3528_combphy_cfg()
479 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3528_combphy_cfg()
480 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3528_combphy_cfg()
481 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); in rk3528_combphy_cfg()
484 dev_err(priv->dev, "incompatible PHY type\n"); in rk3528_combphy_cfg()
485 return -EINVAL; in rk3528_combphy_cfg()
488 rate = clk_get_rate(priv->refclk); in rk3528_combphy_cfg()
492 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3528_combphy_cfg()
493 if (priv->type == PHY_TYPE_USB3) { in rk3528_combphy_cfg()
498 } else if (priv->type == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
505 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3528_combphy_cfg()
506 if (priv->type == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
513 writel(0x570804f0, priv->mmio + RK3528_PHYREG42); in rk3528_combphy_cfg()
517 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3528_combphy_cfg()
518 return -EINVAL; in rk3528_combphy_cfg()
521 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { in rk3528_combphy_cfg()
522 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3528_combphy_cfg()
524 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3528_combphy_cfg()
546 if (priv->type == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
547 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) in rk3528_combphy_cfg()
556 /* pipe-phy-grf */
573 /* pipe-grf */
588 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg()
592 switch (priv->type) { in rk3562_combphy_cfg()
598 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
599 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
600 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
601 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
618 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3562_combphy_cfg()
625 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3562_combphy_cfg()
628 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3562_combphy_cfg()
630 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
631 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
632 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
633 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
636 dev_err(priv->dev, "incompatible PHY type\n"); in rk3562_combphy_cfg()
637 return -EINVAL; in rk3562_combphy_cfg()
640 rate = clk_get_rate(priv->refclk); in rk3562_combphy_cfg()
644 if (priv->type == PHY_TYPE_USB3) { in rk3562_combphy_cfg()
651 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3562_combphy_cfg()
655 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3562_combphy_cfg()
658 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
659 if (priv->type == PHY_TYPE_PCIE) { in rk3562_combphy_cfg()
667 writel(0x4, priv->mmio + RK3568_PHYREG12); in rk3562_combphy_cfg()
673 writel(0x32, priv->mmio + RK3568_PHYREG18); in rk3562_combphy_cfg()
674 writel(0xf0, priv->mmio + RK3568_PHYREG11); in rk3562_combphy_cfg()
678 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3562_combphy_cfg()
679 return -EINVAL; in rk3562_combphy_cfg()
682 if (priv->ext_refclk) { in rk3562_combphy_cfg()
683 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3562_combphy_cfg()
684 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3562_combphy_cfg()
690 val = readl(priv->mmio + RK3568_PHYREG14); in rk3562_combphy_cfg()
692 writel(val, priv->mmio + RK3568_PHYREG14); in rk3562_combphy_cfg()
696 if (priv->enable_ssc) { in rk3562_combphy_cfg()
697 val = readl(priv->mmio + RK3568_PHYREG8); in rk3562_combphy_cfg()
699 writel(val, priv->mmio + RK3568_PHYREG8); in rk3562_combphy_cfg()
706 /* pipe-phy-grf */
739 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
743 switch (priv->type) { in rk3568_combphy_cfg()
750 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
751 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
752 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
753 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
762 val = readl(priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
764 writel(val, priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
771 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3568_combphy_cfg()
778 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3568_combphy_cfg()
779 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3568_combphy_cfg()
781 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
782 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
783 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
784 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
785 switch (priv->id) { in rk3568_combphy_cfg()
787 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); in rk3568_combphy_cfg()
790 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); in rk3568_combphy_cfg()
797 val = readl(priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
799 writel(val, priv->mmio + RK3568_PHYREG15); in rk3568_combphy_cfg()
806 writel(val, priv->mmio + RK3568_PHYREG7); in rk3568_combphy_cfg()
808 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
809 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
810 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
811 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
812 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
816 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
817 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
818 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
819 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
823 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
824 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
825 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
826 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
827 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
831 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
832 return -EINVAL; in rk3568_combphy_cfg()
835 rate = clk_get_rate(priv->refclk); in rk3568_combphy_cfg()
839 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
845 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3568_combphy_cfg()
850 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
854 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
855 if (priv->type == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
862 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3568_combphy_cfg()
868 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3568_combphy_cfg()
869 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3568_combphy_cfg()
870 } else if (priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
881 dev_err(priv->dev, "unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
882 return -EINVAL; in rk3568_combphy_cfg()
885 if (priv->ext_refclk) { in rk3568_combphy_cfg()
886 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
887 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3568_combphy_cfg()
893 val = readl(priv->mmio + RK3568_PHYREG14); in rk3568_combphy_cfg()
895 writel(val, priv->mmio + RK3568_PHYREG14); in rk3568_combphy_cfg()
899 if (priv->enable_ssc) { in rk3568_combphy_cfg()
900 val = readl(priv->mmio + RK3568_PHYREG8); in rk3568_combphy_cfg()
902 writel(val, priv->mmio + RK3568_PHYREG8); in rk3568_combphy_cfg()
909 /* pipe-phy-grf */
936 /* pipe-grf */
956 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3576_combphy_cfg()
960 switch (priv->type) { in rk3576_combphy_cfg()
966 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3576_combphy_cfg()
967 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3576_combphy_cfg()
968 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3576_combphy_cfg()
969 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3576_combphy_cfg()
978 val = readl(priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
980 writel(val, priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
987 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
994 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3576_combphy_cfg()
997 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1000 writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21); in rk3576_combphy_cfg()
1002 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3576_combphy_cfg()
1003 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3576_combphy_cfg()
1004 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3576_combphy_cfg()
1009 val = readl(priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1011 writel(val, priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1016 writel(val, priv->mmio + RK3568_PHYREG7); in rk3576_combphy_cfg()
1018 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3576_combphy_cfg()
1019 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3576_combphy_cfg()
1020 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3576_combphy_cfg()
1021 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3576_combphy_cfg()
1022 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3576_combphy_cfg()
1023 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3576_combphy_cfg()
1027 dev_err(priv->dev, "incompatible PHY type\n"); in rk3576_combphy_cfg()
1028 return -EINVAL; in rk3576_combphy_cfg()
1031 rate = clk_get_rate(priv->refclk); in rk3576_combphy_cfg()
1035 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3576_combphy_cfg()
1036 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
1043 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3576_combphy_cfg()
1044 } else if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
1052 writel(0x00, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1060 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1061 writel(0x02, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1062 writel(0x57, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1064 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3576_combphy_cfg()
1069 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3576_combphy_cfg()
1073 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3576_combphy_cfg()
1074 if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
1076 writel(0xc0, priv->mmio + RK3576_PHYREG30); in rk3576_combphy_cfg()
1085 writel(0x4c, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1095 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1096 writel(0x43, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1097 writel(0x88, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1098 writel(0x56, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1099 } else if (priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
1116 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3576_combphy_cfg()
1117 return -EINVAL; in rk3576_combphy_cfg()
1120 if (priv->ext_refclk) { in rk3576_combphy_cfg()
1121 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3576_combphy_cfg()
1122 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3576_combphy_cfg()
1129 writel(0x0c, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1139 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1140 writel(0x43, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1141 writel(0x88, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1142 writel(0x56, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1146 if (priv->enable_ssc) { in rk3576_combphy_cfg()
1147 val = readl(priv->mmio + RK3568_PHYREG8); in rk3576_combphy_cfg()
1149 writel(val, priv->mmio + RK3568_PHYREG8); in rk3576_combphy_cfg()
1151 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { in rk3576_combphy_cfg()
1153 writel(0x00, priv->mmio + RK3576_PHYREG17); in rk3576_combphy_cfg()
1154 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3576_combphy_cfg()
1157 writel(0x00, priv->mmio + RK3588_PHYREG27); in rk3576_combphy_cfg()
1166 writel(0x90, priv->mmio + RK3568_PHYREG11); in rk3576_combphy_cfg()
1167 writel(0x02, priv->mmio + RK3568_PHYREG12); in rk3576_combphy_cfg()
1168 writel(0x08, priv->mmio + RK3568_PHYREG13); in rk3576_combphy_cfg()
1169 writel(0x57, priv->mmio + RK3568_PHYREG14); in rk3576_combphy_cfg()
1170 writel(0x40, priv->mmio + RK3568_PHYREG15); in rk3576_combphy_cfg()
1172 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3576_combphy_cfg()
1176 writel(val, priv->mmio + RK3568_PHYREG33); in rk3576_combphy_cfg()
1184 /* pipe-phy-grf */
1208 /* php-grf */
1225 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
1229 switch (priv->type) { in rk3588_combphy_cfg()
1231 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
1232 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
1233 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
1234 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
1235 switch (priv->id) { in rk3588_combphy_cfg()
1237 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); in rk3588_combphy_cfg()
1240 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); in rk3588_combphy_cfg()
1250 val = readl(priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1252 writel(val, priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1259 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3588_combphy_cfg()
1266 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3588_combphy_cfg()
1267 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3588_combphy_cfg()
1269 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
1270 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
1271 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
1275 val = readl(priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1277 writel(val, priv->mmio + RK3568_PHYREG15); in rk3588_combphy_cfg()
1284 writel(val, priv->mmio + RK3568_PHYREG7); in rk3588_combphy_cfg()
1286 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
1287 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
1288 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
1289 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
1290 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
1291 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
1296 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
1297 return -EINVAL; in rk3588_combphy_cfg()
1300 rate = clk_get_rate(priv->refclk); in rk3588_combphy_cfg()
1304 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1310 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); in rk3588_combphy_cfg()
1315 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3588_combphy_cfg()
1318 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
1319 if (priv->type == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
1326 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3588_combphy_cfg()
1329 writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27); in rk3588_combphy_cfg()
1332 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3588_combphy_cfg()
1333 } else if (priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1343 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3588_combphy_cfg()
1344 return -EINVAL; in rk3588_combphy_cfg()
1347 if (priv->ext_refclk) { in rk3588_combphy_cfg()
1348 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3588_combphy_cfg()
1349 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3588_combphy_cfg()
1355 val = readl(priv->mmio + RK3568_PHYREG14); in rk3588_combphy_cfg()
1357 writel(val, priv->mmio + RK3568_PHYREG14); in rk3588_combphy_cfg()
1361 if (priv->enable_ssc) { in rk3588_combphy_cfg()
1362 val = readl(priv->mmio + RK3568_PHYREG8); in rk3588_combphy_cfg()
1364 writel(val, priv->mmio + RK3568_PHYREG8); in rk3588_combphy_cfg()
1371 /* pipe-phy-grf */
1392 /* pipe-grf */
1412 .compatible = "rockchip,rk3528-naneng-combphy",
1416 .compatible = "rockchip,rk3562-naneng-combphy",
1420 .compatible = "rockchip,rk3568-naneng-combphy",
1424 .compatible = "rockchip,rk3576-naneng-combphy",
1428 .compatible = "rockchip,rk3588-naneng-combphy",
1438 .name = "rockchip-naneng-combphy",