Lines Matching +full:no +full:- +full:spread +full:- +full:spectrum
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
171 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
173 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
181 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
182 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
183 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
185 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
190 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
193 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
194 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
196 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
197 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
205 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
209 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
211 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
215 switch (priv->type) { in rockchip_combphy_init()
221 if (priv->cfg->combphy_cfg) in rockchip_combphy_init()
222 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_init()
225 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_init()
226 ret = -EINVAL; in rockchip_combphy_init()
231 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); in rockchip_combphy_init()
235 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
239 if (priv->type == PHY_TYPE_USB3) { in rockchip_combphy_init()
242 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
245 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
251 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
260 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
261 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
276 if (args->args_count != 1) { in rockchip_combphy_xlate()
278 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
281 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
283 args->args[0], priv->type); in rockchip_combphy_xlate()
285 priv->type = args->args[0]; in rockchip_combphy_xlate()
287 return priv->phy; in rockchip_combphy_xlate()
294 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_combphy_parse_dt()
295 if (priv->num_clks < 1) in rockchip_combphy_parse_dt()
296 return -EINVAL; in rockchip_combphy_parse_dt()
298 priv->refclk = NULL; in rockchip_combphy_parse_dt()
299 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
300 if (!strncmp(priv->clks[i].id, "ref", 3)) { in rockchip_combphy_parse_dt()
301 priv->refclk = priv->clks[i].clk; in rockchip_combphy_parse_dt()
306 if (!priv->refclk) { in rockchip_combphy_parse_dt()
307 dev_err(dev, "no refclk found\n"); in rockchip_combphy_parse_dt()
308 return -EINVAL; in rockchip_combphy_parse_dt()
311 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
312 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
313 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
314 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
317 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
318 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
319 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
320 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
323 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); in rockchip_combphy_parse_dt()
325 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); in rockchip_combphy_parse_dt()
327 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); in rockchip_combphy_parse_dt()
329 if (PTR_ERR(priv->phy_rst) == -ENOENT) in rockchip_combphy_parse_dt()
330 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); in rockchip_combphy_parse_dt()
331 if (IS_ERR(priv->phy_rst)) in rockchip_combphy_parse_dt()
332 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); in rockchip_combphy_parse_dt()
340 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
348 dev_err(dev, "no OF match data provided\n"); in rockchip_combphy_probe()
349 return -EINVAL; in rockchip_combphy_probe()
354 return -ENOMEM; in rockchip_combphy_probe()
356 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
357 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
358 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
362 /* find the phy-id from the io address */ in rockchip_combphy_probe()
363 priv->id = -ENODEV; in rockchip_combphy_probe()
364 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
365 if (res->start == phy_cfg->phy_ids[id]) { in rockchip_combphy_probe()
366 priv->id = id; in rockchip_combphy_probe()
371 priv->dev = dev; in rockchip_combphy_probe()
372 priv->type = PHY_NONE; in rockchip_combphy_probe()
373 priv->cfg = phy_cfg; in rockchip_combphy_probe()
379 ret = reset_control_assert(priv->phy_rst); in rockchip_combphy_probe()
385 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); in rockchip_combphy_probe()
386 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
388 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
392 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
401 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg()
405 switch (priv->type) { in rk3562_combphy_cfg()
407 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
412 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
413 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
414 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
415 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
418 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
431 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3562_combphy_cfg()
438 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3562_combphy_cfg()
441 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3562_combphy_cfg()
443 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
444 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
445 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
446 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
449 dev_err(priv->dev, "incompatible PHY type\n"); in rk3562_combphy_cfg()
450 return -EINVAL; in rk3562_combphy_cfg()
453 rate = clk_get_rate(priv->refclk); in rk3562_combphy_cfg()
457 if (priv->type == PHY_TYPE_USB3) { in rk3562_combphy_cfg()
463 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3562_combphy_cfg()
467 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3562_combphy_cfg()
470 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
471 if (priv->type == PHY_TYPE_PCIE) { in rk3562_combphy_cfg()
478 writel(0x4, priv->mmio + PHYREG12); in rk3562_combphy_cfg()
484 writel(0x32, priv->mmio + PHYREG18); in rk3562_combphy_cfg()
485 writel(0xf0, priv->mmio + PHYREG11); in rk3562_combphy_cfg()
489 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3562_combphy_cfg()
490 return -EINVAL; in rk3562_combphy_cfg()
493 if (priv->ext_refclk) { in rk3562_combphy_cfg()
494 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3562_combphy_cfg()
495 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3562_combphy_cfg()
500 val = readl(priv->mmio + PHYREG14); in rk3562_combphy_cfg()
502 writel(val, priv->mmio + PHYREG14); in rk3562_combphy_cfg()
506 if (priv->enable_ssc) { in rk3562_combphy_cfg()
507 val = readl(priv->mmio + PHYREG8); in rk3562_combphy_cfg()
509 writel(val, priv->mmio + PHYREG8); in rk3562_combphy_cfg()
516 /* pipe-phy-grf */
549 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
553 switch (priv->type) { in rk3568_combphy_cfg()
555 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
560 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
561 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
562 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
563 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
567 /* Set SSC downward spread spectrum. */ in rk3568_combphy_cfg()
573 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
575 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
583 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
590 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
591 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
593 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
594 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
595 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
596 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
601 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
603 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
610 writel(val, priv->mmio + PHYREG7); in rk3568_combphy_cfg()
612 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
613 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
614 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
615 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
616 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
620 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
621 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
622 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
623 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
627 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
628 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
629 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
630 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
631 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
635 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
636 return -EINVAL; in rk3568_combphy_cfg()
639 rate = clk_get_rate(priv->refclk); in rk3568_combphy_cfg()
643 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
649 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3568_combphy_cfg()
654 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
658 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
659 if (priv->type == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
666 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
672 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
673 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
674 } else if (priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
675 /* downward spread spectrum +500ppm */ in rk3568_combphy_cfg()
683 dev_err(priv->dev, "unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
684 return -EINVAL; in rk3568_combphy_cfg()
687 if (priv->ext_refclk) { in rk3568_combphy_cfg()
688 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
689 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3568_combphy_cfg()
694 val = readl(priv->mmio + PHYREG14); in rk3568_combphy_cfg()
696 writel(val, priv->mmio + PHYREG14); in rk3568_combphy_cfg()
700 if (priv->enable_ssc) { in rk3568_combphy_cfg()
701 val = readl(priv->mmio + PHYREG8); in rk3568_combphy_cfg()
703 writel(val, priv->mmio + PHYREG8); in rk3568_combphy_cfg()
710 /* pipe-phy-grf */
737 /* pipe-grf */
755 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3576_combphy_cfg()
759 switch (priv->type) { in rk3576_combphy_cfg()
761 /* Set SSC downward spread spectrum */ in rk3576_combphy_cfg()
765 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3576_combphy_cfg()
766 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3576_combphy_cfg()
767 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3576_combphy_cfg()
768 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3576_combphy_cfg()
772 /* Set SSC downward spread spectrum */ in rk3576_combphy_cfg()
777 val = readl(priv->mmio + PHYREG15); in rk3576_combphy_cfg()
779 writel(val, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
785 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
792 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3576_combphy_cfg()
795 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
798 writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21); in rk3576_combphy_cfg()
800 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3576_combphy_cfg()
801 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3576_combphy_cfg()
802 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3576_combphy_cfg()
807 val = readl(priv->mmio + PHYREG15); in rk3576_combphy_cfg()
809 writel(val, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
814 writel(val, priv->mmio + PHYREG7); in rk3576_combphy_cfg()
816 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3576_combphy_cfg()
817 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3576_combphy_cfg()
818 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3576_combphy_cfg()
819 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3576_combphy_cfg()
820 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3576_combphy_cfg()
821 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3576_combphy_cfg()
825 dev_err(priv->dev, "incompatible PHY type\n"); in rk3576_combphy_cfg()
826 return -EINVAL; in rk3576_combphy_cfg()
829 rate = clk_get_rate(priv->refclk); in rk3576_combphy_cfg()
833 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); in rk3576_combphy_cfg()
834 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
840 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3576_combphy_cfg()
841 } else if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
848 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
856 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
857 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
858 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
860 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3576_combphy_cfg()
865 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3576_combphy_cfg()
869 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3576_combphy_cfg()
870 if (priv->type == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
872 writel(0xc0, priv->mmio + PHYREG30); in rk3576_combphy_cfg()
880 writel(0x4c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
890 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
891 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
892 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
893 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
894 } else if (priv->type == PHY_TYPE_SATA) { in rk3576_combphy_cfg()
895 /* downward spread spectrum +500ppm */ in rk3576_combphy_cfg()
908 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3576_combphy_cfg()
909 return -EINVAL; in rk3576_combphy_cfg()
912 if (priv->ext_refclk) { in rk3576_combphy_cfg()
913 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3576_combphy_cfg()
914 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3576_combphy_cfg()
920 writel(0x0c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
930 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
931 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
932 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
933 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
937 if (priv->enable_ssc) { in rk3576_combphy_cfg()
938 val = readl(priv->mmio + PHYREG8); in rk3576_combphy_cfg()
940 writel(val, priv->mmio + PHYREG8); in rk3576_combphy_cfg()
942 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { in rk3576_combphy_cfg()
944 writel(0x00, priv->mmio + PHYREG17); in rk3576_combphy_cfg()
945 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3576_combphy_cfg()
948 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
957 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
958 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
959 writel(0x08, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
960 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
961 writel(0x40, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
963 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3576_combphy_cfg()
966 writel(val, priv->mmio + PHYREG33); in rk3576_combphy_cfg()
974 /* pipe-phy-grf */
998 /* php-grf */
1015 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
1019 switch (priv->type) { in rk3588_combphy_cfg()
1021 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
1022 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
1023 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
1024 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
1025 switch (priv->id) { in rk3588_combphy_cfg()
1027 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); in rk3588_combphy_cfg()
1030 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); in rk3588_combphy_cfg()
1035 /* Set SSC downward spread spectrum */ in rk3588_combphy_cfg()
1041 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
1043 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
1051 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
1058 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3588_combphy_cfg()
1059 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
1061 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
1062 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
1063 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
1067 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
1069 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
1076 writel(val, priv->mmio + PHYREG7); in rk3588_combphy_cfg()
1078 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
1079 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
1080 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
1081 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
1082 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
1083 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
1088 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
1089 return -EINVAL; in rk3588_combphy_cfg()
1092 rate = clk_get_rate(priv->refclk); in rk3588_combphy_cfg()
1096 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1102 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3588_combphy_cfg()
1107 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3588_combphy_cfg()
1110 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
1111 if (priv->type == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
1118 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
1121 writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); in rk3588_combphy_cfg()
1124 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
1125 } else if (priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
1126 /* downward spread spectrum +500ppm */ in rk3588_combphy_cfg()
1133 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3588_combphy_cfg()
1134 return -EINVAL; in rk3588_combphy_cfg()
1137 if (priv->ext_refclk) { in rk3588_combphy_cfg()
1138 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3588_combphy_cfg()
1139 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3588_combphy_cfg()
1144 val = readl(priv->mmio + PHYREG14); in rk3588_combphy_cfg()
1146 writel(val, priv->mmio + PHYREG14); in rk3588_combphy_cfg()
1150 if (priv->enable_ssc) { in rk3588_combphy_cfg()
1151 val = readl(priv->mmio + PHYREG8); in rk3588_combphy_cfg()
1153 writel(val, priv->mmio + PHYREG8); in rk3588_combphy_cfg()
1160 /* pipe-phy-grf */
1181 /* pipe-grf */
1201 .compatible = "rockchip,rk3562-naneng-combphy",
1205 .compatible = "rockchip,rk3568-naneng-combphy",
1209 .compatible = "rockchip,rk3576-naneng-combphy",
1213 .compatible = "rockchip,rk3588-naneng-combphy",
1223 .name = "rockchip-naneng-combphy",