Lines Matching +full:fine +full:- +full:tuning
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
156 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
158 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
166 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
167 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
168 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
170 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
175 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
178 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
179 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
181 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
182 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
190 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
194 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rockchip_combphy_init()
196 dev_err(priv->dev, "failed to enable clks\n"); in rockchip_combphy_init()
200 switch (priv->type) { in rockchip_combphy_init()
206 if (priv->cfg->combphy_cfg) in rockchip_combphy_init()
207 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_init()
210 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_init()
211 ret = -EINVAL; in rockchip_combphy_init()
216 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); in rockchip_combphy_init()
220 ret = reset_control_deassert(priv->phy_rst); in rockchip_combphy_init()
224 if (priv->type == PHY_TYPE_USB3) { in rockchip_combphy_init()
227 val == cfg->pipe_phy_status.enable, in rockchip_combphy_init()
230 dev_warn(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_init()
236 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_init()
245 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rockchip_combphy_exit()
246 reset_control_assert(priv->phy_rst); in rockchip_combphy_exit()
261 if (args->args_count != 1) { in rockchip_combphy_xlate()
263 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
266 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
268 args->args[0], priv->type); in rockchip_combphy_xlate()
270 priv->type = args->args[0]; in rockchip_combphy_xlate()
272 return priv->phy; in rockchip_combphy_xlate()
279 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_combphy_parse_dt()
280 if (priv->num_clks < 1) in rockchip_combphy_parse_dt()
281 return -EINVAL; in rockchip_combphy_parse_dt()
283 priv->refclk = NULL; in rockchip_combphy_parse_dt()
284 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
285 if (!strncmp(priv->clks[i].id, "ref", 3)) { in rockchip_combphy_parse_dt()
286 priv->refclk = priv->clks[i].clk; in rockchip_combphy_parse_dt()
291 if (!priv->refclk) { in rockchip_combphy_parse_dt()
293 return -EINVAL; in rockchip_combphy_parse_dt()
296 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); in rockchip_combphy_parse_dt()
297 if (IS_ERR(priv->pipe_grf)) { in rockchip_combphy_parse_dt()
298 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); in rockchip_combphy_parse_dt()
299 return PTR_ERR(priv->pipe_grf); in rockchip_combphy_parse_dt()
302 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); in rockchip_combphy_parse_dt()
303 if (IS_ERR(priv->phy_grf)) { in rockchip_combphy_parse_dt()
304 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
305 return PTR_ERR(priv->phy_grf); in rockchip_combphy_parse_dt()
308 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); in rockchip_combphy_parse_dt()
310 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); in rockchip_combphy_parse_dt()
312 priv->phy_rst = devm_reset_control_get(dev, "phy"); in rockchip_combphy_parse_dt()
313 if (IS_ERR(priv->phy_rst)) in rockchip_combphy_parse_dt()
314 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); in rockchip_combphy_parse_dt()
322 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
331 return -EINVAL; in rockchip_combphy_probe()
336 return -ENOMEM; in rockchip_combphy_probe()
338 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
339 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
340 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
344 /* find the phy-id from the io address */ in rockchip_combphy_probe()
345 priv->id = -ENODEV; in rockchip_combphy_probe()
346 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
347 if (res->start == phy_cfg->phy_ids[id]) { in rockchip_combphy_probe()
348 priv->id = id; in rockchip_combphy_probe()
353 priv->dev = dev; in rockchip_combphy_probe()
354 priv->type = PHY_NONE; in rockchip_combphy_probe()
355 priv->cfg = phy_cfg; in rockchip_combphy_probe()
361 ret = reset_control_assert(priv->phy_rst); in rockchip_combphy_probe()
367 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); in rockchip_combphy_probe()
368 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
370 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
374 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
383 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
387 switch (priv->type) { in rk3568_combphy_cfg()
394 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
395 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
396 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
397 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
407 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
409 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
411 /* Set PLL KVCO fine tuning signals. */ in rk3568_combphy_cfg()
417 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
424 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
425 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
427 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
428 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
429 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
430 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
435 val = readl(priv->mmio + PHYREG15); in rk3568_combphy_cfg()
437 writel(val, priv->mmio + PHYREG15); in rk3568_combphy_cfg()
444 writel(val, priv->mmio + PHYREG7); in rk3568_combphy_cfg()
446 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
447 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
448 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
449 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
450 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
454 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
455 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
456 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
457 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
461 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
462 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
463 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
464 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
465 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
469 dev_err(priv->dev, "incompatible PHY type\n"); in rk3568_combphy_cfg()
470 return -EINVAL; in rk3568_combphy_cfg()
473 rate = clk_get_rate(priv->refclk); in rk3568_combphy_cfg()
477 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
483 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3568_combphy_cfg()
488 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
492 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3568_combphy_cfg()
493 if (priv->type == PHY_TYPE_PCIE) { in rk3568_combphy_cfg()
494 /* PLL KVCO fine tuning. */ in rk3568_combphy_cfg()
500 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3568_combphy_cfg()
506 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3568_combphy_cfg()
507 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3568_combphy_cfg()
508 } else if (priv->type == PHY_TYPE_SATA) { in rk3568_combphy_cfg()
517 dev_err(priv->dev, "unsupported rate: %lu\n", rate); in rk3568_combphy_cfg()
518 return -EINVAL; in rk3568_combphy_cfg()
521 if (priv->ext_refclk) { in rk3568_combphy_cfg()
522 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3568_combphy_cfg()
523 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3568_combphy_cfg()
528 val = readl(priv->mmio + PHYREG14); in rk3568_combphy_cfg()
530 writel(val, priv->mmio + PHYREG14); in rk3568_combphy_cfg()
534 if (priv->enable_ssc) { in rk3568_combphy_cfg()
535 val = readl(priv->mmio + PHYREG8); in rk3568_combphy_cfg()
537 writel(val, priv->mmio + PHYREG8); in rk3568_combphy_cfg()
544 /* pipe-phy-grf */
571 /* pipe-grf */
589 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
593 switch (priv->type) { in rk3588_combphy_cfg()
595 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
596 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
597 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
598 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
599 switch (priv->id) { in rk3588_combphy_cfg()
601 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); in rk3588_combphy_cfg()
604 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); in rk3588_combphy_cfg()
615 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
617 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
619 /* Set PLL KVCO fine tuning signals. */ in rk3588_combphy_cfg()
625 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
632 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); in rk3588_combphy_cfg()
633 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
635 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
636 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
637 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
641 val = readl(priv->mmio + PHYREG15); in rk3588_combphy_cfg()
643 writel(val, priv->mmio + PHYREG15); in rk3588_combphy_cfg()
650 writel(val, priv->mmio + PHYREG7); in rk3588_combphy_cfg()
652 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
653 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
654 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
655 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
656 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
657 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
662 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
663 return -EINVAL; in rk3588_combphy_cfg()
666 rate = clk_get_rate(priv->refclk); in rk3588_combphy_cfg()
670 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
676 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); in rk3588_combphy_cfg()
681 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3588_combphy_cfg()
684 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
685 if (priv->type == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
686 /* PLL KVCO fine tuning. */ in rk3588_combphy_cfg()
692 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); in rk3588_combphy_cfg()
695 writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); in rk3588_combphy_cfg()
698 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); in rk3588_combphy_cfg()
699 } else if (priv->type == PHY_TYPE_SATA) { in rk3588_combphy_cfg()
707 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk3588_combphy_cfg()
708 return -EINVAL; in rk3588_combphy_cfg()
711 if (priv->ext_refclk) { in rk3588_combphy_cfg()
712 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3588_combphy_cfg()
713 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { in rk3588_combphy_cfg()
718 val = readl(priv->mmio + PHYREG14); in rk3588_combphy_cfg()
720 writel(val, priv->mmio + PHYREG14); in rk3588_combphy_cfg()
724 if (priv->enable_ssc) { in rk3588_combphy_cfg()
725 val = readl(priv->mmio + PHYREG8); in rk3588_combphy_cfg()
727 writel(val, priv->mmio + PHYREG8); in rk3588_combphy_cfg()
734 /* pipe-phy-grf */
755 /* pipe-grf */
775 .compatible = "rockchip,rk3568-naneng-combphy",
779 .compatible = "rockchip,rk3588-naneng-combphy",
789 .name = "rockchip-naneng-combphy",