Lines Matching +full:0 +full:x3e4
27 #define CDR_CTRL_REG_1 0x80
28 #define CDR_CTRL_REG_2 0x84
29 #define CDR_CTRL_REG_3 0x88
30 #define CDR_CTRL_REG_4 0x8c
31 #define CDR_CTRL_REG_5 0x90
32 #define CDR_CTRL_REG_6 0x94
33 #define CDR_CTRL_REG_7 0x98
34 #define SSCG_CTRL_REG_1 0x9c
35 #define SSCG_CTRL_REG_2 0xa0
36 #define SSCG_CTRL_REG_3 0xa4
37 #define SSCG_CTRL_REG_4 0xa8
38 #define SSCG_CTRL_REG_5 0xac
39 #define SSCG_CTRL_REG_6 0xb0
40 #define PCS_INTERNAL_CONTROL_2 0x2d8
42 #define PHY_CFG_PLLCFG 0x220
43 #define PHY_CFG_EIOS_DTCT_REG 0x3e4
44 #define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
81 .val = 0x1cb9,
84 .val = 0x023a,
87 .val = 0xd360,
90 .val = 0x1,
93 .val = 0xeb,
96 .val = 0x3f9,
99 .val = 0x1c9,
102 .val = 0x419,
105 .val = 0x200,
108 .val = 0xf101,
115 .val = 0x30,
118 .val = 0x53ef,
121 .val = 0xcf,
126 .lane_offset = 0x800,
134 .lane_offset = 0x800,
148 for (lane = 0; lane < phy->lanes; lane++) { in qcom_uniphy_pcie_init()
151 for (i = 0; i < data->init_seq_num; i++) in qcom_uniphy_pcie_init()
198 return 0; in qcom_uniphy_pcie_power_on()
206 phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in qcom_uniphy_pcie_get_resources()
211 if (phy->num_clks < 0) in qcom_uniphy_pcie_get_resources()
218 return 0; in qcom_uniphy_pcie_get_resources()
246 hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0, in phy_pipe_clk_register()
298 if (ret < 0) in qcom_uniphy_pcie_probe()
317 return 0; in qcom_uniphy_pcie_probe()